diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests/long/fs | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests/long/fs')
6 files changed, 5855 insertions, 5838 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index c7b42033d..0876dc614 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903503 # Number of seconds simulated -sim_ticks 1903503020500 # Number of ticks simulated -final_tick 1903503020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903548 # Number of seconds simulated +sim_ticks 1903548166500 # Number of ticks simulated +final_tick 1903548166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196271 # Simulator instruction rate (inst/s) -host_op_rate 196271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6657053225 # Simulator tick rate (ticks/s) -host_mem_usage 303260 # Number of bytes of host memory used -host_seconds 285.94 # Real time elapsed on the host -sim_insts 56121257 # Number of instructions simulated -sim_ops 56121257 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 882432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24721216 # Number of bytes read from this memory +host_inst_rate 123505 # Simulator instruction rate (inst/s) +host_op_rate 123505 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4187441182 # Simulator tick rate (ticks/s) +host_mem_usage 303204 # Number of bytes of host memory used +host_seconds 454.59 # Real time elapsed on the host +sim_insts 56143492 # Number of instructions simulated +sim_ops 56143492 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 879488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24796480 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 100416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 648960 # Number of bytes read from this memory -system.physmem.bytes_read::total 29002688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 882432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 100416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982848 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7936064 # Number of bytes written to this memory -system.physmem.bytes_written::total 7936064 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13788 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386269 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 101696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 559552 # Number of bytes read from this memory +system.physmem.bytes_read::total 28986880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 879488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 101696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7925376 # Number of bytes written to this memory +system.physmem.bytes_written::total 7925376 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387445 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10140 # Number of read requests responded to by this memory -system.physmem.num_reads::total 453167 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124001 # Number of write requests responded to by this memory -system.physmem.num_writes::total 124001 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 463583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12987222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 340929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15236481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 463583 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4169189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4169189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4169189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 463583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12987222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 340929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19405670 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 346253 # number of replacements -system.l2c.tagsinuse 65331.229324 # Cycle average of tags in use -system.l2c.total_refs 2603754 # Total number of references to valid blocks. -system.l2c.sampled_refs 411399 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.329024 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6380524000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53709.821247 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5286.136461 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6105.466815 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 198.491400 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 31.313401 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.819547 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080660 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093162 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003029 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000478 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996875 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 965065 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 779439 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 111820 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 39391 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1895715 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 831921 # number of Writeback hits -system.l2c.Writeback_hits::total 831921 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 73 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 245 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 28 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits +system.physmem.num_reads::cpu1.inst 1589 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8743 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452920 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123834 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123834 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 462026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13026453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1391961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 293952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15227815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 462026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53424 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4163475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4163475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4163475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 462026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13026453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1391961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 293952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19391291 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 346033 # number of replacements +system.l2c.tagsinuse 65330.743124 # Cycle average of tags in use +system.l2c.total_refs 2608063 # Total number of references to valid blocks. +system.l2c.sampled_refs 411178 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.342905 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6380526000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53708.225390 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5276.213951 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6113.589929 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 198.792297 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 33.921558 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.819522 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.080509 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.093286 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.003033 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000518 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996868 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 970913 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 780748 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 107670 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 39067 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1898398 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 832636 # number of Writeback hits +system.l2c.Writeback_hits::total 832636 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 238 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 165704 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 16093 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 181797 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 965065 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 945143 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 111820 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 55484 # number of demand (read+write) hits -system.l2c.demand_hits::total 2077512 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 965065 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1387261000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1941911500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 514448500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2456360000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3305512500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538108500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3843621000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259011 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014541 # 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mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165312 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165312 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41024.594193 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41433.078394 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42600.703262 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40591.650344 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41764.543151 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43467.944563 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41874.779301 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -348,14 +348,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.468001 # Cycle average of tags in use +system.iocache.tagsinuse 0.468369 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1712293423000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.468001 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.029250 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.029250 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1712293009000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.468369 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.029273 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.029273 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -366,12 +366,12 @@ system.iocache.overall_misses::tsunami.ide 41728 # system.iocache.overall_misses::total 41728 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21012998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21012998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7634627806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7634627806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7655640804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7655640804 # 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number of WriteReq accesses(hits+misses) @@ -390,17 +390,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119392.034091 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183736.710772 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183736.710772 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183465.318347 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183465.318347 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183465.318347 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183465.318347 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7744000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276451.550010 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 276451.550010 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 275789.105732 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 275789.105732 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 201643000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7100 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24752 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1090.704225 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8146.533613 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -416,12 +416,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41728 system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11860000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11860000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5473770000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5473770000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5485630000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5485630000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5485630000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5485630000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9326257976 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9326257976 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9338117976 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9338117976 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9338117976 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9338117976 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -432,12 +432,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131733.009241 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131733.009241 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131461.608512 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131461.608512 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131461.608512 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131461.608512 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224447.871968 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224447.871968 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9362822 # DTB read hits -system.cpu0.dtb.read_misses 32776 # DTB read misses -system.cpu0.dtb.read_acv 407 # DTB read access violations -system.cpu0.dtb.read_accesses 655429 # DTB read accesses -system.cpu0.dtb.write_hits 6177998 # DTB write hits -system.cpu0.dtb.write_misses 6927 # DTB write misses -system.cpu0.dtb.write_acv 263 # DTB write access violations -system.cpu0.dtb.write_accesses 211643 # DTB write accesses -system.cpu0.dtb.data_hits 15540820 # DTB hits -system.cpu0.dtb.data_misses 39703 # DTB misses -system.cpu0.dtb.data_acv 670 # DTB access violations -system.cpu0.dtb.data_accesses 867072 # DTB accesses -system.cpu0.itb.fetch_hits 1071612 # ITB hits -system.cpu0.itb.fetch_misses 26818 # ITB misses -system.cpu0.itb.fetch_acv 827 # ITB acv -system.cpu0.itb.fetch_accesses 1098430 # ITB accesses +system.cpu0.dtb.read_hits 9377828 # DTB read hits +system.cpu0.dtb.read_misses 33360 # DTB read misses +system.cpu0.dtb.read_acv 521 # DTB read access violations +system.cpu0.dtb.read_accesses 633373 # DTB read accesses +system.cpu0.dtb.write_hits 6221809 # DTB write hits +system.cpu0.dtb.write_misses 7167 # DTB write misses +system.cpu0.dtb.write_acv 341 # DTB write access violations +system.cpu0.dtb.write_accesses 216042 # DTB write accesses +system.cpu0.dtb.data_hits 15599637 # DTB hits +system.cpu0.dtb.data_misses 40527 # DTB misses +system.cpu0.dtb.data_acv 862 # DTB access violations +system.cpu0.dtb.data_accesses 849415 # DTB accesses +system.cpu0.itb.fetch_hits 1073423 # ITB hits +system.cpu0.itb.fetch_misses 26403 # ITB misses +system.cpu0.itb.fetch_acv 1051 # ITB acv +system.cpu0.itb.fetch_accesses 1099826 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,277 +483,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 120285579 # number of cpu cycles simulated +system.cpu0.numCycles 120667689 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13328375 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11156715 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 403301 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9703007 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5627426 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13362893 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11185412 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 402804 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 9622475 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5627170 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 881916 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 36485 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 30082863 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 67323144 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13328375 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6509342 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12704270 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1925792 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 41150259 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29396 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 190626 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 307717 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 171 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8274450 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 278264 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 85724819 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.785340 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.113356 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 884758 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 37477 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 30221705 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 67571030 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13362893 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6511928 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12734942 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1928304 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 41309111 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 28714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 205220 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 305503 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8304621 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 277902 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 86063714 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.785128 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.113854 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 73020549 85.18% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 838460 0.98% 86.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1676934 1.96% 88.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 765061 0.89% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2646040 3.09% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 584012 0.68% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 626464 0.73% 93.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 965763 1.13% 94.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4601536 5.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 73328772 85.20% 85.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 837915 0.97% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1666262 1.94% 88.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 768356 0.89% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2658731 3.09% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 585060 0.68% 92.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 622966 0.72% 93.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 967713 1.12% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4627939 5.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 85724819 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.110806 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.559694 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 31004655 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 40959879 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11547285 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 992195 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1220804 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 569651 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 39042 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 66162079 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 119714 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1220804 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 32084617 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 16798713 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 20265121 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10859034 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4496528 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 62667463 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6952 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 714166 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1644224 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 41889226 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 75909055 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 75455060 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 453995 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36387256 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5501970 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1564601 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238699 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11969460 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9870474 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6474014 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1213478 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 815744 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55487857 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1996787 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54121133 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 111429 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6732221 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3352698 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1361171 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 85724819 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.631336 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.279357 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 86063714 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.110741 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.559976 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 31149327 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 41124977 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11584676 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 985581 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1219152 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 571369 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 39493 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 66407813 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 120728 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1219152 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 32233219 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 16872016 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 20344281 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10880828 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4514216 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 62880643 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6942 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 700700 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1661735 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 42005938 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 76144064 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 75702119 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 441945 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36517182 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5488748 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1574453 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 239002 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12018911 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9888186 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6523659 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1201517 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 824194 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 55665948 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1995313 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54317533 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 112244 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6696159 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3338542 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1358752 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 86063714 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.631132 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.280124 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 61209229 71.40% 71.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 11417613 13.32% 84.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5048858 5.89% 90.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3283375 3.83% 94.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2508461 2.93% 97.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1248570 1.46% 98.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 634570 0.74% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 321579 0.38% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52564 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 61486843 71.44% 71.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 11432526 13.28% 84.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5063556 5.88% 90.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3287093 3.82% 94.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2517985 2.93% 97.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1255115 1.46% 98.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 648079 0.75% 99.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 319509 0.37% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53008 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 85724819 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 86063714 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 72995 10.68% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 324242 47.46% 58.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 285988 41.86% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 73354 10.53% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 330176 47.38% 57.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 293358 42.10% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 4465 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37158612 68.66% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60272 0.11% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 18564 0.03% 68.81% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.81% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.81% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.81% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9761868 18.04% 86.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6247803 11.54% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 867318 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3296 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37287239 68.65% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60152 0.11% 68.76% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.76% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15662 0.03% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1646 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9781142 18.01% 86.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6293081 11.59% 98.39% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 875315 1.61% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54121133 # Type of FU issued -system.cpu0.iq.rate 0.449939 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 683225 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012624 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 194116788 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 63916247 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 52959668 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 644951 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 312925 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 303605 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 54462198 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 337695 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 568272 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54317533 # Type of FU issued +system.cpu0.iq.rate 0.450141 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 696889 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012830 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 194880881 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 64065914 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53156794 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 627031 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 303977 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 294706 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 54682626 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 328500 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 571695 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1280116 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2462 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12570 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 515440 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1271953 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2828 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12731 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 517788 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18537 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 100807 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18545 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 107284 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1220804 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 12124657 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 860720 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 60917526 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 643294 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9870474 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6474014 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1758330 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 617908 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 8871 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12570 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 212626 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 388253 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 600879 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 53642657 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9419598 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 478476 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1219152 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 12163042 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 861940 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61112544 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 659342 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9888186 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6523659 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1757966 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 617572 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 9941 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12731 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 210191 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 389993 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 600184 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 53834482 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9436308 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 483050 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3432882 # number of nop insts executed -system.cpu0.iew.exec_refs 15618436 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8560068 # Number of branches executed -system.cpu0.iew.exec_stores 6198838 # Number of stores executed -system.cpu0.iew.exec_rate 0.445961 # Inst execution rate -system.cpu0.iew.wb_sent 53356597 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53263273 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26352404 # num instructions producing a value -system.cpu0.iew.wb_consumers 35613133 # num instructions consuming a value +system.cpu0.iew.exec_nop 3451283 # number of nop insts executed +system.cpu0.iew.exec_refs 15679571 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8587439 # Number of branches executed +system.cpu0.iew.exec_stores 6243263 # Number of stores executed +system.cpu0.iew.exec_rate 0.446138 # Inst execution rate +system.cpu0.iew.wb_sent 53546468 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53451500 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26356174 # num instructions producing a value +system.cpu0.iew.wb_consumers 35593959 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.442807 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.739963 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.442964 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.740468 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7330810 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 635616 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 562628 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 84504015 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.633112 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.546448 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7303960 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 636561 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 562819 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 84844562 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.633202 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.547709 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 64274948 76.06% 76.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8494337 10.05% 86.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4620943 5.47% 91.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2493253 2.95% 94.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1382716 1.64% 96.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 578306 0.68% 96.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 482831 0.57% 97.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 448312 0.53% 97.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1728369 2.05% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 64556270 76.09% 76.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8510919 10.03% 86.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4635841 5.46% 91.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2494817 2.94% 94.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1390539 1.64% 96.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 576056 0.68% 96.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 484846 0.57% 97.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 456978 0.54% 97.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1738296 2.05% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 84504015 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53500498 # Number of instructions committed -system.cpu0.commit.committedOps 53500498 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 84844562 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 53723778 # Number of instructions committed +system.cpu0.commit.committedOps 53723778 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14548932 # Number of memory references committed -system.cpu0.commit.loads 8590358 # Number of loads committed -system.cpu0.commit.membars 216685 # Number of memory barriers committed -system.cpu0.commit.branches 8083038 # Number of branches committed -system.cpu0.commit.fp_insts 301061 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49495422 # Number of committed integer instructions. -system.cpu0.commit.function_calls 700509 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1728369 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14622104 # Number of memory references committed +system.cpu0.commit.loads 8616233 # Number of loads committed +system.cpu0.commit.membars 216543 # Number of memory barriers committed +system.cpu0.commit.branches 8113778 # Number of branches committed +system.cpu0.commit.fp_insts 292474 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49705714 # Number of committed integer instructions. +system.cpu0.commit.function_calls 703203 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1738296 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 143428116 # The number of ROB reads -system.cpu0.rob.rob_writes 122883641 # The number of ROB writes -system.cpu0.timesIdled 1359099 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 34560760 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3686357913 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50400239 # Number of Instructions Simulated -system.cpu0.committedOps 50400239 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 50400239 # Number of Instructions Simulated -system.cpu0.cpi 2.386607 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.386607 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.419005 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.419005 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 70355564 # number of integer regfile reads -system.cpu0.int_regfile_writes 38486142 # number of integer regfile writes -system.cpu0.fp_regfile_reads 150309 # number of floating regfile reads -system.cpu0.fp_regfile_writes 151918 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1870359 # number of misc regfile reads -system.cpu0.misc_regfile_writes 881938 # number of misc regfile writes +system.cpu0.rob.rob_reads 143945633 # The number of ROB reads +system.cpu0.rob.rob_writes 123274808 # The number of ROB writes +system.cpu0.timesIdled 1363780 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 34603975 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3686422279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 50608732 # Number of Instructions Simulated +system.cpu0.committedOps 50608732 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 50608732 # Number of Instructions Simulated +system.cpu0.cpi 2.384325 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.384325 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.419406 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.419406 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 70600527 # number of integer regfile reads +system.cpu0.int_regfile_writes 38607300 # number of integer regfile writes +system.cpu0.fp_regfile_reads 144193 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146198 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1863622 # number of misc regfile reads +system.cpu0.misc_regfile_writes 886886 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -785,245 +785,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 978272 # number of replacements -system.cpu0.icache.tagsinuse 509.990128 # Cycle average of tags in use -system.cpu0.icache.total_refs 7239988 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 978784 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.396921 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23947377000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.990128 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996074 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996074 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7239988 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7239988 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7239988 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7239988 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7239988 # number of overall hits -system.cpu0.icache.overall_hits::total 7239988 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1034461 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1034461 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1034461 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1034461 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1034461 # number of overall misses -system.cpu0.icache.overall_misses::total 1034461 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16768248492 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 16768248492 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 16768248492 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 16768248492 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 16768248492 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 16768248492 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8274449 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8274449 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8274449 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8274449 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8274449 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8274449 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125019 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125019 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125019 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125019 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125019 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125019 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16209.647819 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16209.647819 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16209.647819 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16209.647819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16209.647819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16209.647819 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1517995 # number of cycles access was blocked +system.cpu0.icache.replacements 984085 # number of replacements +system.cpu0.icache.tagsinuse 509.993322 # Cycle average of tags in use +system.cpu0.icache.total_refs 7264923 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984594 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.378598 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23948219000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.993322 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996081 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996081 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 7264923 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7264923 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7264923 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7264923 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7264923 # number of overall hits +system.cpu0.icache.overall_hits::total 7264923 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1039697 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1039697 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1039697 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1039697 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1039697 # number of overall misses +system.cpu0.icache.overall_misses::total 1039697 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16868456488 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 16868456488 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 16868456488 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 16868456488 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 16868456488 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 16868456488 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8304620 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8304620 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8304620 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8304620 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8304620 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8304620 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125195 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125195 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125195 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125195 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125195 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125195 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16224.396616 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16224.396616 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16224.396616 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16224.396616 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1612994 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 159 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 9547.138365 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 9432.713450 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 55484 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 55484 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 55484 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 55484 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 55484 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 55484 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 978977 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 978977 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 978977 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 978977 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 978977 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 978977 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12951368495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12951368495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12951368495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12951368495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12951368495 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12951368495 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118313 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118313 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118313 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.118313 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118313 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.118313 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13229.492108 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13229.492108 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13229.492108 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13229.492108 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13229.492108 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13229.492108 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54925 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54925 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54925 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54925 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54925 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54925 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 984772 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 984772 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 984772 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13041683494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13041683494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13041683494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13041683494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13041683494 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13041683494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118581 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.118581 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.118581 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13243.353278 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1336500 # number of replacements -system.cpu0.dcache.tagsinuse 506.465908 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11143271 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1336941 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.334901 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 23748000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.465908 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989191 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989191 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6824660 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6824660 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3928020 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3928020 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181318 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 181318 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208014 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208014 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10752680 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10752680 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10752680 # number of overall hits -system.cpu0.dcache.overall_hits::total 10752680 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1708787 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1708787 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1807599 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1807599 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22179 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22179 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 632 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 632 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3516386 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3516386 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3516386 # 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average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9794.303797 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33013.982666 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33013.982666 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33013.982666 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33013.982666 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 743236979 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 140000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 67742 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10971.583050 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 28000 # 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number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3942957 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181355 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 181355 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208341 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208341 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10765525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10765525 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10765525 # number of overall hits +system.cpu0.dcache.overall_hits::total 10765525 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1719034 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1719034 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1839372 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1839372 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22429 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22429 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 711 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 711 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3558406 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3558406 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3558406 # number of overall misses +system.cpu0.dcache.overall_misses::total 3558406 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46470872000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 46470872000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71479264510 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71479264510 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 406558000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 406558000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6746500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 6746500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117950136510 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117950136510 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117950136510 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117950136510 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8541602 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8541602 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5782329 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5782329 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203784 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203784 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209052 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 209052 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14323931 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14323931 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14323931 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14323931 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.201254 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.201254 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318102 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.318102 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110063 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110063 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003401 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003401 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248424 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248424 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248424 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248424 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27033.131398 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27033.131398 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38860.689686 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38860.689686 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18126.443444 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18126.443444 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9488.748242 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9488.748242 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33146.902436 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33146.902436 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 754476476 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 245500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 70452 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10709.085278 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 27277.777778 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 787469 # number of writebacks -system.cpu0.dcache.writebacks::total 787469 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 665447 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 665447 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1525035 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1525035 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4877 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4877 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2190482 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2190482 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2190482 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2190482 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1043340 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1043340 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 282564 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 282564 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 632 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 632 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1325904 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1325904 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1325904 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1325904 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27425552538 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27425552538 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9314976366 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9314976366 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 247730500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 247730500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4222000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4222000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36740528904 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 36740528904 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36740528904 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 36740528904 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2057449498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2057449498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3512263498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3512263498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122265 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122265 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085023 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085023 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003029 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003029 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092922 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092922 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092922 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092922 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26286.304118 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26286.304118 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32965.899287 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32965.899287 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14318.026818 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14318.026818 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6680.379747 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6680.379747 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27709.795659 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27709.795659 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27709.795659 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27709.795659 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 796119 # number of writebacks +system.cpu0.dcache.writebacks::total 796119 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 675047 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 675047 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1552745 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1552745 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5057 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5057 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2227792 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2227792 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2227792 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2227792 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1043987 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1043987 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 286627 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 286627 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17372 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17372 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 711 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 711 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330614 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1330614 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330614 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1330614 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27461612037 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27461612037 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9493856805 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9493856805 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 250184001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 250184001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4525001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4525001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36955468842 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 36955468842 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36955468842 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 36955468842 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1456541500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1456541500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2062903998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2062903998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3519445498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3519445498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049569 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049569 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085247 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085247 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003401 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003401 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092894 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092894 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26304.553636 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26304.553636 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33122.688389 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33122.688389 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14401.565796 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14401.565796 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6364.277075 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6364.277075 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1035,22 +1035,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1316259 # DTB read hits -system.cpu1.dtb.read_misses 12259 # DTB read misses -system.cpu1.dtb.read_acv 114 # DTB read access violations -system.cpu1.dtb.read_accesses 313045 # DTB read accesses -system.cpu1.dtb.write_hits 810694 # DTB write hits -system.cpu1.dtb.write_misses 3210 # DTB write misses -system.cpu1.dtb.write_acv 140 # DTB write access violations -system.cpu1.dtb.write_accesses 130863 # DTB write accesses -system.cpu1.dtb.data_hits 2126953 # DTB hits -system.cpu1.dtb.data_misses 15469 # DTB misses -system.cpu1.dtb.data_acv 254 # DTB access violations -system.cpu1.dtb.data_accesses 443908 # DTB accesses -system.cpu1.itb.fetch_hits 378821 # ITB hits -system.cpu1.itb.fetch_misses 8734 # ITB misses -system.cpu1.itb.fetch_acv 397 # ITB acv -system.cpu1.itb.fetch_accesses 387555 # ITB accesses +system.cpu1.dtb.read_hits 1298594 # DTB read hits +system.cpu1.dtb.read_misses 11503 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 332098 # DTB read accesses +system.cpu1.dtb.write_hits 765153 # DTB write hits +system.cpu1.dtb.write_misses 2957 # DTB write misses +system.cpu1.dtb.write_acv 47 # DTB write access violations +system.cpu1.dtb.write_accesses 125840 # DTB write accesses +system.cpu1.dtb.data_hits 2063747 # DTB hits +system.cpu1.dtb.data_misses 14460 # DTB misses +system.cpu1.dtb.data_acv 53 # DTB access violations +system.cpu1.dtb.data_accesses 457938 # DTB accesses +system.cpu1.itb.fetch_hits 372513 # ITB hits +system.cpu1.itb.fetch_misses 8563 # ITB misses +system.cpu1.itb.fetch_acv 155 # ITB acv +system.cpu1.itb.fetch_accesses 381076 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1063,516 +1063,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 10995031 # number of cpu cycles simulated +system.cpu1.numCycles 10640951 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1761936 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1452774 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 65512 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 889011 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 565473 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1701905 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1402674 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 62577 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 862370 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 552113 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 118681 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 6179 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3538328 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8413663 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1761936 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 684154 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1515563 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 337074 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 4688566 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24381 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 85396 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48035 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1081640 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 43091 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 10121394 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.831275 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.201855 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 115027 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5500 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3435420 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8139615 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1701905 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 667140 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1472350 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 326710 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 4537469 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24627 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 73138 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 47601 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1039363 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 39149 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9806707 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.830005 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.196976 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 8605831 85.03% 85.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 83210 0.82% 85.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 170185 1.68% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 136768 1.35% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 220692 2.18% 91.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 89992 0.89% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 103416 1.02% 92.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 63845 0.63% 93.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 647455 6.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 8334357 84.99% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 78230 0.80% 85.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 173812 1.77% 87.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 130927 1.34% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 215769 2.20% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 90418 0.92% 92.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 98526 1.00% 93.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 62686 0.64% 93.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 621982 6.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 10121394 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.160248 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.765224 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3636179 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4783124 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1407347 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 79113 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 215630 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 78857 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5594 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8201368 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 16988 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 215630 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3774532 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 581193 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3715501 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1338240 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 496296 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7575516 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 44770 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 149873 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5044245 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9199948 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9159980 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 39968 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4092104 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 952133 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 317142 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 23346 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1397635 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1414528 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 877825 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 136527 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 116556 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6675821 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 314231 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6372058 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 25577 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1212482 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 668533 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 238569 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 10121394 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.629563 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.309947 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9806707 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.159939 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.764933 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3510066 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4639401 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1367694 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 78184 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 211361 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 75357 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4832 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 7943726 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 14591 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 211361 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3646380 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 524692 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3638231 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1300485 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 485556 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7343826 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 139 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 57550 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 136110 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 4921664 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 8958013 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 8905584 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52429 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3978815 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 942849 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 306458 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22346 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1365387 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1395502 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 827989 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 138090 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 96967 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6484639 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 311488 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6173957 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 24546 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1207593 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 679802 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236614 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9806707 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.629565 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.304884 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 7322432 72.35% 72.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1274873 12.60% 84.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 565463 5.59% 90.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 381432 3.77% 94.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 276297 2.73% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 150290 1.48% 98.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 93014 0.92% 99.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 53503 0.53% 99.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4090 0.04% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 7075152 72.15% 72.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1257607 12.82% 84.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 548751 5.60% 90.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 366543 3.74% 94.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 274418 2.80% 97.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 146525 1.49% 98.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 78833 0.80% 99.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 55100 0.56% 99.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 3778 0.04% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 10121394 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9806707 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2751 1.84% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 83898 56.09% 57.93% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 62938 42.07% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2937 2.09% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 77829 55.26% 57.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 60078 42.66% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2823 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3945332 61.92% 61.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 9935 0.16% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 7188 0.11% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1411 0.02% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1374762 21.57% 83.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 831632 13.05% 96.88% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 198975 3.12% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3992 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3816770 61.82% 61.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10118 0.16% 62.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.05% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10095 0.16% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1996 0.03% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1354962 21.95% 84.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 784960 12.71% 96.91% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 191064 3.09% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6372058 # Type of FU issued -system.cpu1.iq.rate 0.579540 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 149587 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023475 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 22982123 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8175044 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6195827 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 58550 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 29266 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 28229 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6488697 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 30125 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 71376 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6173957 # Type of FU issued +system.cpu1.iq.rate 0.580207 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 140844 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.022813 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 22242262 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 7966601 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 5994284 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 77749 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 38725 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 37333 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6270612 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 40197 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 68178 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 250758 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 518 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1865 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 114138 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 253497 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 450 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1694 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 109535 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 364 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 10621 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 346 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8387 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 215630 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 327250 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 19053 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7270048 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 103390 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1414528 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 877825 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 292634 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6157 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4769 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1865 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 31136 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 75519 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 106655 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6299419 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1333225 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 72638 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 211361 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 294243 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 17071 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7057887 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 102198 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1395502 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 827989 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 289869 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6102 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1694 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 30581 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 71547 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 102128 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6103512 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1313696 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 70445 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 279996 # number of nop insts executed -system.cpu1.iew.exec_refs 2150860 # number of memory reference insts executed -system.cpu1.iew.exec_branches 922163 # Number of branches executed -system.cpu1.iew.exec_stores 817635 # Number of stores executed -system.cpu1.iew.exec_rate 0.572933 # Inst execution rate -system.cpu1.iew.wb_sent 6254968 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6224056 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2925555 # num instructions producing a value -system.cpu1.iew.wb_consumers 4065237 # num instructions consuming a value +system.cpu1.iew.exec_nop 261760 # number of nop insts executed +system.cpu1.iew.exec_refs 2085126 # number of memory reference insts executed +system.cpu1.iew.exec_branches 894247 # Number of branches executed +system.cpu1.iew.exec_stores 771430 # Number of stores executed +system.cpu1.iew.exec_rate 0.573587 # Inst execution rate +system.cpu1.iew.wb_sent 6061366 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6031617 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2917806 # num instructions producing a value +system.cpu1.iew.wb_consumers 4086073 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.566079 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.719652 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.566831 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.714086 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1244518 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 75662 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 99560 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9905764 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.601159 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.526173 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1232464 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 74874 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 96289 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9595346 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.599743 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.518608 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 7610675 76.83% 76.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1117297 11.28% 88.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 392466 3.96% 92.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 237967 2.40% 94.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 150669 1.52% 96.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 70627 0.71% 96.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 80896 0.82% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 63718 0.64% 98.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 181449 1.83% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 7360615 76.71% 76.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1091727 11.38% 88.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 382276 3.98% 92.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 236221 2.46% 94.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 149500 1.56% 96.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 68368 0.71% 96.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 77096 0.80% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 48958 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 180585 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9905764 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5954935 # Number of instructions committed -system.cpu1.commit.committedOps 5954935 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 9595346 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 5754744 # Number of instructions committed +system.cpu1.commit.committedOps 5754744 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1927457 # Number of memory references committed -system.cpu1.commit.loads 1163770 # Number of loads committed -system.cpu1.commit.membars 20047 # Number of memory barriers committed -system.cpu1.commit.branches 840841 # Number of branches committed -system.cpu1.commit.fp_insts 27263 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5573216 # Number of committed integer instructions. -system.cpu1.commit.function_calls 89926 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 181449 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1860459 # Number of memory references committed +system.cpu1.commit.loads 1142005 # Number of loads committed +system.cpu1.commit.membars 20259 # Number of memory barriers committed +system.cpu1.commit.branches 814036 # Number of branches committed +system.cpu1.commit.fp_insts 36051 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5384897 # Number of committed integer instructions. +system.cpu1.commit.function_calls 87726 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 180585 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 16822912 # The number of ROB reads -system.cpu1.rob.rob_writes 14613272 # The number of ROB writes -system.cpu1.timesIdled 86532 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 873637 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3796008743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5721018 # Number of Instructions Simulated -system.cpu1.committedOps 5721018 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5721018 # Number of Instructions Simulated -system.cpu1.cpi 1.921866 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.921866 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.520328 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.520328 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8196384 # number of integer regfile reads -system.cpu1.int_regfile_writes 4468767 # number of integer regfile writes -system.cpu1.fp_regfile_reads 18086 # number of floating regfile reads -system.cpu1.fp_regfile_writes 17123 # number of floating regfile writes -system.cpu1.misc_regfile_reads 275818 # number of misc regfile reads -system.cpu1.misc_regfile_writes 138963 # number of misc regfile writes -system.cpu1.icache.replacements 112877 # number of replacements -system.cpu1.icache.tagsinuse 455.325853 # Cycle average of tags in use -system.cpu1.icache.total_refs 961616 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 113389 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.480682 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1880828738000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 455.325853 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.889308 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.889308 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 961616 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 961616 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 961616 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 961616 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 961616 # number of overall hits -system.cpu1.icache.overall_hits::total 961616 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 120024 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 120024 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 120024 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 120024 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 120024 # number of overall misses -system.cpu1.icache.overall_misses::total 120024 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1993076499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1993076499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1993076499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1993076499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1993076499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1993076499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1081640 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1081640 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1081640 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1081640 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1081640 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1081640 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110965 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.110965 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110965 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.110965 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110965 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.110965 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16605.649695 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 16605.649695 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16605.649695 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 16605.649695 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16605.649695 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 16605.649695 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 288999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 16310969 # The number of ROB reads +system.cpu1.rob.rob_writes 14184459 # The number of ROB writes +system.cpu1.timesIdled 82580 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 834244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3796004491 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5534760 # Number of Instructions Simulated +system.cpu1.committedOps 5534760 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 5534760 # Number of Instructions Simulated +system.cpu1.cpi 1.922568 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.922568 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.520138 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.520138 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 7951221 # number of integer regfile reads +system.cpu1.int_regfile_writes 4345022 # number of integer regfile writes +system.cpu1.fp_regfile_reads 24272 # number of floating regfile reads +system.cpu1.fp_regfile_writes 22982 # number of floating regfile writes +system.cpu1.misc_regfile_reads 283160 # number of misc regfile reads +system.cpu1.misc_regfile_writes 134137 # number of misc regfile writes +system.cpu1.icache.replacements 108736 # number of replacements +system.cpu1.icache.tagsinuse 452.848051 # Cycle average of tags in use +system.cpu1.icache.total_refs 924017 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 109246 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.458131 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1880838222000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 452.848051 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.884469 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.884469 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 924017 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 924017 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 924017 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 924017 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 924017 # number of overall hits +system.cpu1.icache.overall_hits::total 924017 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 115346 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 115346 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 115346 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 115346 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 115346 # number of overall misses +system.cpu1.icache.overall_misses::total 115346 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1915256999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1915256999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1915256999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1915256999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1915256999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1915256999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1039363 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1039363 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1039363 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1039363 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1039363 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1039363 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110978 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.110978 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110978 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.110978 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110978 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.110978 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16604.450948 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 16604.450948 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 16604.450948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 16604.450948 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 222999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 50 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 5779.980000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7433.300000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6586 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6586 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6586 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6586 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6586 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6586 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 113438 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 113438 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 113438 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 113438 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 113438 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 113438 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550619499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1550619499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1550619499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1550619499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1550619499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1550619499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.104876 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.104876 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.104876 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.104876 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.104876 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.104876 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13669.312744 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13669.312744 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13669.312744 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13669.312744 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13669.312744 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13669.312744 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6038 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6038 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6038 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6038 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6038 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6038 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 109308 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 109308 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 109308 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 109308 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 109308 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 109308 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1491398999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1491398999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1491398999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1491398999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1491398999 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1491398999 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105168 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.105168 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.105168 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13644.005919 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 66353 # number of replacements -system.cpu1.dcache.tagsinuse 422.855509 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1693567 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 66865 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 25.328154 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1880297916000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 422.855509 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.825890 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.825890 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1103263 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1103263 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 554602 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 554602 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16904 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16904 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15090 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15090 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1657865 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1657865 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1657865 # number of overall hits -system.cpu1.dcache.overall_hits::total 1657865 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 120863 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 120863 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 188065 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 188065 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1871 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1871 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 714 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 308928 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 308928 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 308928 # number of overall misses -system.cpu1.dcache.overall_misses::total 308928 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2422870500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2422870500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7680920661 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7680920661 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 31721000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 31721000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8263500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 8263500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10103791161 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10103791161 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10103791161 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10103791161 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1224126 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1224126 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 742667 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 742667 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18775 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18775 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15804 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15804 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1966793 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1966793 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1966793 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1966793 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.098734 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.098734 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.253229 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.253229 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099654 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099654 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045178 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045178 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.157072 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.157072 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.157072 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.157072 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20046.420327 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20046.420327 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40841.840114 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 40841.840114 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16954.035275 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16954.035275 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11573.529412 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11573.529412 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32705.974081 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32705.974081 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32705.974081 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32705.974081 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 54269989 # number of cycles access was blocked +system.cpu1.dcache.replacements 61811 # number of replacements +system.cpu1.dcache.tagsinuse 423.387508 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1665798 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62157 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 26.799846 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1880297158000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 423.387508 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.826929 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.826929 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1100458 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1100458 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 541491 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 541491 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16674 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16674 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14757 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 14757 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1641949 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1641949 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1641949 # number of overall hits +system.cpu1.dcache.overall_hits::total 1641949 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 110209 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 110209 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 156496 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 156496 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1520 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1520 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 666 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 666 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 266705 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 266705 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 266705 # number of overall misses +system.cpu1.dcache.overall_misses::total 266705 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2207117500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2207117500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6428377585 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6428377585 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 25057000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 25057000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8004500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 8004500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8635495085 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8635495085 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8635495085 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8635495085 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1210667 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1210667 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 697987 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 697987 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18194 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 18194 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15423 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15423 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1908654 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1908654 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1908654 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1908654 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.091032 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.091032 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224210 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.224210 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083544 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083544 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043182 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.043182 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.139735 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.139735 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.139735 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.139735 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20026.653903 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20026.653903 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41076.945002 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41076.945002 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16484.868421 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16484.868421 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12018.768769 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12018.768769 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 32378.452166 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 32378.452166 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 48117991 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6147 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4997 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8828.695136 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9629.375825 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 44452 # number of writebacks -system.cpu1.dcache.writebacks::total 44452 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 76735 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 76735 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 160629 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 160629 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 625 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 625 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 237364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 237364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 237364 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 237364 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 44128 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 44128 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 27436 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 27436 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1246 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1246 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 712 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 712 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 71564 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 71564 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 71564 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 71564 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 680335003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 680335003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 908440847 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 908440847 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 14899501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 14899501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6048501 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6048501 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1588775850 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1588775850 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1588775850 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1588775850 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26654500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26654500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 549434000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 549434000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 576088500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 576088500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036049 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036049 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066365 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066365 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.045052 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.045052 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.036386 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.036386 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036386 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036386 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15417.308806 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15417.308806 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33111.271577 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33111.271577 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11957.865971 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.865971 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8495.085674 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8495.085674 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22200.769242 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22200.769242 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22200.769242 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22200.769242 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 36517 # number of writebacks +system.cpu1.dcache.writebacks::total 36517 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66699 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 66699 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 133155 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 133155 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 347 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 347 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 199854 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 199854 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 199854 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 199854 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43510 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 43510 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23341 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 23341 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1173 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1173 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 665 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 665 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 66851 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 66851 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 66851 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 66851 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 664874003 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 664874003 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 774412476 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 774412476 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13964500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13964500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5940500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5940500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1439286479 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1439286479 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1439286479 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1439286479 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25429000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25429000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 545455000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 545455000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 570884000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 570884000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035939 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035939 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033440 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033440 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064472 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064472 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043117 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043117 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.035025 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035025 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15280.946978 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15280.946978 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33178.204704 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33178.204704 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11904.944587 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.944587 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8933.082707 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8933.082707 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1581,171 +1581,162 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6363 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 198040 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71346 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 130 0.07% 40.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.10% 41.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102331 58.23% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 175740 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69979 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 130 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.36% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69973 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142015 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862552849000 97.86% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 68272000 0.00% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 582924500 0.03% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4256000 0.00% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40116611000 2.11% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903324912500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980840 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 199157 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71465 40.61% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.10% 41.78% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 9 0.01% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102444 58.21% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 175976 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70100 49.28% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.35% 50.72% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 9 0.01% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 70091 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142258 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862744375000 97.86% 97.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 69542000 0.00% 97.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 583001500 0.03% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5982500 0.00% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40144359500 2.11% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903547260500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980900 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683791 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808097 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 5 2.35% 2.35% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.45% 10.80% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.41% 12.21% # number of syscalls executed -system.cpu0.kern.syscall::6 28 13.15% 25.35% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 25.82% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.47% 26.29% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.23% 30.52% # number of syscalls executed -system.cpu0.kern.syscall::19 5 2.35% 32.86% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.88% 34.74% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.94% 35.68% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.88% 37.56% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.29% 40.85% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.94% 41.78% # number of syscalls executed -system.cpu0.kern.syscall::45 38 17.84% 59.62% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.88% 61.50% # number of syscalls executed -system.cpu0.kern.syscall::48 6 2.82% 64.32% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.23% 68.54% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 69.01% # number of syscalls executed -system.cpu0.kern.syscall::59 4 1.88% 70.89% # number of syscalls executed -system.cpu0.kern.syscall::71 32 15.02% 85.92% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.41% 87.32% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.23% 91.55% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 92.02% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.47% 92.49% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.29% 95.77% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.94% 96.71% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.94% 97.65% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.94% 98.59% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.06% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.94% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 213 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684188 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808394 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.65% 3.65% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.68% 12.33% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.37% 13.70% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.61% 28.31% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.46% 28.77% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.65% 32.42% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.57% 36.99% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.74% 39.73% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.46% 40.18% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.37% 41.55% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.74% 44.29% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.91% 45.21% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.44% 61.64% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.37% 63.01% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.57% 67.58% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.57% 72.15% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.46% 72.60% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.74% 75.34% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.50% 85.84% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.37% 87.21% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.74% 89.95% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.46% 90.41% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.37% 91.78% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.11% 95.89% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.91% 96.80% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.91% 97.72% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.46% 98.17% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.91% 99.09% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.91% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 219 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 103 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 101 0.05% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3753 2.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::tbi 37 0.02% 2.11% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.12% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169151 91.71% 93.83% # number of callpals executed -system.cpu0.kern.callpal::rdps 6371 3.45% 97.28% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.28% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.28% # number of callpals executed -system.cpu0.kern.callpal::rdusp 6 0.00% 97.29% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.29% # number of callpals executed -system.cpu0.kern.callpal::rti 4525 2.45% 99.74% # number of callpals executed -system.cpu0.kern.callpal::callsys 331 0.18% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 146 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184440 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6935 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1104 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3850 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169235 91.57% 93.74% # number of callpals executed +system.cpu0.kern.callpal::rdps 6384 3.45% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::rti 4673 2.53% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 133 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 184824 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7179 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1251 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1104 -system.cpu0.kern.mode_good::user 1104 +system.cpu0.kern.mode_good::kernel 1250 +system.cpu0.kern.mode_good::user 1251 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.159193 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.174119 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.274661 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1900909928000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1870692000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.296679 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901642531000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1904721500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3754 # number of times the context was actually changed +system.cpu0.kern.swap_context 3851 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2268 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39512 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10294 33.41% 33.41% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1926 6.25% 39.66% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 103 0.33% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18486 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30809 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10284 45.72% 45.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1926 8.56% 54.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 103 0.46% 54.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10181 45.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22494 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876458068500 98.58% 98.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533952000 0.03% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 54130500 0.00% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 26455983000 1.39% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903502134000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999029 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2262 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 38430 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10197 33.29% 33.29% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 6.29% 39.58% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 101 0.33% 39.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18406 60.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30630 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10185 45.68% 45.68% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 8.64% 54.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 101 0.45% 54.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10084 45.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22296 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1876291886000 98.58% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533607500 0.03% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 52904000 0.00% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 26445439500 1.39% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903323837000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998823 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.550741 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.730111 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 3 2.65% 2.65% # number of syscalls executed -system.cpu1.kern.syscall::3 12 10.62% 13.27% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.88% 14.16% # number of syscalls executed -system.cpu1.kern.syscall::6 14 12.39% 26.55% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.31% 31.86% # number of syscalls executed -system.cpu1.kern.syscall::19 5 4.42% 36.28% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.77% 38.05% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.77% 39.82% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.77% 41.59% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.54% 45.13% # number of syscalls executed -system.cpu1.kern.syscall::45 16 14.16% 59.29% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.77% 61.06% # number of syscalls executed -system.cpu1.kern.syscall::48 4 3.54% 64.60% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.88% 65.49% # number of syscalls executed -system.cpu1.kern.syscall::59 3 2.65% 68.14% # number of syscalls executed -system.cpu1.kern.syscall::71 22 19.47% 87.61% # number of syscalls executed -system.cpu1.kern.syscall::74 7 6.19% 93.81% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.77% 95.58% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.77% 97.35% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.77% 99.12% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 113 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.547865 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.727914 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.28% 10.28% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.93% 11.21% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.35% 20.56% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.93% 21.50% # number of syscalls executed +system.cpu1.kern.syscall::17 7 6.54% 28.04% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.80% 30.84% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.80% 33.64% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.67% 38.32% # number of syscalls executed +system.cpu1.kern.syscall::45 18 16.82% 55.14% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.80% 57.94% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.93% 58.88% # number of syscalls executed +system.cpu1.kern.syscall::71 31 28.97% 87.85% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.35% 97.20% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.80% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 107 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wripir 9 0.03% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 478 1.50% 1.53% # number of callpals executed -system.cpu1.kern.callpal::tbi 16 0.05% 1.58% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.60% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26108 81.82% 83.42% # number of callpals executed -system.cpu1.kern.callpal::rdps 2389 7.49% 90.91% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.91% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 90.92% # number of callpals executed -system.cpu1.kern.callpal::rdusp 3 0.01% 90.93% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.94% # number of callpals executed -system.cpu1.kern.callpal::rti 2671 8.37% 99.31% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.58% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 34 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.04% # number of callpals executed +system.cpu1.kern.callpal::swpctx 385 1.22% 1.26% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.27% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.29% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26077 82.56% 83.85% # number of callpals executed +system.cpu1.kern.callpal::rdps 2376 7.52% 91.38% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.38% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.02% 91.39% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.40% # number of callpals executed +system.cpu1.kern.callpal::rti 2525 7.99% 99.40% # number of callpals executed +system.cpu1.kern.callpal::callsys 142 0.45% 99.85% # number of callpals executed +system.cpu1.kern.callpal::imb 47 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31908 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1099 # number of protection mode switches -system.cpu1.kern.mode_switch::user 634 # number of protection mode switches +system.cpu1.kern.callpal::total 31584 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 861 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 660 -system.cpu1.kern.mode_good::user 634 +system.cpu1.kern.mode_good::kernel 514 +system.cpu1.kern.mode_good::user 488 system.cpu1.kern.mode_good::idle 26 -system.cpu1.kern.mode_switch_good::kernel 0.600546 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.596980 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.012677 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.348837 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2247097500 0.12% 0.12% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 912883500 0.05% 0.17% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1900342145000 99.83% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 479 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::total 0.302353 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2103355500 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 871184500 0.05% 0.16% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1899849485000 99.84% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 386 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index b2dcfbe50..ab9c5cd0a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,146 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.864443 # Number of seconds simulated -sim_ticks 1864443445500 # Number of ticks simulated -final_tick 1864443445500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.867374 # Number of seconds simulated +sim_ticks 1867373908500 # Number of ticks simulated +final_tick 1867373908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198323 # Simulator instruction rate (inst/s) -host_op_rate 198323 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6987525181 # Simulator tick rate (ticks/s) -host_mem_usage 299164 # Number of bytes of host memory used -host_seconds 266.82 # Real time elapsed on the host -sim_insts 52917560 # Number of instructions simulated -sim_ops 52917560 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 968960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory +host_inst_rate 123272 # Simulator instruction rate (inst/s) +host_op_rate 123272 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4349339718 # Simulator tick rate (ticks/s) +host_mem_usage 299108 # Number of bytes of host memory used +host_seconds 429.35 # Real time elapsed on the host +sim_insts 52926469 # Number of instructions simulated +sim_ops 52926469 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 969792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28501248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7519232 # Number of bytes written to this memory -system.physmem.bytes_written::total 7519232 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15140 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28501568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 969792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7518720 # Number of bytes written to this memory +system.physmem.bytes_written::total 7518720 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15153 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445332 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117488 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117488 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13344465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1422563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15286732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4032963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4032963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4032963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13344465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1422563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19319696 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 338394 # number of replacements -system.l2c.tagsinuse 65347.941058 # Cycle average of tags in use -system.l2c.total_refs 2558628 # Total number of references to valid blocks. -system.l2c.sampled_refs 403561 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.340127 # Average number of references to valid blocks. -system.l2c.warmup_cycle 4870004000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53835.098828 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5353.738970 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6159.103260 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.821458 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.081692 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.093980 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997130 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 1006554 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 827784 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1834338 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 840935 # number of Writeback hits -system.l2c.Writeback_hits::total 840935 # number of Writeback hits +system.physmem.num_reads::total 445337 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117480 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117480 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 519335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13323249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1420330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15262914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 519335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 519335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4026360 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4026360 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4026360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 519335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13323249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1420330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19289275 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 338398 # number of replacements +system.l2c.tagsinuse 65348.140689 # Cycle average of tags in use +system.l2c.total_refs 2559915 # Total number of references to valid blocks. +system.l2c.sampled_refs 403567 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.343222 # Average number of references to valid blocks. +system.l2c.warmup_cycle 4870006000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53844.889123 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5363.726417 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6139.525149 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.821608 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.081844 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.093682 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997133 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1007783 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 827771 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1835554 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 841020 # number of Writeback hits +system.l2c.Writeback_hits::total 841020 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185458 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185458 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 1006554 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1013242 # number of demand (read+write) hits -system.l2c.demand_hits::total 2019796 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 1006554 # number of overall hits -system.l2c.overall_hits::cpu.data 1013242 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1333882500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1884635500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 3218518000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3218518000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.136032 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.635294 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.635294 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383479 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383479 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.277541 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.166814 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.277541 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.166814 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41050.690047 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.939962 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40156.378331 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42200 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42200 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383447 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383447 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166729 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166729 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40155.211960 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41574.074074 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41606.778113 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41606.778113 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41050.690047 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40551.426073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40570.119350 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41050.690047 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40551.426073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40570.119350 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41867.797539 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -231,14 +231,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.286638 # Cycle average of tags in use +system.iocache.tagsinuse 1.309507 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1711308746000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.286638 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.080415 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.080415 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1711308479000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.309507 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.081844 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.081844 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -249,12 +249,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7639193806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7639193806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7659866804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7659866804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7659866804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7659866804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11464497806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11464497806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11485170804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11485170804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11485170804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11485170804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -273,17 +273,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183846.597179 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183846.597179 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183579.791588 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183579.791588 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183579.791588 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183579.791588 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7379000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275907.244080 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275907.244080 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 275258.737064 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 275258.737064 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199587000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7110 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24660 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1037.834037 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8093.552311 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -299,12 +299,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5478339000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5478339000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5490015000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5490015000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5490015000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5490015000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9303643992 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9303643992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9315319992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9315319992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9315319992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9315319992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -315,12 +315,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131842.967848 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131842.967848 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131576.153385 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131576.153385 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131576.153385 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131576.153385 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223903.638621 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223903.638621 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -338,22 +338,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9936242 # DTB read hits -system.cpu.dtb.read_misses 43490 # DTB read misses -system.cpu.dtb.read_acv 516 # DTB read access violations -system.cpu.dtb.read_accesses 957786 # DTB read accesses -system.cpu.dtb.write_hits 6625146 # DTB write hits -system.cpu.dtb.write_misses 10048 # DTB write misses -system.cpu.dtb.write_acv 376 # DTB write access violations -system.cpu.dtb.write_accesses 340602 # DTB write accesses -system.cpu.dtb.data_hits 16561388 # DTB hits -system.cpu.dtb.data_misses 53538 # DTB misses -system.cpu.dtb.data_acv 892 # DTB access violations -system.cpu.dtb.data_accesses 1298388 # DTB accesses -system.cpu.itb.fetch_hits 1339050 # ITB hits -system.cpu.itb.fetch_misses 40176 # ITB misses -system.cpu.itb.fetch_acv 1137 # ITB acv -system.cpu.itb.fetch_accesses 1379226 # ITB accesses +system.cpu.dtb.read_hits 9950205 # DTB read hits +system.cpu.dtb.read_misses 43861 # DTB read misses +system.cpu.dtb.read_acv 493 # DTB read access violations +system.cpu.dtb.read_accesses 957335 # DTB read accesses +system.cpu.dtb.write_hits 6626699 # DTB write hits +system.cpu.dtb.write_misses 9966 # DTB write misses +system.cpu.dtb.write_acv 395 # DTB write access violations +system.cpu.dtb.write_accesses 340478 # DTB write accesses +system.cpu.dtb.data_hits 16576904 # DTB hits +system.cpu.dtb.data_misses 53827 # DTB misses +system.cpu.dtb.data_acv 888 # DTB access violations +system.cpu.dtb.data_accesses 1297813 # DTB accesses +system.cpu.itb.fetch_hits 1339762 # ITB hits +system.cpu.itb.fetch_misses 37185 # ITB misses +system.cpu.itb.fetch_acv 1122 # ITB acv +system.cpu.itb.fetch_accesses 1376947 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -366,277 +366,277 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 124718167 # number of cpu cycles simulated +system.cpu.numCycles 124800831 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14016362 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11699457 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 447467 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10098689 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5905629 # Number of BTB hits +system.cpu.BPredUnit.lookups 14048431 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11726244 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 450741 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10120037 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5916610 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 935083 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44772 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31431497 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71249565 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14016362 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6840712 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13427140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2133623 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43145521 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33490 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 277896 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 300852 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 229 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8810652 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 301668 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 90022350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.791465 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.121682 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 938783 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45408 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31451408 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71430724 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14048431 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6855393 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13459712 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2155244 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43163669 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 276321 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 306226 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 194 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8835796 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303984 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 90109445 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.792711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.123252 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76595210 85.08% 85.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 880275 0.98% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1754034 1.95% 88.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 853758 0.95% 88.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2767447 3.07% 92.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 598798 0.67% 92.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 668363 0.74% 93.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009728 1.12% 94.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4894737 5.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76649733 85.06% 85.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 882120 0.98% 86.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1758761 1.95% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 855148 0.95% 88.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2774809 3.08% 92.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 597111 0.66% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671452 0.75% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1010353 1.12% 94.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4909958 5.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 90022350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.112384 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.571285 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32462663 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 42944944 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12200929 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1050932 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1362881 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 612569 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43257 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69997551 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 131864 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1362881 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33604793 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17288612 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21444377 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11497846 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4823839 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66302391 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7264 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 752324 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1793006 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44298032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80385832 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79896368 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 489464 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38124388 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6173636 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1698063 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251025 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12720780 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10525150 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6958577 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1307223 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 920725 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58755274 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2090184 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57106230 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 126003 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7528195 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3871424 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1424917 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 90022350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.634356 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.284426 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 90109445 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.112567 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.572358 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32486072 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 42966960 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12232972 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1046401 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1377039 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 612715 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43176 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70146735 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 131924 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1377039 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33631618 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17301504 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21458473 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11517889 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4822920 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66414787 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7289 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 750703 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1791896 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44375645 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80516952 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80027527 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 489425 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38131021 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6244616 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1698641 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251106 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12735763 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10548926 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6961519 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1298320 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 905557 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58829539 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2094293 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57137234 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 128634 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7593303 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3942261 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1428853 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 90109445 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.634087 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.284474 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64211383 71.33% 71.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11984837 13.31% 84.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5359973 5.95% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3439210 3.82% 94.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2607784 2.90% 97.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1324300 1.47% 98.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 687470 0.76% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 352783 0.39% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 54610 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64286768 71.34% 71.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11995743 13.31% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5355125 5.94% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3438365 3.82% 94.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2611846 2.90% 97.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1326020 1.47% 98.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 685055 0.76% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 355852 0.39% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 54671 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 90022350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 90109445 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 75162 9.94% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 361865 47.84% 57.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 319378 42.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 75508 9.96% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 363265 47.93% 57.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 319103 42.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38979239 68.26% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61855 0.11% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10375615 18.17% 86.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6703515 11.74% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949472 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38991069 68.24% 68.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61859 0.11% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25608 0.04% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10392240 18.19% 86.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6705676 11.74% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949855 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57106230 # Type of FU issued -system.cpu.iq.rate 0.457882 # Inst issue rate -system.cpu.iq.fu_busy_cnt 756405 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013246 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 204420366 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68047675 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55829438 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 696851 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 339603 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327742 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57490896 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 364448 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598206 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57137234 # Type of FU issued +system.cpu.iq.rate 0.457827 # Inst issue rate +system.cpu.iq.fu_busy_cnt 757876 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013264 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 204573341 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68190814 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55847999 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 697081 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 339930 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327759 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57523312 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 364507 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 597966 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1442254 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2799 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13958 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 583775 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1464590 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2710 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13959 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 585881 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17984 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 104066 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18028 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 111488 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1362881 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12351222 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 868923 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64407898 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684720 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10525150 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6958577 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1840963 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 621108 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12330 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13958 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 238471 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 421447 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 659918 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56579740 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10008035 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 526489 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1377039 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12355921 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 868580 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64490760 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 689025 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10548926 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6961519 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1842879 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 620807 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12564 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13959 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 241262 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 422502 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 663764 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56606739 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10022317 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 530494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3562440 # number of nop insts executed -system.cpu.iew.exec_refs 16658473 # number of memory reference insts executed -system.cpu.iew.exec_branches 8978804 # Number of branches executed -system.cpu.iew.exec_stores 6650438 # Number of stores executed -system.cpu.iew.exec_rate 0.453661 # Inst execution rate -system.cpu.iew.wb_sent 56268334 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56157180 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27683314 # num instructions producing a value -system.cpu.iew.wb_consumers 37519561 # num instructions consuming a value +system.cpu.iew.exec_nop 3566928 # number of nop insts executed +system.cpu.iew.exec_refs 16674247 # number of memory reference insts executed +system.cpu.iew.exec_branches 8979744 # Number of branches executed +system.cpu.iew.exec_stores 6651930 # Number of stores executed +system.cpu.iew.exec_rate 0.453577 # Inst execution rate +system.cpu.iew.wb_sent 56287349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56175758 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27690548 # num instructions producing a value +system.cpu.iew.wb_consumers 37534692 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.450273 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737837 # average fanout of values written-back +system.cpu.iew.wb_rate 0.450123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737732 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8193317 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 665267 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 615735 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 88659469 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.632811 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.547834 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8267625 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 665440 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 619184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 88732406 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.632394 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.547937 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67465140 76.09% 76.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8924230 10.07% 86.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4814714 5.43% 91.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2600553 2.93% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1445109 1.63% 96.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 596766 0.67% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 516883 0.58% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 484830 0.55% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1811244 2.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67542246 76.12% 76.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8923750 10.06% 86.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4811841 5.42% 91.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2594320 2.92% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1447946 1.63% 96.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 597901 0.67% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 519027 0.58% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 475014 0.54% 97.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1820361 2.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 88659469 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56104643 # Number of instructions committed -system.cpu.commit.committedOps 56104643 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 88732406 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56113829 # Number of instructions committed +system.cpu.commit.committedOps 56113829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15457698 # Number of memory references committed -system.cpu.commit.loads 9082896 # Number of loads committed -system.cpu.commit.membars 226441 # Number of memory barriers committed -system.cpu.commit.branches 8439531 # Number of branches committed +system.cpu.commit.refs 15459974 # Number of memory references committed +system.cpu.commit.loads 9084336 # Number of loads committed +system.cpu.commit.membars 226495 # Number of memory barriers committed +system.cpu.commit.branches 8440914 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51953528 # Number of committed integer instructions. -system.cpu.commit.function_calls 739583 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1811244 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 51962143 # Number of committed integer instructions. +system.cpu.commit.function_calls 739769 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1820361 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150896568 # The number of ROB reads -system.cpu.rob.rob_writes 129959625 # The number of ROB writes -system.cpu.timesIdled 1384663 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34695817 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3604162300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52917560 # Number of Instructions Simulated -system.cpu.committedOps 52917560 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52917560 # Number of Instructions Simulated -system.cpu.cpi 2.356839 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.356839 # CPI: Total CPI of All Threads -system.cpu.ipc 0.424297 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.424297 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74164887 # number of integer regfile reads -system.cpu.int_regfile_writes 40500361 # number of integer regfile writes -system.cpu.fp_regfile_reads 166351 # number of floating regfile reads -system.cpu.fp_regfile_writes 166958 # number of floating regfile writes -system.cpu.misc_regfile_reads 1995249 # number of misc regfile reads -system.cpu.misc_regfile_writes 947406 # number of misc regfile writes +system.cpu.rob.rob_reads 151043798 # The number of ROB reads +system.cpu.rob.rob_writes 130140767 # The number of ROB writes +system.cpu.timesIdled 1385278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34691386 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3609940555 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52926469 # Number of Instructions Simulated +system.cpu.committedOps 52926469 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52926469 # Number of Instructions Simulated +system.cpu.cpi 2.358004 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.358004 # CPI: Total CPI of All Threads +system.cpu.ipc 0.424087 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.424087 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74197467 # number of integer regfile reads +system.cpu.int_regfile_writes 40518410 # number of integer regfile writes +system.cpu.fp_regfile_reads 166390 # number of floating regfile reads +system.cpu.fp_regfile_writes 166940 # number of floating regfile writes +system.cpu.misc_regfile_reads 1995246 # number of misc regfile reads +system.cpu.misc_regfile_writes 947641 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -668,245 +668,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1021086 # number of replacements -system.cpu.icache.tagsinuse 509.954176 # Cycle average of tags in use -system.cpu.icache.total_refs 7728678 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1021597 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.565290 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23896761000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.954176 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996004 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996004 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7728679 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7728679 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7728679 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7728679 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7728679 # number of overall hits -system.cpu.icache.overall_hits::total 7728679 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1081971 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1081971 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1081971 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1081971 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1081971 # number of overall misses -system.cpu.icache.overall_misses::total 1081971 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17450602485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17450602485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17450602485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17450602485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17450602485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17450602485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8810650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8810650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8810650 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8810650 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8810650 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8810650 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122803 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122803 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122803 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122803 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122803 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122803 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16128.530695 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16128.530695 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16128.530695 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16128.530695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16128.530695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16128.530695 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1774492 # number of cycles access was blocked +system.cpu.icache.replacements 1022327 # number of replacements +system.cpu.icache.tagsinuse 509.956829 # Cycle average of tags in use +system.cpu.icache.total_refs 7752117 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1022838 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.579027 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23896694000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.956829 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996009 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996009 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7752118 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7752118 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7752118 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7752118 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7752118 # number of overall hits +system.cpu.icache.overall_hits::total 7752118 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1083676 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1083676 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1083676 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1083676 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16124.307901 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16124.307901 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1701496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 205 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8656.058537 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9098.909091 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1021838 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1021838 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13459032492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13459032492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13459032492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13459032492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13459032492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13459032492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115978 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115978 # 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number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1826719 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1826719 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1967450 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1967450 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23276 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23276 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7252868 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7252868 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4173229 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4173229 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190095 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 219635 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 213497 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 219640 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219640 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15223668 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15223668 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15223668 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15223668 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.201437 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.201437 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320461 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.320461 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109613 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109613 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000023 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000023 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.249368 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.249368 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.249368 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.249368 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26730.086291 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26730.086291 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38131.155537 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38131.155537 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18388.447328 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18388.447328 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30800 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30800 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.061664 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32642.061664 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.061664 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32642.061664 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 733938028 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72096 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10180.010375 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.249452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.249452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.249452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.249452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26710.048023 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26710.048023 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38282.475826 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38282.475826 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18401.311854 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18401.311854 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30700 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30700 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32707.293656 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32707.293656 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32707.293656 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32707.293656 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 749837529 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 205000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72763 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10305.203592 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25625 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840935 # number of writebacks -system.cpu.dcache.writebacks::total 840935 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 742319 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 742319 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667295 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1667295 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5261 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5261 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2409614 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2409614 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2409614 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2409614 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084400 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084400 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300155 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300155 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18015 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18015 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 841020 # number of writebacks +system.cpu.dcache.writebacks::total 841020 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 745266 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 745266 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667773 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1667773 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5284 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5284 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2413039 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2413039 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2413039 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2413039 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084268 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084268 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300264 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300264 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18118 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18118 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384555 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384555 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384555 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384555 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28231864000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28231864000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9653593940 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9653593940 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 269637000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 269637000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1384532 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384532 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28231218500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28231218500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9703849435 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9703849435 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 271481500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 271481500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 138000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 138000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37885457940 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37885457940 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37885457940 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37885457940 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423534500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423534500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2001030998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2001030998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3424565498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3424565498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119498 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119498 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084413 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084413 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37935067935 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37935067935 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37935067935 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37935067935 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1425162500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1425162500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2002731998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002731998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3427894498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427894498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119381 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119381 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048893 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048893 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084863 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084863 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090999 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090999 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090999 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090999 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26034.548137 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26034.548137 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32162.029418 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32162.029418 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14967.360533 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14967.360533 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090946 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090946 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26037.122280 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26037.122280 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32317.725185 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32317.725185 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14984.076609 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.076609 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27600 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27362.912950 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27362.912950 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27362.912950 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27362.912950 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27399.199105 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27399.199105 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27399.199105 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27399.199105 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -915,28 +915,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6425 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211112 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74681 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 133 0.07% 41.03% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1886 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105636 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182336 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73314 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1886 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73315 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148648 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1823792488500 97.82% 97.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 71545000 0.00% 97.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 571672500 0.03% 97.85% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 40006830500 2.15% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1864442536500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981695 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6432 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211195 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74695 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 137 0.08% 41.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1890 1.04% 42.06% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105693 57.94% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182415 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73328 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 137 0.09% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1890 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73331 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148686 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1826702082500 97.82% 97.82% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 72077500 0.00% 97.83% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 572984500 0.03% 97.86% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 40025844000 2.14% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1867372988500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981699 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694034 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815242 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693811 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815097 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -975,29 +975,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175205 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6791 3.54% 96.97% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175272 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6795 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5112 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rti 5118 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192064 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches -system.cpu.kern.mode_switch::user 1735 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2104 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1905 -system.cpu.kern.mode_good::user 1735 +system.cpu.kern.callpal::total 192141 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2108 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325641 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080798 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393229 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29922134000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2785239500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1831735155000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080645 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393483 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29935560000 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2782423500 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1834654997000 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 07942a1c8..e2d527772 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538055 # Number of seconds simulated -sim_ticks 2538055224500 # Number of ticks simulated -final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.538087 # Number of seconds simulated +sim_ticks 2538087368500 # Number of ticks simulated +final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74782 # Simulator instruction rate (inst/s) -host_op_rate 96192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3131579061 # Simulator tick rate (ticks/s) -host_mem_usage 390232 # Number of bytes of host memory used -host_seconds 810.47 # Real time elapsed on the host -sim_insts 60608338 # Number of instructions simulated -sim_ops 77960937 # Number of ops (including micro ops) simulated +host_inst_rate 75387 # Simulator instruction rate (inst/s) +host_op_rate 96971 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3156986836 # Simulator tick rate (ticks/s) +host_mem_usage 390016 # Number of bytes of host memory used +host_seconds 803.96 # Real time elapsed on the host +sim_insts 60608307 # Number of instructions simulated +sim_ops 77960925 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64349 # number of replacements -system.l2c.tagsinuse 51370.291201 # Cycle average of tags in use -system.l2c.total_refs 1966684 # Total number of references to valid blocks. -system.l2c.sampled_refs 129742 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.158422 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527049892000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36909.964338 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.537302 # Average occupied blocks per requestor +system.l2c.replacements 64372 # number of replacements +system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use +system.l2c.total_refs 1967256 # Total number of references to valid blocks. +system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8186.541319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6225.247998 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563201 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000741 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124917 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094990 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783848 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 978702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387818 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1500728 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits -system.l2c.Writeback_hits::total 608398 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112928 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112928 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500746 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613656 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122661 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11547 # number of overall hits -system.l2c.overall_hits::cpu.inst 978702 # number of overall hits -system.l2c.overall_hits::cpu.data 500746 # number of overall hits -system.l2c.overall_hits::total 1613656 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits +system.l2c.Writeback_hits::total 608347 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits +system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits +system.l2c.overall_hits::cpu.inst 978266 # number of overall hits +system.l2c.overall_hits::cpu.data 500583 # number of overall hits +system.l2c.overall_hits::total 1613985 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2903 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133164 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133164 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12372 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143855 # number of demand (read+write) misses -system.l2c.demand_misses::total 156289 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143884 # number of demand (read+write) misses +system.l2c.demand_misses::total 156312 # number of demand (read+write) misses system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12372 # number of overall misses -system.l2c.overall_misses::cpu.data 143855 # number of overall misses -system.l2c.overall_misses::total 156289 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3190500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu.inst 12366 # number of overall misses +system.l2c.overall_misses::cpu.data 143884 # number of overall misses +system.l2c.overall_misses::total 156312 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3194000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 658900997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 562244999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1224396496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7068682495 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7068682495 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3190500 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 658485498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 561949499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1223688997 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1101000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1101000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7073691498 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7073691498 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3194000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 658900997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7630927494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8293078991 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 3190500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu.inst 658485498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7635640997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8297380495 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3194000 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32081918388 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5320000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198827716888 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198833036888 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026679 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015132 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015120 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088264 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,9 +332,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15052335 # DTB read hits +system.cpu.checker.dtb.read_hits 15052368 # DTB read hits system.cpu.checker.dtb.read_misses 7317 # DTB read misses -system.cpu.checker.dtb.write_hits 11295995 # DTB write hits +system.cpu.checker.dtb.write_hits 11296020 # DTB write hits system.cpu.checker.dtb.write_misses 2195 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -345,13 +345,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15059652 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11298190 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15059685 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11298215 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26348330 # DTB hits +system.cpu.checker.dtb.hits 26348388 # DTB hits system.cpu.checker.dtb.misses 9512 # DTB misses -system.cpu.checker.dtb.accesses 26357842 # DTB accesses -system.cpu.checker.itb.inst_hits 61787107 # ITB inst hits +system.cpu.checker.dtb.accesses 26357900 # DTB accesses +system.cpu.checker.itb.inst_hits 61787075 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -368,36 +368,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61791578 # ITB inst accesses -system.cpu.checker.itb.hits 61787107 # DTB hits +system.cpu.checker.itb.inst_accesses 61791546 # ITB inst accesses +system.cpu.checker.itb.hits 61787075 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61791578 # DTB accesses -system.cpu.checker.numCycles 78251513 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61791546 # DTB accesses +system.cpu.checker.numCycles 78251500 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51779226 # DTB read hits -system.cpu.dtb.read_misses 81574 # DTB read misses -system.cpu.dtb.write_hits 11882622 # DTB write hits -system.cpu.dtb.write_misses 18093 # DTB write misses +system.cpu.dtb.read_hits 51778790 # DTB read hits +system.cpu.dtb.read_misses 81353 # DTB read misses +system.cpu.dtb.write_hits 11881898 # DTB write hits +system.cpu.dtb.write_misses 18166 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8066 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8033 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860800 # DTB read accesses -system.cpu.dtb.write_accesses 11900715 # DTB write accesses +system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51860143 # DTB read accesses +system.cpu.dtb.write_accesses 11900064 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63661848 # DTB hits -system.cpu.dtb.misses 99667 # DTB misses -system.cpu.dtb.accesses 63761515 # DTB accesses -system.cpu.itb.inst_hits 13144692 # ITB inst hits -system.cpu.itb.inst_misses 11967 # ITB inst misses +system.cpu.dtb.hits 63660688 # DTB hits +system.cpu.dtb.misses 99519 # DTB misses +system.cpu.dtb.accesses 63760207 # DTB accesses +system.cpu.itb.inst_hits 13142674 # ITB inst hits +system.cpu.itb.inst_misses 12012 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -406,122 +406,122 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5259 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5318 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13156659 # ITB inst accesses -system.cpu.itb.hits 13144692 # DTB hits -system.cpu.itb.misses 11967 # DTB misses -system.cpu.itb.accesses 13156659 # DTB accesses -system.cpu.numCycles 487285069 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154686 # ITB inst accesses +system.cpu.itb.hits 13142674 # DTB hits +system.cpu.itb.misses 12012 # DTB misses +system.cpu.itb.accesses 13154686 # DTB accesses +system.cpu.numCycles 487300785 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits +system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available @@ -549,13 +549,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued @@ -568,10 +568,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued @@ -583,361 +583,361 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued -system.cpu.iq.rate 0.259591 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued +system.cpu.iq.rate 0.259577 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255493 # number of nop insts executed -system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed -system.cpu.iew.exec_branches 11931891 # Number of branches executed -system.cpu.iew.exec_stores 12393835 # Number of stores executed -system.cpu.iew.exec_rate 0.253013 # Inst execution rate -system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47524907 # num instructions producing a value -system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value +system.cpu.iew.exec_nop 255111 # number of nop insts executed +system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed +system.cpu.iew.exec_branches 11930392 # Number of branches executed +system.cpu.iew.exec_stores 12393079 # Number of stores executed +system.cpu.iew.exec_rate 0.253002 # Inst execution rate +system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47523827 # num instructions producing a value +system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758719 # Number of instructions committed -system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60758688 # Number of instructions committed +system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520132 # Number of memory references committed -system.cpu.commit.loads 15719739 # Number of loads committed -system.cpu.commit.membars 413350 # Number of memory barriers committed -system.cpu.commit.branches 10163894 # Number of branches committed +system.cpu.commit.refs 27520186 # Number of memory references committed +system.cpu.commit.loads 15719769 # Number of loads committed +system.cpu.commit.membars 413359 # Number of memory barriers committed +system.cpu.commit.branches 10163898 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. -system.cpu.commit.function_calls 996264 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. +system.cpu.commit.function_calls 996262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256736769 # The number of ROB reads -system.cpu.rob.rob_writes 209812510 # The number of ROB writes -system.cpu.timesIdled 1906775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324667246 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588737338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608338 # Number of Instructions Simulated -system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated -system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558055788 # number of integer regfile reads -system.cpu.int_regfile_writes 90157821 # number of integer regfile writes -system.cpu.fp_regfile_reads 8288 # number of floating regfile reads -system.cpu.fp_regfile_writes 2908 # number of floating regfile writes -system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads -system.cpu.misc_regfile_writes 913357 # number of misc regfile writes -system.cpu.icache.replacements 991945 # number of replacements -system.cpu.icache.tagsinuse 511.576100 # Cycle average of tags in use -system.cpu.icache.total_refs 12062971 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992457 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.154654 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225347000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576100 # Average occupied blocks per requestor +system.cpu.rob.rob_reads 256700614 # The number of ROB reads +system.cpu.rob.rob_writes 209796185 # The number of ROB writes +system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60608307 # Number of Instructions Simulated +system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated +system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558050325 # number of integer regfile reads +system.cpu.int_regfile_writes 90161621 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads +system.cpu.misc_regfile_writes 913390 # number of misc regfile writes +system.cpu.icache.replacements 991554 # number of replacements +system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use +system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12062971 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12062971 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12062971 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12062971 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12062971 # number of overall hits -system.cpu.icache.overall_hits::total 12062971 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1077319 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1077319 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1077319 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1077319 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1077319 # number of overall misses -system.cpu.icache.overall_misses::total 1077319 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16672871489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16672871489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16672871489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16672871489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16672871489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16672871489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13140290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13140290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13140290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13140290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081986 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081986 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081986 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081986 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2904990 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits +system.cpu.icache.overall_hits::total 12061582 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses +system.cpu.icache.overall_misses::total 1076715 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 436 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6662.821101 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84824 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84824 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84824 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84824 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992495 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 992495 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 992495 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 992495 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 992495 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 992495 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12649346990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12649346990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644089 # number of replacements -system.cpu.dcache.tagsinuse 511.991456 # Cycle average of tags in use -system.cpu.dcache.total_refs 21738846 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644601 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724499 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991456 # Average occupied blocks per requestor +system.cpu.dcache.replacements 643955 # number of replacements +system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use +system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908205 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13908205 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258424 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258424 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283313 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283313 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285772 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285772 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21166629 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21166629 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21166629 # number of overall hits -system.cpu.dcache.overall_hits::total 21166629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 766922 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 766922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2994004 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2994004 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13808 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13808 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3759495 # number of overall misses +system.cpu.dcache.overall_misses::total 3759495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14876538000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14876538000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129441839072 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129441839072 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224157500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224157500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 359000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 359000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144318377072 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24926244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24926244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24926244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24926244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052182 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052182 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292007 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292007 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046437 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046437 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150825 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150825 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150825 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150825 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19428.423293 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19428.423293 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43236.852036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43236.852036 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16228.009846 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16228.009846 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22437.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 22437.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38387.702889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38387.702889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33577415 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7376000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7440 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608398 # number of writebacks -system.cpu.dcache.writebacks::total 608398 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 380638 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 380638 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2745107 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2745107 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1447 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3125745 # 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number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744878 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3124452 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3124452 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3124452 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3124452 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386136 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -959,16 +959,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index b2358caab..37534da99 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,71 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.617033 # Number of seconds simulated -sim_ticks 2617033170500 # Number of ticks simulated -final_tick 2617033170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.617165 # Number of seconds simulated +sim_ticks 2617165375500 # Number of ticks simulated +final_tick 2617165375500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88113 # Simulator instruction rate (inst/s) -host_op_rate 113402 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3655705591 # Simulator tick rate (ticks/s) -host_mem_usage 391256 # Number of bytes of host memory used -host_seconds 715.88 # Real time elapsed on the host -sim_insts 63077791 # Number of instructions simulated -sim_ops 81181923 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4357428 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5244336 # Number of bytes read from this memory -system.physmem.bytes_read::total 131535204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 820992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4255104 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7284240 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81969 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301800 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66486 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823770 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46277796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1665026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 162456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2003924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50261191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 162456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1625927 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1150974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2783396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1625927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46277796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1671522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 162456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3154898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53044587 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 89131 # Simulator instruction rate (inst/s) +host_op_rate 114699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3698456604 # Simulator tick rate (ticks/s) +host_mem_usage 391036 # Number of bytes of host memory used +host_seconds 707.64 # Real time elapsed on the host +sim_insts 63072219 # Number of instructions simulated +sim_ops 81165616 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -84,237 +29,310 @@ system.realview.nvmem.bw_inst_read::total 171 # I system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72594 # number of replacements -system.l2c.tagsinuse 53100.305923 # Cycle average of tags in use -system.l2c.total_refs 1970249 # Total number of references to valid blocks. -system.l2c.sampled_refs 137794 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.298511 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 388160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4317812 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 434112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5305072 # Number of bytes read from this memory +system.physmem.bytes_read::total 131557540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 388160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 434112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4272576 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7301712 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6783 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82918 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302149 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66759 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824043 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46275459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 148313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1649805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 165871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2027030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50267186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 148313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 165871 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1632520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1150915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2789931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1632520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46275459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 148313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1656300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 165871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3177945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53057118 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72943 # number of replacements +system.l2c.tagsinuse 53116.867697 # Cycle average of tags in use +system.l2c.total_refs 1971460 # Total number of references to valid blocks. +system.l2c.sampled_refs 138142 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.271257 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37791.704596 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.504480 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.004560 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4202.741800 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2939.105076 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.484693 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4025.080355 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4123.680364 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.576656 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37786.311031 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 4.267723 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000236 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4199.901742 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2938.535340 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 12.943065 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.004375 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4043.458423 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4131.445760 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.576573 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000065 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064129 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.044847 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061418 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062922 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.810246 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 54561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 401038 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165879 # 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mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.840125 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.849717 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.845295 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783515 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.813278 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.795954 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618358 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.533183 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567818 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000203 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.217465 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091859 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40411.328872 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40388.960103 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40404.341603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40734.530859 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.288451 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.098817 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.500000 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40019.795658 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.245675 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40016.164585 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41094.922774 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40730.693596 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40895.030032 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40423.935251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40727.858238 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.058335 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.889669 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40027.883460 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.546261 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.054422 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40017.066086 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41076.199160 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40760.780552 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40900.455825 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +537,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9087709 # DTB read hits -system.cpu0.dtb.read_misses 37707 # DTB read misses -system.cpu0.dtb.write_hits 5292852 # DTB write hits -system.cpu0.dtb.write_misses 6797 # DTB write misses +system.cpu0.dtb.read_hits 7439931 # DTB read hits +system.cpu0.dtb.read_misses 24509 # DTB read misses +system.cpu0.dtb.write_hits 4439969 # DTB write hits +system.cpu0.dtb.write_misses 3332 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2252 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1465 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1349 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9125416 # DTB read accesses -system.cpu0.dtb.write_accesses 5299649 # DTB write accesses +system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7464440 # DTB read accesses +system.cpu0.dtb.write_accesses 4443301 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14380561 # DTB hits -system.cpu0.dtb.misses 44504 # DTB misses -system.cpu0.dtb.accesses 14425065 # DTB accesses -system.cpu0.itb.inst_hits 4426363 # ITB inst hits -system.cpu0.itb.inst_misses 5791 # ITB inst misses +system.cpu0.dtb.hits 11879900 # DTB hits +system.cpu0.dtb.misses 27841 # DTB misses +system.cpu0.dtb.accesses 11907741 # DTB accesses +system.cpu0.itb.inst_hits 3552097 # ITB inst hits +system.cpu0.itb.inst_misses 3937 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -536,542 +566,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1661 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 929 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4432154 # ITB inst accesses -system.cpu0.itb.hits 4426363 # DTB hits -system.cpu0.itb.misses 5791 # DTB misses -system.cpu0.itb.accesses 4432154 # DTB accesses -system.cpu0.numCycles 73540541 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 3556034 # ITB inst accesses +system.cpu0.itb.hits 3552097 # DTB hits +system.cpu0.itb.misses 3937 # DTB misses +system.cpu0.itb.accesses 3556034 # DTB accesses +system.cpu0.numCycles 63548405 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6354280 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4863798 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 316535 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 4079773 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3047693 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5090505 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 3902323 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 231356 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3310708 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2517095 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 700511 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 30883 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12981968 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33339853 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6354280 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3748204 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7827899 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1608255 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 88516 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 23525864 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 77679 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 91798 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4424514 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 175463 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2818 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 45755598 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.940589 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.320885 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 576022 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 23707 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 10651881 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 26843573 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5090505 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3093117 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 6356133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1209317 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66372 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20477375 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 36616 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 72183 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 3550824 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 136175 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2156 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 38533087 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.905766 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.281431 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 37936221 82.91% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 625086 1.37% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 819758 1.79% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 695394 1.52% 87.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 800497 1.75% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 578636 1.26% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 719119 1.57% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 370554 0.81% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3210333 7.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32183362 83.52% 83.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 497864 1.29% 84.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 649099 1.68% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 569855 1.48% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 713173 1.85% 89.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 461238 1.20% 91.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 562037 1.46% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 306432 0.80% 93.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2590027 6.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 45755598 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086405 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.453353 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13479181 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 23559009 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7020718 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 606128 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1090562 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 996028 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66487 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41577642 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 218603 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1090562 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14092626 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6784553 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14469405 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6963849 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2354603 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40318960 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2633 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 472928 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1334672 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 351 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40667832 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 182121697 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 182086780 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34917 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31702592 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8965239 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 463825 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 419023 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5696158 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7936117 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5894118 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139492 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1233570 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 38069002 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 950684 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38295497 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6802670 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14391567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 261548 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 45755598 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.836958 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.462966 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 38533087 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.080104 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.422411 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 11016691 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20495843 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 5693231 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512184 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 815138 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 784502 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 52422 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 33794983 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 170156 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 815138 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 11512212 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6110309 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12456624 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 5662288 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1976516 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 32836773 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1958 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 434728 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1081609 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 147 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 32827027 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 148293172 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 148253410 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 39762 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 25938752 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6888275 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 379434 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 344458 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4684493 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6313022 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4948082 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 931233 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 932024 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 31038582 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 848484 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 31613010 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 68951 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5311616 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10469723 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 281141 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 38533087 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.820412 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.447904 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 29855724 65.25% 65.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6336412 13.85% 79.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3245721 7.09% 86.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2523061 5.51% 91.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2111675 4.62% 96.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 936021 2.05% 98.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 511535 1.12% 99.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 181147 0.40% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54302 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 25332313 65.74% 65.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5318332 13.80% 79.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2653261 6.89% 86.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2120070 5.50% 91.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1758280 4.56% 96.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 743996 1.93% 98.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 416585 1.08% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 146664 0.38% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 43586 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 45755598 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 38533087 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27761 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 835942 77.99% 80.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207752 19.38% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 17185 1.90% 1.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.05% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 711308 78.54% 80.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 176706 19.51% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 23003680 60.07% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50163 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9567598 24.98% 85.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5620993 14.68% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 39793 0.13% 0.13% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 18975009 60.02% 60.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42063 0.13% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 2 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 627 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7818427 24.73% 85.02% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4737084 14.98% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38295497 # Type of FU issued -system.cpu0.iq.rate 0.520740 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1071919 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.027991 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 123548516 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45830842 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35351164 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8368 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39310727 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4345 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 327037 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 31613010 # Type of FU issued +system.cpu0.iq.rate 0.497463 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 905651 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028648 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 102751361 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 37203152 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 29110459 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 9929 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5392 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4352 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 32473546 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5322 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 253493 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1508258 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3980 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13847 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 614652 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1084760 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3550 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10332 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 476904 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149655 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5288 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1893731 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4858 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1090562 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4675196 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 127491 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39158193 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 88903 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7936117 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5894118 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 617815 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49276 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17780 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13847 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 160769 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144529 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 305298 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37872918 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9405503 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 422579 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 815138 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4299477 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 104449 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 31945570 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 72737 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 6313022 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 4948082 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 576088 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 33936 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17434 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10332 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 115531 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 108245 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 223776 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 31278568 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7699224 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 334442 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 138507 # number of nop insts executed -system.cpu0.iew.exec_refs 14971538 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5077620 # Number of branches executed -system.cpu0.iew.exec_stores 5566035 # Number of stores executed -system.cpu0.iew.exec_rate 0.514994 # Inst execution rate -system.cpu0.iew.wb_sent 37653849 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35355057 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18700837 # num instructions producing a value -system.cpu0.iew.wb_consumers 35658328 # num instructions consuming a value +system.cpu0.iew.exec_nop 58504 # number of nop insts executed +system.cpu0.iew.exec_refs 12394115 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4158454 # Number of branches executed +system.cpu0.iew.exec_stores 4694891 # Number of stores executed +system.cpu0.iew.exec_rate 0.492201 # Inst execution rate +system.cpu0.iew.wb_sent 31120630 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 29114811 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 15418480 # num instructions producing a value +system.cpu0.iew.wb_consumers 29202336 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.480756 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524445 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.458152 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.527988 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6703968 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 689136 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 267907 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 44701440 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.716325 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.672707 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5043051 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 567343 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 195875 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 37746791 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.699150 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.656907 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32554343 72.83% 72.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6077315 13.60% 86.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1947893 4.36% 90.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1038743 2.32% 93.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 803562 1.80% 94.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 505193 1.13% 96.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 401469 0.90% 96.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 200976 0.45% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1171946 2.62% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 27673007 73.31% 73.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5099673 13.51% 86.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1632700 4.33% 91.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 816219 2.16% 93.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 659263 1.75% 95.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 376754 1.00% 96.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 343613 0.91% 96.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 170043 0.45% 97.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 975519 2.58% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 44701440 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24280608 # Number of instructions committed -system.cpu0.commit.committedOps 32020757 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 37746791 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 19900047 # Number of instructions committed +system.cpu0.commit.committedOps 26390683 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11707325 # Number of memory references committed -system.cpu0.commit.loads 6427859 # Number of loads committed -system.cpu0.commit.membars 234599 # Number of memory barriers committed -system.cpu0.commit.branches 4418672 # Number of branches committed -system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28286546 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500309 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1171946 # number cycles where commit BW limit reached +system.cpu0.commit.refs 9699440 # Number of memory references committed +system.cpu0.commit.loads 5228262 # Number of loads committed +system.cpu0.commit.membars 194354 # Number of memory barriers committed +system.cpu0.commit.branches 3620828 # Number of branches committed +system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 23422561 # Number of committed integer instructions. +system.cpu0.commit.function_calls 422942 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 975519 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 81369547 # The number of ROB reads -system.cpu0.rob.rob_writes 78542452 # The number of ROB writes -system.cpu0.timesIdled 427204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27784943 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5160481977 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24199866 # Number of Instructions Simulated -system.cpu0.committedOps 31940015 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24199866 # Number of Instructions Simulated -system.cpu0.cpi 3.038882 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.038882 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.329068 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.329068 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176731885 # number of integer regfile reads -system.cpu0.int_regfile_writes 35129220 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3381 # number of floating regfile reads -system.cpu0.fp_regfile_writes 940 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47656068 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527809 # number of misc regfile writes -system.cpu0.icache.replacements 407270 # number of replacements -system.cpu0.icache.tagsinuse 511.577657 # Cycle average of tags in use -system.cpu0.icache.total_refs 3982592 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 407782 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.766473 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7275068000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.577657 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3982592 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3982592 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3982592 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3982592 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3982592 # number of overall hits -system.cpu0.icache.overall_hits::total 3982592 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 441782 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 441782 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 441782 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 441782 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 441782 # number of overall misses -system.cpu0.icache.overall_misses::total 441782 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7132710997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7132710997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7132710997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7132710997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7132710997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7132710997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4424374 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4424374 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4424374 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4424374 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4424374 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4424374 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099852 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099852 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099852 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099852 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099852 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099852 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16145.318272 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16145.318272 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16145.318272 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16145.318272 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1383498 # number of cycles access was blocked +system.cpu0.rob.rob_reads 67501483 # The number of ROB reads +system.cpu0.rob.rob_writes 63684069 # The number of ROB writes +system.cpu0.timesIdled 366948 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25015318 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5170100782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 19875493 # Number of Instructions Simulated +system.cpu0.committedOps 26366129 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 19875493 # Number of Instructions Simulated +system.cpu0.cpi 3.197325 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.197325 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.312761 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.312761 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 145756307 # number of integer regfile reads +system.cpu0.int_regfile_writes 28747856 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4243 # number of floating regfile reads +system.cpu0.fp_regfile_writes 404 # number of floating regfile writes +system.cpu0.misc_regfile_reads 38262536 # number of misc regfile reads +system.cpu0.misc_regfile_writes 444175 # number of misc regfile writes +system.cpu0.icache.replacements 335591 # number of replacements +system.cpu0.icache.tagsinuse 511.578004 # Cycle average of tags in use +system.cpu0.icache.total_refs 3187209 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 336103 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.482834 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 7275076000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.578004 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999176 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999176 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3187209 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3187209 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3187209 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3187209 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3187209 # number of overall hits +system.cpu0.icache.overall_hits::total 3187209 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 363477 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 363477 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 363477 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 363477 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 363477 # number of overall misses +system.cpu0.icache.overall_misses::total 363477 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5925752494 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5925752494 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5925752494 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5925752494 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5925752494 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5925752494 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 3550686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 3550686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 3550686 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 3550686 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 3550686 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 3550686 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102368 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.102368 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102368 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.102368 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102368 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.102368 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16302.964133 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16302.964133 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16302.964133 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16302.964133 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1276494 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 169 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 156 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8186.378698 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8182.653846 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33988 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33988 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33988 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33988 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33988 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33988 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407794 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 407794 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 407794 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092170 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.092170 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.092170 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13416.665029 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4556806494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8394000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8394000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8394000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8394000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.094661 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.094661 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.094661 # 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number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1594295 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1594295 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9014 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9014 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7780 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1995851 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1995851 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1995851 # number of overall misses -system.cpu0.dcache.overall_misses::total 1995851 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7292954000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 7292954000 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178801 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178801 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18161.735848 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18161.735848 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44946.320697 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44946.320697 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12628.300422 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12628.300422 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11615.745501 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11615.745501 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39557.385975 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39557.385975 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7317992 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1712000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1467 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 85 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4988.406271 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20141.176471 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 225959 # 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number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 155489 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152427 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 152427 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7329543 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7329543 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7329543 # number of overall hits +system.cpu0.dcache.overall_hits::total 7329543 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 331165 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 331165 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1441313 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1441313 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8607 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8607 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7989 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7989 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1772478 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1772478 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1772478 # number of overall misses +system.cpu0.dcache.overall_misses::total 1772478 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6024148000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6024148000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68192376390 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 68192376390 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105659500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 105659500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 91795500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 91795500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 74216524390 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 74216524390 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 74216524390 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 74216524390 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5050252 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5050252 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4051769 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4051769 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 164096 # 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miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052451 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052451 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049802 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049802 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.194735 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.194735 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.194735 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.194735 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18190.774991 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18190.774991 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47312.676976 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 47312.676976 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12275.996282 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12275.996282 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11490.236575 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11490.236575 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41871.619501 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41871.619501 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 5649995 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1774500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1210 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 93 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4669.417355 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 19080.645161 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks -system.cpu0.dcache.writebacks::total 255942 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 212150 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 212150 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463164 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1463164 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 530 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 530 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1675314 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1675314 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1675314 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1675314 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189406 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189406 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131131 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131131 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8484 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8484 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320537 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320537 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320537 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320537 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2811014487 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2811014487 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4674099005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4674099005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79244002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79244002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65918035 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65918035 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7485113492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7485113492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7485113492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7485113492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13455989500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13455989500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1298746899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1298746899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14754736399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14754736399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029881 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029881 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027185 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027185 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046281 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046281 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043342 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043342 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028716 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028716 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14841.211403 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14841.211403 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35644.500576 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35644.500576 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9340.405705 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9340.405705 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8480.385308 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8480.385308 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 209818 # number of writebacks +system.cpu0.dcache.writebacks::total 209818 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 177491 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 177491 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1323875 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1323875 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 700 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1501366 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1501366 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1501366 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1501366 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 153674 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 153674 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 117438 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 117438 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7907 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7907 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7979 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7979 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 271112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 271112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 271112 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 271112 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2311816775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2311816775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4408331005 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4408331005 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70347504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70347504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 66656537 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66656537 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6720147780 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6720147780 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6720147780 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6720147780 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12100601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12100601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1292553399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1292553399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13393154899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13393154899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030429 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030429 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048185 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.048185 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029786 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029786 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15043.642874 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15043.642874 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37537.517711 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37537.517711 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8896.864045 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8896.864045 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8353.996365 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8353.996365 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1081,27 +1107,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43452334 # DTB read hits -system.cpu1.dtb.read_misses 46277 # DTB read misses -system.cpu1.dtb.write_hits 7091337 # DTB write hits -system.cpu1.dtb.write_misses 12150 # DTB write misses +system.cpu1.dtb.read_hits 45088968 # DTB read hits +system.cpu1.dtb.read_misses 60619 # DTB read misses +system.cpu1.dtb.write_hits 7938217 # DTB write hits +system.cpu1.dtb.write_misses 15813 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2524 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3762 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2729 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3748 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43498611 # DTB read accesses -system.cpu1.dtb.write_accesses 7103487 # DTB write accesses +system.cpu1.dtb.perms_faults 727 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 45149587 # DTB read accesses +system.cpu1.dtb.write_accesses 7954030 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50543671 # DTB hits -system.cpu1.dtb.misses 58427 # DTB misses -system.cpu1.dtb.accesses 50602098 # DTB accesses -system.cpu1.itb.inst_hits 9232744 # ITB inst hits -system.cpu1.itb.inst_misses 6115 # ITB inst misses +system.cpu1.dtb.hits 53027185 # DTB hits +system.cpu1.dtb.misses 76432 # DTB misses +system.cpu1.dtb.accesses 53103617 # DTB accesses +system.cpu1.itb.inst_hits 10093689 # ITB inst hits +system.cpu1.itb.inst_misses 8052 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1110,542 +1136,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1606 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1586 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1727 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2426 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9238859 # ITB inst accesses -system.cpu1.itb.hits 9232744 # DTB hits -system.cpu1.itb.misses 6115 # DTB misses -system.cpu1.itb.accesses 9238859 # DTB accesses -system.cpu1.numCycles 420389270 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10101741 # ITB inst accesses +system.cpu1.itb.hits 10093689 # DTB hits +system.cpu1.itb.misses 8052 # DTB misses +system.cpu1.itb.accesses 10101741 # DTB accesses +system.cpu1.numCycles 430376404 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9847995 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8081754 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 448433 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6818773 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5657403 # Number of BTB hits +system.cpu1.BPredUnit.lookups 11102078 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 9036479 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 529963 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7542756 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 6181694 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 833939 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50420 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22177481 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71987538 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9847995 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6491342 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15338669 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4640041 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 86616 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 81067805 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5869 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 63713 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142087 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9230611 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 860735 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3603 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 122048207 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.712843 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.062128 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 958293 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 57467 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 24500240 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 78456444 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 11102078 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 7139987 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 16800094 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 5031478 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 107954 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 84138717 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 105572 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 161210 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10091008 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 896138 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 4286 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 129269647 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.735584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.091589 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 106717875 87.44% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 829211 0.68% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1015415 0.83% 88.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2063306 1.69% 90.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1641471 1.34% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 615009 0.50% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2274741 1.86% 94.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 467540 0.38% 94.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6423639 5.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 112479856 87.01% 87.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 952035 0.74% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1186228 0.92% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2188812 1.69% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1732150 1.34% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 728800 0.56% 92.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2428875 1.88% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 531185 0.41% 94.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7041706 5.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 122048207 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.023426 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.171240 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23807304 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 80829213 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13786228 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 560401 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3065061 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1241341 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102643 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 81234919 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 343119 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3065061 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25364340 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34010393 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 42304537 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12707018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4596858 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74746383 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 20429 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 720817 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3279864 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33412 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 79106997 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 344419030 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 344359691 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59339 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50193146 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28913851 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 487769 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 421850 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8399849 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14034972 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8614706 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1072487 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1529720 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 67446295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1206628 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 91979521 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 109681 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18910261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53596675 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 286825 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 122048207 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.753633 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.492572 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 129269647 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.025796 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.182297 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 26260600 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 83914684 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15106265 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 652780 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3335318 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1450901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 116510 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 88966869 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 389379 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3335318 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 27931781 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34696050 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 44327698 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 14003132 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4975668 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 82212740 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 21319 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 759400 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3532141 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33925 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 86942184 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 378153831 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 378105448 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 48383 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 55944710 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 30997473 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 570448 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 494970 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9410070 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15640035 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 9547074 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1284923 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1813164 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 74425843 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1310750 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 98630822 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 132915 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 20366425 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 57377380 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 269048 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 129269647 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.762985 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.495609 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 90230410 73.93% 73.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9124502 7.48% 81.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4577298 3.75% 85.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4017634 3.29% 88.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10703333 8.77% 97.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1977632 1.62% 98.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1055737 0.87% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 281681 0.23% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 79980 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 94766617 73.31% 73.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10139907 7.84% 81.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 5158815 3.99% 85.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4427747 3.43% 88.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 11055431 8.55% 97.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2157635 1.67% 98.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1155512 0.89% 99.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 316791 0.25% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 91192 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 122048207 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 129269647 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28913 0.37% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7574685 95.84% 96.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298874 3.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 39597 0.49% 0.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1008 0.01% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7696421 95.46% 95.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 325487 4.04% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39479578 42.92% 43.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61492 0.07% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1697 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44651207 48.54% 91.88% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7471778 8.12% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 326092 0.33% 0.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 43501050 44.10% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 69634 0.07% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 16 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1718 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 46384595 47.03% 91.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 8347697 8.46% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 91979521 # Type of FU issued -system.cpu1.iq.rate 0.218796 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7903470 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.085926 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 314063875 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 87576510 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55784562 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14814 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8109 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 99561488 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7766 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 369403 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 98630822 # Type of FU issued +system.cpu1.iq.rate 0.229173 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 8062513 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.081744 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 334791339 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 96121166 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 62008917 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11647 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6672 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5500 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 106361230 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6013 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 441985 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4042367 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6847 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 22042 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1594624 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4452276 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7115 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 25628 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1723414 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965742 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1047944 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 32221586 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1050708 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3065061 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25634357 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 409319 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68777683 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 134755 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14034972 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8614706 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 896270 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 80399 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 14951 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 22042 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 226446 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 198201 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 424647 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 89117462 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43838045 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2862059 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3335318 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26012639 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 434151 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 75941872 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 151121 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15640035 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 9547074 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 940187 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 96009 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 15502 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 25628 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 268769 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 233332 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 502101 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 95691641 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 45532774 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2939181 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 124760 # number of nop insts executed -system.cpu1.iew.exec_refs 51234744 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7395685 # Number of branches executed -system.cpu1.iew.exec_stores 7396699 # Number of stores executed -system.cpu1.iew.exec_rate 0.211988 # Inst execution rate -system.cpu1.iew.wb_sent 87946957 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55791363 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30796912 # num instructions producing a value -system.cpu1.iew.wb_consumers 54575062 # num instructions consuming a value +system.cpu1.iew.exec_nop 205279 # number of nop insts executed +system.cpu1.iew.exec_refs 53793996 # number of memory reference insts executed +system.cpu1.iew.exec_branches 8312135 # Number of branches executed +system.cpu1.iew.exec_stores 8261222 # Number of stores executed +system.cpu1.iew.exec_rate 0.222344 # Inst execution rate +system.cpu1.iew.wb_sent 94462198 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 62014417 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 34071785 # num instructions producing a value +system.cpu1.iew.wb_consumers 60996509 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.132714 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.564304 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.144093 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.558586 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 19037243 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 919803 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 377326 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 119031582 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.414273 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.369590 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 20655264 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1041702 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 445913 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 125990352 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.435949 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.396620 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 101746657 85.48% 85.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8535054 7.17% 92.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2209116 1.86% 94.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1312161 1.10% 95.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1288209 1.08% 96.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 590684 0.50% 97.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 998098 0.84% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 485890 0.41% 98.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1865713 1.57% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 106643597 84.64% 84.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9506424 7.55% 92.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2528568 2.01% 94.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1530167 1.21% 95.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1425850 1.13% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 711007 0.56% 97.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1063442 0.84% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 518210 0.41% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 2063087 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 119031582 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38947564 # Number of instructions committed -system.cpu1.commit.committedOps 49311547 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 125990352 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 43322553 # Number of instructions committed +system.cpu1.commit.committedOps 54925314 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17012687 # Number of memory references committed -system.cpu1.commit.loads 9992605 # Number of loads committed -system.cpu1.commit.membars 202357 # Number of memory barriers committed -system.cpu1.commit.branches 6222202 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43701968 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556417 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1865713 # number cycles where commit BW limit reached +system.cpu1.commit.refs 19011419 # Number of memory references committed +system.cpu1.commit.loads 11187759 # Number of loads committed +system.cpu1.commit.membars 242679 # Number of memory barriers committed +system.cpu1.commit.branches 7019269 # Number of branches committed +system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 48550450 # Number of committed integer instructions. +system.cpu1.commit.function_calls 633769 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 2063087 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 184400014 # The number of ROB reads -system.cpu1.rob.rob_writes 139856425 # The number of ROB writes -system.cpu1.timesIdled 1519588 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 298341063 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4812976632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38877925 # Number of Instructions Simulated -system.cpu1.committedOps 49241908 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38877925 # Number of Instructions Simulated -system.cpu1.cpi 10.813058 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.813058 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092481 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092481 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 398800057 # number of integer regfile reads -system.cpu1.int_regfile_writes 58498146 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4943 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes -system.cpu1.misc_regfile_reads 91875872 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429758 # number of misc regfile writes -system.cpu1.icache.replacements 623101 # number of replacements -system.cpu1.icache.tagsinuse 498.730815 # Cycle average of tags in use -system.cpu1.icache.total_refs 8556871 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 623613 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.721444 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 75785780000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.730815 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974084 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974084 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8556871 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8556871 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8556871 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8556871 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8556871 # number of overall hits -system.cpu1.icache.overall_hits::total 8556871 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 673686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 673686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 673686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 673686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 673686 # number of overall misses -system.cpu1.icache.overall_misses::total 673686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10642693998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10642693998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10642693998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10642693998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10642693998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10642693998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9230557 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9230557 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9230557 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9230557 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9230557 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9230557 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072984 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.072984 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072984 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.072984 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072984 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.072984 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15797.706941 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15797.706941 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15797.706941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15797.706941 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1133998 # number of cycles access was blocked +system.cpu1.rob.rob_reads 198211439 # The number of ROB reads +system.cpu1.rob.rob_writes 154591902 # The number of ROB writes +system.cpu1.timesIdled 1579473 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 301106757 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4803892671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 43196726 # Number of Instructions Simulated +system.cpu1.committedOps 54799487 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 43196726 # Number of Instructions Simulated +system.cpu1.cpi 9.963172 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 9.963172 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.100370 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.100370 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 429674423 # number of integer regfile reads +system.cpu1.int_regfile_writes 64872300 # number of integer regfile writes +system.cpu1.fp_regfile_reads 3964 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1982 # number of floating regfile writes +system.cpu1.misc_regfile_reads 101230364 # number of misc regfile reads +system.cpu1.misc_regfile_writes 513642 # number of misc regfile writes +system.cpu1.icache.replacements 694768 # number of replacements +system.cpu1.icache.tagsinuse 498.623067 # Cycle average of tags in use +system.cpu1.icache.total_refs 9339186 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 695280 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.432266 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 75785789000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.623067 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.973873 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.973873 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 9339186 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9339186 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9339186 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9339186 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9339186 # number of overall hits +system.cpu1.icache.overall_hits::total 9339186 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 751768 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 751768 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 751768 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 751768 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 751768 # number of overall misses +system.cpu1.icache.overall_misses::total 751768 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11830653994 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11830653994 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11830653994 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11830653994 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11830653994 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11830653994 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10090954 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10090954 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10090954 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10090954 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10090954 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10090954 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074499 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.074499 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074499 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.074499 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074499 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.074499 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15737.107717 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15737.107717 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15737.107717 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15737.107717 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1257996 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 174 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 215 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6517.229885 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5851.144186 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50044 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 50044 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 50044 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 50044 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 50044 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 50044 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623642 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 623642 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 623642 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 623642 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 623642 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 623642 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8149352498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8149352498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8149352498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8149352498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8149352498 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8149352498 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 56459 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 56459 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 56459 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 56459 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 56459 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 56459 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 695309 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 695309 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 695309 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 695309 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 695309 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 695309 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9048159496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 9048159496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9048159496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 9048159496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9048159496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 9048159496 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3211500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067563 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067563 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067563 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13067.356750 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068904 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.068904 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.068904 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13013.148824 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363581 # number of replacements -system.cpu1.dcache.tagsinuse 487.223522 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13117187 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363929 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.043258 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 71474573000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.223522 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951608 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951608 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8616147 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8616147 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4254446 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4254446 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105790 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105790 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100736 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100736 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12870593 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12870593 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12870593 # number of overall hits -system.cpu1.dcache.overall_hits::total 12870593 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 410065 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 410065 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1595508 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1595508 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10912 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10912 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2005573 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2005573 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2005573 # number of overall misses -system.cpu1.dcache.overall_misses::total 2005573 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8126055000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8126055000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66044305227 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 66044305227 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166791500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 166791500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95304000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 95304000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 74170360227 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 74170360227 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 74170360227 # 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miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134818 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134818 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134818 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19816.504700 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19816.504700 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41393.904153 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41393.904153 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11681.713125 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11681.713125 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8733.870968 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8733.870968 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 36982.129410 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 36982.129410 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29670016 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5568500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6658 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4456.295584 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 32187.861272 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 413009 # number of replacements +system.cpu1.dcache.tagsinuse 487.394187 # Cycle average of tags in use +system.cpu1.dcache.total_refs 14990250 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 413521 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.250275 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 71474582000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.394187 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951942 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951942 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9825576 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9825576 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4872589 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4872589 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123205 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 123205 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 119861 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 119861 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 14698165 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 14698165 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 14698165 # number of overall hits +system.cpu1.dcache.overall_hits::total 14698165 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 478795 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 478795 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1745196 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1745196 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14728 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14728 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10805 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10805 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2223991 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2223991 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2223991 # number of overall misses +system.cpu1.dcache.overall_misses::total 2223991 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9322511500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9322511500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 69699331710 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 69699331710 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 175643000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 175643000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94845500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 94845500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 79021843210 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 79021843210 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 79021843210 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 79021843210 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10304371 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10304371 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6617785 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6617785 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137933 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 137933 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130666 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 130666 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16922156 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16922156 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16922156 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16922156 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046465 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.046465 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263713 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.263713 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106776 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106776 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.082692 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.082692 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131425 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.131425 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131425 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.131425 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19470.778726 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19470.778726 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39937.824582 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39937.824582 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11925.787615 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11925.787615 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8777.926886 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8777.926886 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35531.548109 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35531.548109 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 31184009 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5513500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4502.455819 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33213.855422 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328251 # number of writebacks -system.cpu1.dcache.writebacks::total 328251 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178277 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 178277 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432587 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1432587 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1464 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1464 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1610864 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1610864 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1610864 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1610864 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231788 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231788 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162921 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162921 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12814 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12814 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394709 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394709 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394709 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394709 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3566201462 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3566201462 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5537603585 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5537603585 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104573506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104573506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61265506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61265506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9103805047 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9103805047 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9103805047 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9103805047 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169309741500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169309741500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40933880282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40933880282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210243621782 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210243621782 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025679 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025679 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027850 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027850 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106723 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106723 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097709 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097709 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026533 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026533 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15385.617297 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15385.617297 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33989.501568 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33989.501568 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8160.879195 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8160.879195 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5616.051517 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5616.051517 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 373664 # number of writebacks +system.cpu1.dcache.writebacks::total 373664 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211355 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 211355 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1568704 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1568704 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1302 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1302 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1780059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1780059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1780059 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1780059 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267440 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 267440 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 176492 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 176492 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13426 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13426 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10800 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10800 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 443932 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 443932 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 443932 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 443932 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4040609191 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4040609191 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5818534579 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5818534579 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 114031007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 114031007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61142007 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61142007 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9859143770 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9859143770 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9859143770 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9859143770 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170666816500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170666816500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40957900116 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40957900116 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 211624716616 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 211624716616 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025954 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025954 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097337 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097337 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.082653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.082653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026234 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026234 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15108.469904 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15108.469904 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32967.695867 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32967.695867 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8493.297110 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8493.297110 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5661.296944 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5661.296944 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1667,18 +1693,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323189312111 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323189312111 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323290279244 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323290279244 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43824 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 36101 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 61677 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index c4b0f36dd..5e48f5c5e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538055 # Number of seconds simulated -sim_ticks 2538055224500 # Number of ticks simulated -final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.538087 # Number of seconds simulated +sim_ticks 2538087368500 # Number of ticks simulated +final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88262 # Simulator instruction rate (inst/s) -host_op_rate 113532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3696075323 # Simulator tick rate (ticks/s) -host_mem_usage 390228 # Number of bytes of host memory used -host_seconds 686.69 # Real time elapsed on the host -sim_insts 60608338 # Number of instructions simulated -sim_ops 77960937 # Number of ops (including micro ops) simulated +host_inst_rate 89486 # Simulator instruction rate (inst/s) +host_op_rate 115106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3747392596 # Simulator tick rate (ticks/s) +host_mem_usage 390008 # Number of bytes of host memory used +host_seconds 677.29 # Real time elapsed on the host +sim_insts 60608307 # Number of instructions simulated +sim_ops 77960925 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64349 # number of replacements -system.l2c.tagsinuse 51370.291201 # Cycle average of tags in use -system.l2c.total_refs 1966684 # Total number of references to valid blocks. -system.l2c.sampled_refs 129742 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.158422 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527049892000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36909.964338 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.537302 # Average occupied blocks per requestor +system.l2c.replacements 64372 # number of replacements +system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use +system.l2c.total_refs 1967256 # Total number of references to valid blocks. +system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8186.541319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6225.247998 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563201 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000741 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124917 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094990 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783848 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 978702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387818 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1500728 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits -system.l2c.Writeback_hits::total 608398 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112928 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112928 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500746 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613656 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122661 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11547 # number of overall hits -system.l2c.overall_hits::cpu.inst 978702 # number of overall hits -system.l2c.overall_hits::cpu.data 500746 # number of overall hits -system.l2c.overall_hits::total 1613656 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits +system.l2c.Writeback_hits::total 608347 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits +system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits +system.l2c.overall_hits::cpu.inst 978266 # number of overall hits +system.l2c.overall_hits::cpu.data 500583 # number of overall hits +system.l2c.overall_hits::total 1613985 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2903 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133164 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133164 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12372 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143855 # number of demand (read+write) misses -system.l2c.demand_misses::total 156289 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143884 # number of demand (read+write) misses +system.l2c.demand_misses::total 156312 # number of demand (read+write) misses system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::cpu.inst 507249999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5869808998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6379552997 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5320000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745798500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166751118500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32081918388 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32081918388 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5320000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198827716888 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198833036888 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026679 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015132 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015120 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088264 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,27 +332,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51779226 # DTB read hits -system.cpu.dtb.read_misses 81574 # DTB read misses -system.cpu.dtb.write_hits 11882622 # DTB write hits -system.cpu.dtb.write_misses 18093 # DTB write misses +system.cpu.dtb.read_hits 51778790 # DTB read hits +system.cpu.dtb.read_misses 81353 # DTB read misses +system.cpu.dtb.write_hits 11881898 # DTB write hits +system.cpu.dtb.write_misses 18166 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4488 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4472 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860800 # DTB read accesses -system.cpu.dtb.write_accesses 11900715 # DTB write accesses +system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51860143 # DTB read accesses +system.cpu.dtb.write_accesses 11900064 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63661848 # DTB hits -system.cpu.dtb.misses 99667 # DTB misses -system.cpu.dtb.accesses 63761515 # DTB accesses -system.cpu.itb.inst_hits 13144692 # ITB inst hits -system.cpu.itb.inst_misses 11967 # ITB inst misses +system.cpu.dtb.hits 63660688 # DTB hits +system.cpu.dtb.misses 99519 # DTB misses +system.cpu.dtb.accesses 63760207 # DTB accesses +system.cpu.itb.inst_hits 13142674 # ITB inst hits +system.cpu.itb.inst_misses 12012 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -361,122 +361,122 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2661 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13156659 # ITB inst accesses -system.cpu.itb.hits 13144692 # DTB hits -system.cpu.itb.misses 11967 # DTB misses -system.cpu.itb.accesses 13156659 # DTB accesses -system.cpu.numCycles 487285069 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154686 # ITB inst accesses +system.cpu.itb.hits 13142674 # DTB hits +system.cpu.itb.misses 12012 # DTB misses +system.cpu.itb.accesses 13154686 # DTB accesses +system.cpu.numCycles 487300785 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits +system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available @@ -504,13 +504,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued @@ -523,10 +523,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued @@ -538,361 +538,361 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued -system.cpu.iq.rate 0.259591 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued +system.cpu.iq.rate 0.259577 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255493 # number of nop insts executed -system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed -system.cpu.iew.exec_branches 11931891 # Number of branches executed -system.cpu.iew.exec_stores 12393835 # Number of stores executed -system.cpu.iew.exec_rate 0.253013 # Inst execution rate -system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47524907 # num instructions producing a value -system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value +system.cpu.iew.exec_nop 255111 # number of nop insts executed +system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed +system.cpu.iew.exec_branches 11930392 # Number of branches executed +system.cpu.iew.exec_stores 12393079 # Number of stores executed +system.cpu.iew.exec_rate 0.253002 # Inst execution rate +system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47523827 # num instructions producing a value +system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758719 # Number of instructions committed -system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60758688 # Number of instructions committed +system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520132 # Number of memory references committed -system.cpu.commit.loads 15719739 # Number of loads committed -system.cpu.commit.membars 413350 # Number of memory barriers committed -system.cpu.commit.branches 10163894 # Number of branches committed +system.cpu.commit.refs 27520186 # Number of memory references committed +system.cpu.commit.loads 15719769 # Number of loads committed +system.cpu.commit.membars 413359 # Number of memory barriers committed +system.cpu.commit.branches 10163898 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. -system.cpu.commit.function_calls 996264 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. +system.cpu.commit.function_calls 996262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256736769 # The number of ROB reads -system.cpu.rob.rob_writes 209812510 # The number of ROB writes -system.cpu.timesIdled 1906775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324667246 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588737338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608338 # Number of Instructions Simulated -system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated -system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558055785 # number of integer regfile reads -system.cpu.int_regfile_writes 90157820 # number of integer regfile writes -system.cpu.fp_regfile_reads 8288 # number of floating regfile reads -system.cpu.fp_regfile_writes 2908 # number of floating regfile writes -system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads -system.cpu.misc_regfile_writes 913357 # number of misc regfile writes -system.cpu.icache.replacements 991945 # number of replacements -system.cpu.icache.tagsinuse 511.576100 # Cycle average of tags in use -system.cpu.icache.total_refs 12062971 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992457 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.154654 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225347000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576100 # Average occupied blocks per requestor +system.cpu.rob.rob_reads 256700614 # The number of ROB reads +system.cpu.rob.rob_writes 209796185 # The number of ROB writes +system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60608307 # Number of Instructions Simulated +system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated +system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558050322 # number of integer regfile reads +system.cpu.int_regfile_writes 90161620 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads +system.cpu.misc_regfile_writes 913390 # number of misc regfile writes +system.cpu.icache.replacements 991554 # number of replacements +system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use +system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12062971 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12062971 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12062971 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12062971 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12062971 # number of overall hits -system.cpu.icache.overall_hits::total 12062971 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1077319 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1077319 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1077319 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1077319 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1077319 # number of overall misses -system.cpu.icache.overall_misses::total 1077319 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16672871489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16672871489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16672871489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16672871489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16672871489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16672871489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13140290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13140290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13140290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13140290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081986 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081986 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081986 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081986 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2904990 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits +system.cpu.icache.overall_hits::total 12061582 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses +system.cpu.icache.overall_misses::total 1076715 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 436 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6662.821101 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84824 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84824 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84824 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84824 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992495 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 992495 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 992495 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 992495 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 992495 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 992495 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12649346990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12649346990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644089 # number of replacements -system.cpu.dcache.tagsinuse 511.991456 # Cycle average of tags in use -system.cpu.dcache.total_refs 21738846 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644601 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724499 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991456 # Average occupied blocks per requestor +system.cpu.dcache.replacements 643955 # number of replacements +system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use +system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908205 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13908205 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258424 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258424 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283313 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283313 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285772 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285772 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21166629 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21166629 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21166629 # number of overall hits -system.cpu.dcache.overall_hits::total 21166629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 766922 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 766922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2994004 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2994004 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13808 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13808 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3759495 # number of overall misses +system.cpu.dcache.overall_misses::total 3759495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14876538000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14876538000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129441839072 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129441839072 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224157500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224157500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 359000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 359000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144318377072 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24926244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24926244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24926244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24926244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052182 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052182 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292007 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292007 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046437 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046437 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150825 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150825 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150825 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150825 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19428.423293 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19428.423293 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43236.852036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43236.852036 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16228.009846 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16228.009846 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22437.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 22437.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38387.702889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38387.702889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33577415 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7376000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7440 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608398 # number of writebacks -system.cpu.dcache.writebacks::total 608398 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 380638 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 380638 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2745107 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2745107 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1447 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3125745 # 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number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744878 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3124452 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3124452 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3124452 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3124452 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386136 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -914,16 +914,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index c2225df75..ef4c69b34 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.167942 # Number of seconds simulated -sim_ticks 5167941639500 # Number of ticks simulated -final_tick 5167941639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.163939 # Number of seconds simulated +sim_ticks 5163939423500 # Number of ticks simulated +final_tick 5163939423500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128954 # Simulator instruction rate (inst/s) -host_op_rate 254914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1633898837 # Simulator tick rate (ticks/s) -host_mem_usage 412792 # Number of bytes of host memory used -host_seconds 3162.95 # Real time elapsed on the host -sim_insts 407876198 # Number of instructions simulated -sim_ops 806280456 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2473280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory +host_inst_rate 202828 # Simulator instruction rate (inst/s) +host_op_rate 400952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2568035232 # Simulator tick rate (ticks/s) +host_mem_usage 368532 # Number of bytes of host memory used +host_seconds 2010.85 # Real time elapsed on the host +sim_insts 407858031 # Number of instructions simulated +sim_ops 806254969 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2460224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1074496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10579456 # Number of bytes read from this memory -system.physmem.bytes_read::total 14130624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1074496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1074496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9348288 # Number of bytes written to this memory -system.physmem.bytes_written::total 9348288 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38645 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1069888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10576384 # Number of bytes read from this memory +system.physmem.bytes_read::total 14109824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1069888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1069888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9320448 # Number of bytes written to this memory +system.physmem.bytes_written::total 9320448 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38441 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16789 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165304 # Number of read requests responded to by this memory -system.physmem.num_reads::total 220791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 146067 # Number of write requests responded to by this memory -system.physmem.num_writes::total 146067 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 478581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 582 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16717 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165256 # Number of read requests responded to by this memory +system.physmem.num_reads::total 220466 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145632 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145632 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 570 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 207916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2047131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2734285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 207916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 207916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1808900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1808900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1808900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 478581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 207184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2048123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2732376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1804910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1804910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1804910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 570 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 207916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2047131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4543184 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 109808 # number of replacements -system.l2c.tagsinuse 64836.655656 # Cycle average of tags in use -system.l2c.total_refs 3979638 # Total number of references to valid blocks. -system.l2c.sampled_refs 173786 # Sample count of references to valid blocks. -system.l2c.avg_refs 22.899647 # Average number of references to valid blocks. +system.physmem.bw_total::cpu.inst 207184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2048123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4537286 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 109190 # number of replacements +system.l2c.tagsinuse 64839.015299 # Cycle average of tags in use +system.l2c.total_refs 3984882 # Total number of references to valid blocks. +system.l2c.sampled_refs 173424 # Sample count of references to valid blocks. +system.l2c.avg_refs 22.977685 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50087.148367 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 11.882077 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.155165 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3382.932484 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11354.537562 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.764269 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000181 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 49968.765370 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 13.151051 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.155230 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3435.794855 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11421.148791 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.762463 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051619 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.173256 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989329 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 103999 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8349 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1054675 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1347003 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2514026 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1610152 # number of Writeback hits -system.l2c.Writeback_hits::total 1610152 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 315 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 315 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 158022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 158022 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 103999 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8349 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1054675 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1505025 # number of demand (read+write) hits -system.l2c.demand_hits::total 2672048 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 103999 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8349 # number of overall hits -system.l2c.overall_hits::cpu.inst 1054675 # number of overall hits -system.l2c.overall_hits::cpu.data 1505025 # number of overall hits -system.l2c.overall_hits::total 2672048 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 47 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.052426 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.174273 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989365 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 103321 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 8437 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1055749 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1347777 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2515284 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1610495 # number of Writeback hits +system.l2c.Writeback_hits::total 1610495 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 337 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 158131 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 158131 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 103321 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 8437 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1055749 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1505908 # number of demand (read+write) hits +system.l2c.demand_hits::total 2673415 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 103321 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 8437 # number of overall hits +system.l2c.overall_hits::cpu.inst 1055749 # number of overall hits +system.l2c.overall_hits::cpu.data 1505908 # number of overall hits +system.l2c.overall_hits::total 2673415 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16790 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 35954 # number of ReadReq misses -system.l2c.ReadReq_misses::total 52797 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3370 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3370 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 130295 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130295 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 47 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000718 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015669 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025996 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020568 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.914518 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.914518 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.451916 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.451916 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000718 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.015669 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 88673398500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 88673398500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2308733000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2308733000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 90982131500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 90982131500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026002 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020541 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.909433 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.909433 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.451599 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.451599 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.064056 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.064056 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40872.595092 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41157.459919 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 41066.020722 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40119.436202 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40119.436202 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.744403 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.744403 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40351.063830 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40895.585332 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41169.311553 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41081.715621 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40131.796690 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40131.796690 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.130527 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.130527 # 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average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40872.595092 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40312.023682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40363.427076 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47571 # number of replacements -system.iocache.tagsinuse 0.197047 # Cycle average of tags in use +system.iocache.replacements 47573 # number of replacements +system.iocache.tagsinuse 0.184801 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47587 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996693441000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.197047 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.012315 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.012315 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses -system.iocache.ReadReq_misses::total 906 # number of ReadReq misses +system.iocache.warmup_cycle 4996693675000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.184801 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.011550 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.011550 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # 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number of overall miss cycles -system.iocache.overall_miss_latency::total 7049863092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses +system.iocache.demand_misses::total 47628 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses +system.iocache.overall_misses::total 47628 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137681932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 137681932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9939428160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9939428160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10077110092 # 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number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +330,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150165.487859 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 150165.487859 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147984.014555 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 147984.014555 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 148025.513207 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 148025.513207 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151632.083700 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 151632.083700 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212744.609589 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 212744.609589 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 211579.534979 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 211579.534979 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72537008 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8981 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8076.718406 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 908 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47626 # 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number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47628 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47628 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47628 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47628 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90434000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 90434000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7509668946 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7509668946 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7600102946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7600102946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98130.242826 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98130.242826 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95977.267080 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 95977.267080 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99596.916300 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 99596.916300 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160737.777098 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 160737.777098 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,141 +393,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 465854401 # number of cpu cycles simulated +system.cpu.numCycles 465816448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86523106 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86523106 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1197724 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 82002674 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79454296 # Number of BTB hits +system.cpu.BPredUnit.lookups 86514848 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86514848 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1196192 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 82053392 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79452542 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31142494 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427260156 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86523106 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79454296 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164033620 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5133412 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 157235 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 72542740 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 65499 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9290212 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 538342 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3947 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 271874324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.102439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.406784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31181464 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427226624 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86514848 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79452542 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164016210 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5124580 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 155814 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 72471814 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36433 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 65503 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9296745 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 539923 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4055 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 271815204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.102878 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.406830 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 108271510 39.82% 39.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1601345 0.59% 40.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71956301 26.47% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 975717 0.36% 67.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1623613 0.60% 67.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2452165 0.90% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1122687 0.41% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1426947 0.52% 69.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82444039 30.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 108229721 39.82% 39.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1589699 0.58% 40.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71960202 26.47% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 971866 0.36% 67.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1623537 0.60% 67.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2454126 0.90% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1122252 0.41% 69.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1424890 0.52% 69.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82438911 30.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271874324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185730 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.917154 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34951113 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69967599 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159705810 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3354905 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3894897 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840212837 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1268 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3894897 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37909479 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43328722 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11932417 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159774211 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15034598 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836385126 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33598 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7166437 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5990052 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 17455 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998119194 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816357971 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816357131 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 840 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964226207 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33892980 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468339 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476044 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 32058525 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17336195 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10280230 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1246899 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 991215 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 830038809 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256743 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824423080 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186157 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23985276 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36420028 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 206597 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271874324 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.032368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.413899 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 271815204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185727 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.917157 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34976255 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 69906357 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159691682 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3353316 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3887594 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840157503 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1253 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3887594 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37933620 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43316590 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11886084 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159761513 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15029803 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836332638 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 33622 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7171271 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5982447 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 16586 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998051723 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816227596 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816227024 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 572 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964187470 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33864246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 467105 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 474137 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 32047540 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17336278 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10273791 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1251259 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 987046 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829985579 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1254715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824362930 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 185325 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23972130 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36446956 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 204607 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 271815204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.032807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.413784 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82559406 30.37% 30.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18414875 6.77% 37.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10591768 3.90% 41.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7608288 2.80% 43.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75794422 27.88% 71.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3619554 1.33% 73.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72418483 26.64% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 726775 0.27% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 140753 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82518813 30.36% 30.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18405041 6.77% 37.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10590940 3.90% 41.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7611334 2.80% 43.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75787785 27.88% 71.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3621369 1.33% 73.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72414876 26.64% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 725602 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 139444 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271874324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 271815204 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 331331 32.21% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547593 53.24% 85.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 149610 14.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 330736 32.15% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548005 53.27% 85.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150045 14.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308279 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796609033 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308450 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796558014 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -556,246 +556,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18024617 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9481151 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18020026 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9476440 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824423080 # Type of FU issued -system.cpu.iq.rate 1.769701 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1028534 # FU busy when requested +system.cpu.iq.FU_type_0::total 824362930 # Type of FU issued +system.cpu.iq.rate 1.769716 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1028786 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1922068884 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855291159 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819794003 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 201 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 398 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825143243 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1662305 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 1921889039 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 855222885 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819729616 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825083173 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1659720 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3372855 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25441 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1870494 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3372872 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25465 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11865 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1866399 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1917611 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21826 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1917615 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3894897 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28837700 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2469058 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831295552 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 338895 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17336195 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10280230 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 727529 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1778064 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16969 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 715653 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 628490 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1344143 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822456639 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17610649 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1966440 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3887594 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28830241 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2469402 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831240294 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 338803 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17336278 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10273791 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 725681 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1777576 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17730 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11865 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 713088 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 629130 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1342218 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822392031 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17604275 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1970898 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26845315 # number of memory reference insts executed -system.cpu.iew.exec_branches 83298308 # Number of branches executed -system.cpu.iew.exec_stores 9234666 # Number of stores executed -system.cpu.iew.exec_rate 1.765480 # Inst execution rate -system.cpu.iew.wb_sent 821926439 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819794057 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639752157 # num instructions producing a value -system.cpu.iew.wb_consumers 1045352654 # num instructions consuming a value +system.cpu.iew.exec_refs 26833761 # number of memory reference insts executed +system.cpu.iew.exec_branches 83292230 # Number of branches executed +system.cpu.iew.exec_stores 9229486 # Number of stores executed +system.cpu.iew.exec_rate 1.765485 # Inst execution rate +system.cpu.iew.wb_sent 821862423 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819729668 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639700217 # num instructions producing a value +system.cpu.iew.wb_consumers 1045258728 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.759765 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611996 # average fanout of values written-back +system.cpu.iew.wb_rate 1.759770 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612002 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24913133 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050144 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1202812 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267994872 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.008567 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.862606 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24883748 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1050106 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1201289 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267943051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.009053 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.862554 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95708063 35.71% 35.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12360558 4.61% 40.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3940570 1.47% 41.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74894252 27.95% 69.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2417220 0.90% 70.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1553799 0.58% 71.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1057768 0.39% 71.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70929617 26.47% 98.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5133025 1.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95668224 35.70% 35.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12347484 4.61% 40.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3939395 1.47% 41.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74898098 27.95% 69.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2419496 0.90% 70.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1554494 0.58% 71.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1057385 0.39% 71.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70928163 26.47% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5130312 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267994872 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407876198 # Number of instructions committed -system.cpu.commit.committedOps 806280456 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267943051 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407858031 # Number of instructions committed +system.cpu.commit.committedOps 806254969 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22373073 # Number of memory references committed -system.cpu.commit.loads 13963337 # Number of loads committed -system.cpu.commit.membars 471701 # Number of memory barriers committed -system.cpu.commit.branches 82186197 # Number of branches committed +system.cpu.commit.refs 22370795 # Number of memory references committed +system.cpu.commit.loads 13963403 # Number of loads committed +system.cpu.commit.membars 471705 # Number of memory barriers committed +system.cpu.commit.branches 82181312 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735221140 # Number of committed integer instructions. +system.cpu.commit.int_insts 735195017 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5133025 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5130312 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1093976833 # The number of ROB reads -system.cpu.rob.rob_writes 1666301286 # The number of ROB writes -system.cpu.timesIdled 1419086 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 193980077 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9870026331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407876198 # Number of Instructions Simulated -system.cpu.committedOps 806280456 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407876198 # Number of Instructions Simulated -system.cpu.cpi 1.142147 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.142147 # CPI: Total CPI of All Threads -system.cpu.ipc 0.875544 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.875544 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508347107 # number of integer regfile reads -system.cpu.int_regfile_writes 977902256 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.misc_regfile_reads 265221380 # number of misc regfile reads -system.cpu.misc_regfile_writes 402568 # number of misc regfile writes -system.cpu.icache.replacements 1070981 # number of replacements -system.cpu.icache.tagsinuse 510.788530 # Cycle average of tags in use -system.cpu.icache.total_refs 8144587 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1071493 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.601157 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1093872885 # The number of ROB reads +system.cpu.rob.rob_writes 1666184214 # The number of ROB writes +system.cpu.timesIdled 1421273 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 194001244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9862059849 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407858031 # Number of Instructions Simulated +system.cpu.committedOps 806254969 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407858031 # Number of Instructions Simulated +system.cpu.cpi 1.142104 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.142104 # CPI: Total CPI of All Threads +system.cpu.ipc 0.875577 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.875577 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508209791 # number of integer regfile reads +system.cpu.int_regfile_writes 977816443 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.misc_regfile_reads 265196274 # number of misc regfile reads +system.cpu.misc_regfile_writes 402502 # number of misc regfile writes +system.cpu.icache.replacements 1071989 # number of replacements +system.cpu.icache.tagsinuse 510.817098 # Cycle average of tags in use +system.cpu.icache.total_refs 8149627 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1072501 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.598713 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 147426882000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.788530 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997634 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997634 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8144587 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8144587 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8144587 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8144587 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8144587 # number of overall hits -system.cpu.icache.overall_hits::total 8144587 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1145619 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1145619 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1145619 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1145619 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1145619 # number of overall misses -system.cpu.icache.overall_misses::total 1145619 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18957217490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18957217490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18957217490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18957217490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18957217490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18957217490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9290206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9290206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9290206 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9290206 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9290206 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9290206 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123315 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123315 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123315 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123315 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123315 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123315 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16547.576018 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16547.576018 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16547.576018 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16547.576018 # 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mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115580 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115580 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13787.270193 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13787.270193 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13787.270193 # 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average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,78 +804,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1799 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1799 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10696 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10696 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10696 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10696 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10696 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10696 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143761538 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143761538 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143761538 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143761538 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143761538 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143761538 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245119 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245119 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245102 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245102 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13440.682311 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10825 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10825 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10825 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10825 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10825 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10825 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 145034027 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 145034027 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 145034027 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 145034027 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 145034027 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 145034027 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245181 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245181 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245165 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245165 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13398.062540 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109374 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.962684 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 139077 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109389 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.271398 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108961672000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.962684 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810168 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.810168 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139087 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 139087 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139087 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 139087 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139087 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 139087 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110364 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110364 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110364 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110364 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110364 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110364 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2009314000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2009314000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2009314000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2009314000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2009314000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2009314000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249451 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 249451 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249451 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 249451 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249451 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 249451 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442428 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442428 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442428 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442428 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442428 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442428 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18206.244790 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18206.244790 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18206.244790 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18206.244790 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109056 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.865602 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 139886 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109072 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.282511 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5108962066000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.865602 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866600 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.866600 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139886 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 139886 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 139886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139886 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 139886 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110096 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110096 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110096 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110096 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110096 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110096 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2001823500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2001823500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2001823500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2001823500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2001823500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2001823500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249982 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 249982 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249982 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 249982 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249982 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 249982 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.440416 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.440416 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.440416 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.440416 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.440416 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.440416 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18182.527067 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18182.527067 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18182.527067 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -884,146 +884,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35688 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35688 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110364 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110364 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110364 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110364 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110364 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110364 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1675589507 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1675589507 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1675589507 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442428 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442428 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442428 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15182.391967 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35215 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35215 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110096 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110096 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110096 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110096 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110096 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110096 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1668892003 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1668892003 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1668892003 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.440416 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.440416 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.440416 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15158.516231 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1671342 # number of replacements -system.cpu.dcache.tagsinuse 511.998194 # Cycle average of tags in use -system.cpu.dcache.total_refs 19219573 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1671854 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.495964 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1672208 # number of replacements +system.cpu.dcache.tagsinuse 511.998155 # Cycle average of tags in use +system.cpu.dcache.total_refs 19212274 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1672720 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.485649 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 35774000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998194 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.998155 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11132776 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11132776 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8081984 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8081984 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19214760 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19214760 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19214760 # number of overall hits -system.cpu.dcache.overall_hits::total 19214760 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2269875 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2269875 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318465 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318465 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2588340 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2588340 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2588340 # number of overall misses -system.cpu.dcache.overall_misses::total 2588340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48782293500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48782293500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10759861985 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10759861985 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 59542155485 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 59542155485 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 59542155485 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 59542155485 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13402651 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13402651 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8400449 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8400449 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21803100 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21803100 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21803100 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21803100 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037910 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037910 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118714 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118714 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118714 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21491.180572 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21491.180572 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33786.638987 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33786.638987 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23003.993094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23003.993094 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 188390485 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 11127928 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11127928 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8079547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8079547 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19207475 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19207475 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19207475 # number of overall hits +system.cpu.dcache.overall_hits::total 19207475 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2271021 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2271021 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318564 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318564 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2589585 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2589585 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2589585 # number of overall misses +system.cpu.dcache.overall_misses::total 2589585 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48812772000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48812772000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10760956984 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10760956984 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 59573728984 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 59573728984 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 59573728984 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 59573728984 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13398949 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13398949 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8398111 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398111 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21797060 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21797060 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21797060 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21797060 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169492 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169492 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037933 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037933 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118804 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118804 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118804 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118804 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21493.756333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21493.756333 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33779.576424 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33779.576424 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23005.125912 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23005.125912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23005.125912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23005.125912 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 188289984 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 47569 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 47618 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3960.362526 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3954.176656 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1572665 # number of writebacks -system.cpu.dcache.writebacks::total 1572665 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885789 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 885789 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26582 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 26582 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 912371 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912371 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 912371 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912371 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1384086 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1384086 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291883 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291883 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1675969 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1675969 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1675969 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1675969 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25963695523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25963695523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9454770488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9454770488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35418466011 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 35418466011 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35418466011 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 35418466011 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96735790500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96735790500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2476089500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2476089500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99211880000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99211880000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034746 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034746 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076868 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076868 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076868 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076868 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18758.729965 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18758.729965 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32392.330105 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32392.330105 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21133.127171 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21133.127171 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21133.127171 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21133.127171 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1573408 # number of writebacks +system.cpu.dcache.writebacks::total 1573408 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 886097 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 886097 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26577 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26577 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912674 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912674 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912674 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912674 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1384924 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1384924 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291987 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291987 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1676911 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1676911 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1676911 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1676911 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25980128023 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25980128023 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9456082986 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9456082986 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35436211009 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 35436211009 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35436211009 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 35436211009 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96735395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96735395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2475863500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2475863500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99211259000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99211259000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034768 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034768 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076933 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076933 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076933 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076933 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18759.244567 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18759.244567 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32385.287653 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32385.287653 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21131.837652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21131.837652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21131.837652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21131.837652 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |