diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/long/fs | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/fs')
51 files changed, 26125 insertions, 25960 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini index 2b85e262c..961681a43 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini @@ -25,7 +25,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:134217727 +mem_ranges=0:134217727:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false @@ -60,7 +60,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=8796093022208:18446744073709551615 +ranges=8796093022208:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -170,7 +170,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -604,7 +604,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -664,7 +664,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -827,7 +827,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=Cache children=tags -addr_ranges=0:134217727 +addr_ranges=0:134217727:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -872,7 +872,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -884,7 +884,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -916,29 +916,36 @@ update_data=false warn_access= pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -958,6 +965,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -967,7 +975,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -989,9 +997,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout index 7ccffc14c..98915ba59 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:23 -gem5 executing on e108600-lin, pid 39539 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:46 +gem5 executing on e108600-lin, pid 28076 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-minor Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1909061460000 because m5_exit instruction encountered +Exiting @ tick 1893220881500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index e646f5b40..3b8894174 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.889223 # Number of seconds simulated -sim_ticks 1889223246000 # Number of ticks simulated -final_tick 1889223246000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.893221 # Number of seconds simulated +sim_ticks 1893220881500 # Number of ticks simulated +final_tick 1893220881500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22780 # Simulator instruction rate (inst/s) -host_op_rate 22780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 766551699 # Simulator tick rate (ticks/s) -host_mem_usage 396616 # Number of bytes of host memory used -host_seconds 2464.57 # Real time elapsed on the host -sim_insts 56141873 # Number of instructions simulated -sim_ops 56141873 # Number of ops (including micro ops) simulated +host_inst_rate 15759 # Simulator instruction rate (inst/s) +host_op_rate 15759 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 531367557 # Simulator tick rate (ticks/s) +host_mem_usage 390932 # Number of bytes of host memory used +host_seconds 3562.92 # Real time elapsed on the host +sim_insts 56147815 # Number of instructions simulated +sim_ops 56147815 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859008 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1046208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860800 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25907520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory -system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388422 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25907968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1046208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1046208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7566592 # Number of bytes written to this memory +system.physmem.bytes_written::total 7566592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388450 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404805 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 554488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13158322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13713318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 554488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 554488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4005100 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4005100 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4005100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 554488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13158322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17718418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404805 # Number of read requests accepted -system.physmem.writeReqs 118227 # Number of write requests accepted -system.physmem.readBursts 404805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 7565120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25907520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 404812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118228 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118228 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 552607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13131484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13684599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3996677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3996677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3996677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13131484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17681276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404812 # Number of read requests accepted +system.physmem.writeReqs 118228 # Number of write requests accepted +system.physmem.readBursts 404812 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118228 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25900544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 7565312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25907968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7566592 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25470 # Per bank write bursts -system.physmem.perBankRdBursts::1 25713 # Per bank write bursts -system.physmem.perBankRdBursts::2 25812 # Per bank write bursts -system.physmem.perBankRdBursts::3 25774 # Per bank write bursts -system.physmem.perBankRdBursts::4 25230 # Per bank write bursts -system.physmem.perBankRdBursts::5 24950 # Per bank write bursts -system.physmem.perBankRdBursts::6 24793 # Per bank write bursts -system.physmem.perBankRdBursts::7 24569 # Per bank write bursts -system.physmem.perBankRdBursts::8 25113 # Per bank write bursts -system.physmem.perBankRdBursts::9 25266 # Per bank write bursts -system.physmem.perBankRdBursts::10 25525 # Per bank write bursts -system.physmem.perBankRdBursts::11 24857 # Per bank write bursts -system.physmem.perBankRdBursts::12 24533 # Per bank write bursts -system.physmem.perBankRdBursts::13 25560 # Per bank write bursts -system.physmem.perBankRdBursts::14 25804 # Per bank write bursts -system.physmem.perBankRdBursts::15 25731 # Per bank write bursts -system.physmem.perBankWrBursts::0 7815 # Per bank write bursts -system.physmem.perBankWrBursts::1 7678 # Per bank write bursts -system.physmem.perBankWrBursts::2 8068 # Per bank write bursts -system.physmem.perBankWrBursts::3 7736 # Per bank write bursts -system.physmem.perBankWrBursts::4 7326 # Per bank write bursts -system.physmem.perBankWrBursts::5 6953 # Per bank write bursts -system.physmem.perBankWrBursts::6 6780 # Per bank write bursts -system.physmem.perBankWrBursts::7 6420 # Per bank write bursts -system.physmem.perBankWrBursts::8 7238 # Per bank write bursts -system.physmem.perBankWrBursts::9 6883 # Per bank write bursts -system.physmem.perBankWrBursts::10 7397 # Per bank write bursts -system.physmem.perBankWrBursts::11 6875 # Per bank write bursts -system.physmem.perBankWrBursts::12 7088 # Per bank write bursts -system.physmem.perBankWrBursts::13 8006 # Per bank write bursts -system.physmem.perBankWrBursts::14 7993 # Per bank write bursts -system.physmem.perBankWrBursts::15 7949 # Per bank write bursts +system.physmem.perBankRdBursts::0 25483 # Per bank write bursts +system.physmem.perBankRdBursts::1 25705 # Per bank write bursts +system.physmem.perBankRdBursts::2 25813 # Per bank write bursts +system.physmem.perBankRdBursts::3 25775 # Per bank write bursts +system.physmem.perBankRdBursts::4 25223 # Per bank write bursts +system.physmem.perBankRdBursts::5 24955 # Per bank write bursts +system.physmem.perBankRdBursts::6 24789 # Per bank write bursts +system.physmem.perBankRdBursts::7 24583 # Per bank write bursts +system.physmem.perBankRdBursts::8 25108 # Per bank write bursts +system.physmem.perBankRdBursts::9 25258 # Per bank write bursts +system.physmem.perBankRdBursts::10 25518 # Per bank write bursts +system.physmem.perBankRdBursts::11 24875 # Per bank write bursts +system.physmem.perBankRdBursts::12 24528 # Per bank write bursts +system.physmem.perBankRdBursts::13 25564 # Per bank write bursts +system.physmem.perBankRdBursts::14 25798 # Per bank write bursts +system.physmem.perBankRdBursts::15 25721 # Per bank write bursts +system.physmem.perBankWrBursts::0 7829 # Per bank write bursts +system.physmem.perBankWrBursts::1 7671 # Per bank write bursts +system.physmem.perBankWrBursts::2 8071 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts +system.physmem.perBankWrBursts::4 7318 # Per bank write bursts +system.physmem.perBankWrBursts::5 6944 # Per bank write bursts +system.physmem.perBankWrBursts::6 6788 # Per bank write bursts +system.physmem.perBankWrBursts::7 6427 # Per bank write bursts +system.physmem.perBankWrBursts::8 7237 # Per bank write bursts +system.physmem.perBankWrBursts::9 6873 # Per bank write bursts +system.physmem.perBankWrBursts::10 7386 # Per bank write bursts +system.physmem.perBankWrBursts::11 6888 # Per bank write bursts +system.physmem.perBankWrBursts::12 7081 # Per bank write bursts +system.physmem.perBankWrBursts::13 8010 # Per bank write bursts +system.physmem.perBankWrBursts::14 7995 # Per bank write bursts +system.physmem.perBankWrBursts::15 7945 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 1889214280000 # Total gap between requests +system.physmem.numWrRetry 68 # Number of times write queue was full causing retry +system.physmem.totGap 1893211891000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404805 # Read request sizes (log2) +system.physmem.readPktSize::6 404812 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118227 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118228 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,193 +149,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63746 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 524.988548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.641335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 414.335221 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14725 23.10% 23.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10901 17.10% 40.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5357 8.40% 48.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3110 4.88% 53.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2601 4.08% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1701 2.67% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1560 2.45% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1439 2.26% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22352 35.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63746 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.386372 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2900.765356 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5295 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 528.527867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 322.547536 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.556682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14397 22.74% 22.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11107 17.54% 40.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4705 7.43% 47.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3113 4.92% 52.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2233 3.53% 56.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2328 3.68% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1953 3.08% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1598 2.52% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21885 34.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63319 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5233 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.334798 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2918.735904 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5230 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5298 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.311250 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.880356 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.145944 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4698 88.67% 88.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.62% 89.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 235 4.44% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 22 0.42% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 12 0.23% 94.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.26% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 10 0.19% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.08% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 30 0.57% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 15 0.28% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 179 3.38% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 1 0.02% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.02% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.08% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 12 0.23% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 2 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.08% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 8 0.15% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5298 # Writes before turning the bus around for reads -system.physmem.totQLat 2164522000 # Total ticks spent queuing -system.physmem.totMemAccLat 9752647000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5348.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5233 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5233 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.588955 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.741886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.816216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4718 90.16% 90.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.63% 90.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 174 3.33% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 5 0.10% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 12 0.23% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.15% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1 0.02% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 32 0.61% 95.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 151 2.89% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 15 0.29% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 10 0.19% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 3 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 10 0.19% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.11% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 12 0.23% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.17% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 5 0.10% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.08% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5233 # Writes before turning the bus around for reads +system.physmem.totQLat 5895300250 # Total ticks spent queuing +system.physmem.totMemAccLat 13483350250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023480000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14567.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24098.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33317.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.71 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 363251 # Number of row buffer hits during reads -system.physmem.writeRowHits 95908 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.12 # Row buffer hit rate for writes -system.physmem.avgGap 3612043.39 # Average gap between requests -system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 234556560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127982250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578025800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 380868480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60772181625 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1080221277750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1266709348065 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.494357 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1796832063750 # Time in different power states -system.physmem_0.memoryStateTime::REF 63085100000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29299865000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247363200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134970000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1578634200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385099920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61856765370 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1079269896750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1266867185040 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.577899 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1795248089750 # Time in different power states -system.physmem_1.memoryStateTime::REF 63085100000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30883852750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15253451 # Number of BP lookups -system.cpu.branchPred.condPredicted 13119801 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 515637 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12113296 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4570787 # Number of BTB hits +system.physmem.avgWrQLen 24.81 # Average write queue length when enqueuing +system.physmem.readRowHits 363810 # Number of row buffer hits during reads +system.physmem.writeRowHits 95775 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes +system.physmem.avgGap 3619631.18 # Average gap between requests +system.physmem.pageHitRate 87.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 221882640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 117933420 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1444607640 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4693391040.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4737017490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 303974400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10896307530 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 5550083520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 443242644240 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 471515616450 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.054730 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1881921702000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 481983250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1993748000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1843690402750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 14453321750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8706248250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23895177500 # Time in different power states +system.physmem_1.actEnergy 230215020 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122362185 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 310146300 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4816933680.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4925461770 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 303573120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11119407240 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 5660238720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 442986687510 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 471921610125 # Total energy per rank (pJ) +system.physmem_1.averagePower 249.269176 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1881622925500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 484393500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2046440000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1842500290250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 14740166500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9065047000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24384544250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15264339 # Number of BP lookups +system.cpu.branchPred.condPredicted 13122374 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 525708 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12102111 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4571092 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.733636 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 859438 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30658 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6570706 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 545483 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 6025223 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 218035 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.771030 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 863726 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33596 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6525159 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 541190 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5983969 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 222121 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9316925 # DTB read hits -system.cpu.dtb.read_misses 17695 # DTB read misses +system.cpu.dtb.read_hits 9321681 # DTB read hits +system.cpu.dtb.read_misses 17691 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764827 # DTB read accesses -system.cpu.dtb.write_hits 6393212 # DTB write hits +system.cpu.dtb.read_accesses 764795 # DTB read accesses +system.cpu.dtb.write_hits 6394158 # DTB write hits system.cpu.dtb.write_misses 2442 # DTB write misses -system.cpu.dtb.write_acv 158 # DTB write access violations -system.cpu.dtb.write_accesses 298820 # DTB write accesses -system.cpu.dtb.data_hits 15710137 # DTB hits -system.cpu.dtb.data_misses 20137 # DTB misses -system.cpu.dtb.data_acv 369 # DTB access violations -system.cpu.dtb.data_accesses 1063647 # DTB accesses -system.cpu.itb.fetch_hits 4018824 # ITB hits -system.cpu.itb.fetch_misses 6310 # ITB misses -system.cpu.itb.fetch_acv 701 # ITB acv -system.cpu.itb.fetch_accesses 4025134 # ITB accesses +system.cpu.dtb.write_acv 159 # DTB write access violations +system.cpu.dtb.write_accesses 298776 # DTB write accesses +system.cpu.dtb.data_hits 15715839 # DTB hits +system.cpu.dtb.data_misses 20133 # DTB misses +system.cpu.dtb.data_acv 370 # DTB access violations +system.cpu.dtb.data_accesses 1063571 # DTB accesses +system.cpu.itb.fetch_hits 4020046 # ITB hits +system.cpu.itb.fetch_misses 6280 # ITB misses +system.cpu.itb.fetch_acv 699 # ITB acv +system.cpu.itb.fetch_accesses 4026326 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -350,27 +363,27 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12752 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281746974.905897 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439847984.325030 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281786440.323087 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439974345.162947 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 19000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 369000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 92804534000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796418712000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 185630526 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 96550538000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796670343500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 193121889 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56141873 # Number of instructions committed -system.cpu.committedOps 56141873 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2958149 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 56147815 # Number of instructions committed +system.cpu.committedOps 56147815 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2978612 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3592815966 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.306454 # CPI: cycles per instruction -system.cpu.ipc 0.302439 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199005 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36197195 64.47% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60822 0.11% 70.28% # Class of committed instruction +system.cpu.quiesceCycles 3593319874 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.439526 # CPI: cycles per instruction +system.cpu.ipc 0.290738 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199269 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36201024 64.47% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60831 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -398,34 +411,34 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9319321 16.60% 86.95% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6372729 11.35% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 951086 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 9320403 16.60% 86.95% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6373341 11.35% 98.31% # Class of committed instruction +system.cpu.op_class_0::IprAccess 951232 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56141873 # Class of committed instruction +system.cpu.op_class_0::total 56147815 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211498 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74792 40.94% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1903 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105883 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182709 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73425 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.hwrei 211531 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74800 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105905 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182741 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73433 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1903 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73425 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148884 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1835945903000 97.18% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 85568000 0.00% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 710063500 0.04% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 52480708000 2.78% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1889222242500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73433 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148902 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837683771000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 86162500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 712688000 0.04% 97.11% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54737244500 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1893219866000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693454 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814870 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693386 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814825 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -464,514 +477,514 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175546 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175574 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5128 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192434 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches +system.cpu.kern.callpal::total 192465 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2091 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches system.cpu.kern.mode_good::kernel 1905 system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324200 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324255 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080344 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36856948000 1.95% 1.95% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4192339500 0.22% 2.17% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1848172945000 97.83% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392541 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 37297482500 1.97% 1.97% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4311459500 0.23% 2.20% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1851610914000 97.80% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85233988 # Number of cycles that the object actually ticked -system.cpu.idleCycles 100396538 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394263 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980931 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13942036 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394775 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.995903 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 94238500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980931 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy +system.cpu.tickCycles 85352026 # Number of cycles that the object actually ticked +system.cpu.idleCycles 107769863 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394246 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13946627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394758 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.999317 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63909041 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63909041 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7981560 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7981560 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5577988 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5577988 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183448 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183448 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199007 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199007 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13559548 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13559548 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13559548 # number of overall hits -system.cpu.dcache.overall_hits::total 13559548 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096304 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096304 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573678 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16581 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16581 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1669982 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1669982 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1669982 # number of overall misses -system.cpu.dcache.overall_misses::total 1669982 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31558344500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31558344500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22538815500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22538815500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222577500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222577500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54097160000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54097160000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54097160000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54097160000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9077864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9077864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6151666 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6151666 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199007 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199007 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15229530 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15229530 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15229530 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15229530 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120767 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120767 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093256 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093256 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082893 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082893 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109654 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109654 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109654 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109654 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28786.125472 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28786.125472 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39288.268855 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39288.268855 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.647548 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13423.647548 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32393.858137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32393.858137 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63927104 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63927104 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7985415 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7985415 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5578562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5578562 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183593 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183593 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199022 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199022 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13563977 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13563977 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13563977 # number of overall hits +system.cpu.dcache.overall_hits::total 13563977 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096352 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096352 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573692 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573692 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16450 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16450 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1670044 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1670044 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1670044 # number of overall misses +system.cpu.dcache.overall_misses::total 1670044 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33571810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33571810000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25337965000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25337965000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222587500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222587500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 58909775000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 58909775000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 58909775000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 58909775000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9081767 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9081767 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152254 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152254 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200043 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200043 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199022 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199022 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15234021 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15234021 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15234021 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15234021 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120720 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120720 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093249 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.109626 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109626 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109626 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109626 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30621.378900 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30621.378900 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44166.495262 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44166.495262 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13531.155015 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13531.155015 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35274.384986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35274.384986 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837697 # number of writebacks -system.cpu.dcache.writebacks::total 837697 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269759 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269759 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837664 # number of writebacks +system.cpu.dcache.writebacks::total 837664 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21993 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21993 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269693 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269693 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291740 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291740 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291740 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291740 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074323 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074323 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303919 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 303919 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16578 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16578 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378242 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378242 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378242 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378242 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291686 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291686 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291686 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291686 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074359 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074359 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303999 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 303999 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16447 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16447 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378358 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378358 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378358 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378358 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16551 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16551 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30011433500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30011433500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11481403000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11481403000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205832000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205832000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41492836500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41492836500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41492836500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41492836500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534160500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534160500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534160500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534160500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118345 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118345 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049404 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049404 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082878 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082878 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090498 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090498 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27935.205241 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27935.205241 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37777.838832 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37777.838832 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12415.972976 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12415.972976 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.581530 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.581530 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92692.918857 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92692.918857 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1476241 # number of replacements -system.cpu.icache.tags.tagsinuse 509.437018 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19208652 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1476752 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.007365 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 33938325500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.437018 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994994 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994994 # Average percentage of cache occupancy +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32011150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32011150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12927980000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12927980000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205437000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205437000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44939130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44939130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44939130000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44939130000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534184500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534184500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534184500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534184500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118298 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118298 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049413 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049413 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082217 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082217 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090479 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090479 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29795.580434 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29795.580434 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42526.389889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42526.389889 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12490.849395 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12490.849395 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221383.044733 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221383.044733 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92683.169214 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92683.169214 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1477105 # number of replacements +system.cpu.icache.tags.tagsinuse 509.256263 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19233040 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1477616 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.016264 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 36168250500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.256263 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # 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Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5334629 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405144 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.167242 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6356009000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 267.504634 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5791.332200 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59357.491346 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004082 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088369 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.905723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998174 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1477105 # number of writebacks +system.cpu.icache.writebacks::total 1477105 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477790 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1477790 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1477790 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1477790 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1477790 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1477790 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19218793500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19218793500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19218793500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19218793500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19218793500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19218793500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071353 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071353 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071353 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13005.091048 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13005.091048 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59330 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 578 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 457 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59344 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 46327377 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 46327377 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 837697 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 837697 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71510.018938 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71510.018938 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63343.767334 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63343.767334 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87457.857531 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87457.857531 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5742250 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2870700 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1972 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9332571500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9332571500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1455004000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1455004000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19244147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19244147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1455004000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28576719000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30031723000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1455004000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28576719000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30031723000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447540500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447540500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447540500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447540500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383711 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383711 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011063 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249571 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249571 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141070 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141070 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80003.527586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80003.527586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 89001.957426 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 89001.957426 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70691.805706 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70691.805706 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208880.303030 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208880.303030 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.831028 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.831028 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5743946 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871549 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2574859 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1476241 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 303930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 303930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1476926 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4430038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217161 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8647199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188999168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142932652 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 331931820 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340234 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923264 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3228320 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000974 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031197 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 2575626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 914380 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1477105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1090934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 242 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4432629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217118 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8649747 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189109696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142929468 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 332039164 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340242 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923392 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3229178 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000972 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031158 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3225175 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3145 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3226040 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3138 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3228320 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5198149000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3229178 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5199830000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2215530716 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2216814740 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2103938977 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2103909988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -985,12 +998,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51173 # Transaction distribution -system.iobus.trans_dist::WriteResp 51173 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5098 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51175 # Transaction distribution +system.iobus.trans_dist::WriteResp 51175 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -999,11 +1012,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116552 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1012,50 +1025,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44332 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705940 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5405000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5417000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 800000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 803500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 182000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14495500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15637500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5973000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6005000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216181312 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216245035 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23481000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.301361 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.299106 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1731952426000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.301361 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081335 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081335 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1735874546000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.299106 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081194 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081194 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1064,14 +1077,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21934383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21934383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4859195929 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4859195929 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4881130312 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4881130312 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4881130312 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4881130312 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22024383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22024383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948308652 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4948308652 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4970333035 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4970333035 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4970333035 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4970333035 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1088,19 +1101,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126788.341040 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126788.341040 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116942.528133 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116942.528133 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116983.350797 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116983.350797 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127308.572254 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 127308.572254 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119087.135445 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119087.135445 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119121.223128 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119121.223128 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1402 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 107.846154 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1112,14 +1125,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13284383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13284383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2779181979 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2779181979 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2792466362 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2792466362 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2792466362 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2792466362 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13374383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13374383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868251757 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2868251757 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2881626140 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2881626140 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2881626140 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2881626140 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1128,75 +1141,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76788.341040 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76788.341040 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66884.433457 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66884.433457 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827436 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381422 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77308.572254 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 77308.572254 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69028.007244 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69028.007244 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827498 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381477 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295668 # Transaction distribution -system.membus.trans_dist::WriteReq 9621 # Transaction distribution -system.membus.trans_dist::WriteResp 9621 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution -system.membus.trans_dist::CleanEvict 262241 # Transaction distribution -system.membus.trans_dist::UpgradeReq 137 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116498 # Transaction distribution -system.membus.trans_dist::ReadExResp 116498 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288761 # Transaction distribution -system.membus.trans_dist::BadAddressError 23 # Transaction distribution +system.membus.trans_dist::ReadResp 295653 # Transaction distribution +system.membus.trans_dist::WriteReq 9623 # Transaction distribution +system.membus.trans_dist::WriteResp 9623 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118228 # Transaction distribution +system.membus.trans_dist::CleanEvict 262245 # Transaction distribution +system.membus.trans_dist::UpgradeReq 138 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 116520 # Transaction distribution +system.membus.trans_dist::ReadExResp 116520 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288747 # Transaction distribution +system.membus.trans_dist::BadAddressError 24 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148773 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181947 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265346 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44332 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860652 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1265372 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30861180 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33518380 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 433 # Total snoops (count) +system.membus.pkt_size::total 33518908 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 434 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463499 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001458 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038162 # Request fanout histogram +system.membus.snoop_fanout::samples 463510 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001463 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038218 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462823 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 676 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463499 # Request fanout histogram -system.membus.reqLayer0.occupancy 29272500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463510 # Request fanout histogram +system.membus.reqLayer0.occupancy 30461000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319341290 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319556082 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160301000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160064000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1228,28 +1241,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal index 2c979b67f..b49f55c8a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index ac0bee128..7fa651550 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -25,7 +25,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:134217727 +mem_ranges=0:134217727:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false @@ -60,7 +60,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=8796093022208:18446744073709551615 +ranges=8796093022208:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -194,7 +194,7 @@ useIndirect=true [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -733,7 +733,7 @@ useIndirect=true [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1091,7 +1091,7 @@ pipelined=false [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1239,7 +1239,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=Cache children=tags -addr_ranges=0:134217727 +addr_ranges=0:134217727:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -1285,7 +1285,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1383,27 +1383,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1423,6 +1423,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1432,7 +1433,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1454,9 +1455,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index b3e079503..1abbf975c 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -3,14 +3,14 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:23 -gem5 executing on e108600-lin, pid 39569 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:46 +gem5 executing on e108600-lin, pid 28085 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 127844500 -Exiting @ tick 1907672102500 because m5_exit instruction encountered +info: Launching CPU 1 @ 133768500 +Exiting @ tick 1907549438500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index dfe837c06..2752814bd 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906534 # Number of seconds simulated -sim_ticks 1906533530000 # Number of ticks simulated -final_tick 1906533530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.907549 # Number of seconds simulated +sim_ticks 1907549438500 # Number of ticks simulated +final_tick 1907549438500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134861 # Simulator instruction rate (inst/s) -host_op_rate 134861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4533949866 # Simulator tick rate (ticks/s) -host_mem_usage 343876 # Number of bytes of host memory used -host_seconds 420.50 # Real time elapsed on the host -sim_insts 56709432 # Number of instructions simulated -sim_ops 56709432 # Number of ops (including micro ops) simulated +host_inst_rate 120882 # Simulator instruction rate (inst/s) +host_op_rate 120882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4068519298 # Simulator tick rate (ticks/s) +host_mem_usage 339992 # Number of bytes of host memory used +host_seconds 468.86 # Real time elapsed on the host +sim_insts 56676315 # Number of instructions simulated +sim_ops 56676315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 896192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24492096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 81664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 812544 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 857728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24440448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 121088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26283456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 896192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 81664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7904832 # Number of bytes written to this memory -system.physmem.bytes_written::total 7904832 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14003 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 382689 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12696 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26308480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 857728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 121088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7911424 # Number of bytes written to this memory +system.physmem.bytes_written::total 7911424 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13402 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 381882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410679 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123513 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123513 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 470064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12846402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 426189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13785992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 470064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512897 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4146180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4146180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4146180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 470064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12846402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 426189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17932172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410679 # Number of read requests accepted -system.physmem.writeReqs 123513 # Number of write requests accepted -system.physmem.readBursts 410679 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123513 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26276352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7903488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26283456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7904832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 411070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123616 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123616 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12812485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 465653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13791768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63478 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4147428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4147428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4147428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12812485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 465653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17939196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411070 # Number of read requests accepted +system.physmem.writeReqs 123616 # Number of write requests accepted +system.physmem.readBursts 411070 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123616 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26300288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue +system.physmem.bytesWritten 7909696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26308480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7911424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26110 # Per bank write bursts -system.physmem.perBankRdBursts::1 26073 # Per bank write bursts -system.physmem.perBankRdBursts::2 25765 # Per bank write bursts -system.physmem.perBankRdBursts::3 25777 # Per bank write bursts -system.physmem.perBankRdBursts::4 25805 # Per bank write bursts -system.physmem.perBankRdBursts::5 25558 # Per bank write bursts -system.physmem.perBankRdBursts::6 25453 # Per bank write bursts -system.physmem.perBankRdBursts::7 25268 # Per bank write bursts -system.physmem.perBankRdBursts::8 25514 # Per bank write bursts -system.physmem.perBankRdBursts::9 25670 # Per bank write bursts -system.physmem.perBankRdBursts::10 25901 # Per bank write bursts -system.physmem.perBankRdBursts::11 25385 # Per bank write bursts -system.physmem.perBankRdBursts::12 25810 # Per bank write bursts -system.physmem.perBankRdBursts::13 25833 # Per bank write bursts -system.physmem.perBankRdBursts::14 25046 # Per bank write bursts -system.physmem.perBankRdBursts::15 25600 # Per bank write bursts -system.physmem.perBankWrBursts::0 8438 # Per bank write bursts -system.physmem.perBankWrBursts::1 8395 # Per bank write bursts -system.physmem.perBankWrBursts::2 7934 # Per bank write bursts -system.physmem.perBankWrBursts::3 7573 # Per bank write bursts -system.physmem.perBankWrBursts::4 7567 # Per bank write bursts -system.physmem.perBankWrBursts::5 7501 # Per bank write bursts -system.physmem.perBankWrBursts::6 7444 # Per bank write bursts -system.physmem.perBankWrBursts::7 7061 # Per bank write bursts -system.physmem.perBankWrBursts::8 7349 # Per bank write bursts -system.physmem.perBankWrBursts::9 7703 # Per bank write bursts -system.physmem.perBankWrBursts::10 7693 # Per bank write bursts -system.physmem.perBankWrBursts::11 7415 # Per bank write bursts -system.physmem.perBankWrBursts::12 7960 # Per bank write bursts -system.physmem.perBankWrBursts::13 8226 # Per bank write bursts -system.physmem.perBankWrBursts::14 7426 # Per bank write bursts -system.physmem.perBankWrBursts::15 7807 # Per bank write bursts +system.physmem.perBankRdBursts::0 26240 # Per bank write bursts +system.physmem.perBankRdBursts::1 25986 # Per bank write bursts +system.physmem.perBankRdBursts::2 25958 # Per bank write bursts +system.physmem.perBankRdBursts::3 25690 # Per bank write bursts +system.physmem.perBankRdBursts::4 25582 # Per bank write bursts +system.physmem.perBankRdBursts::5 25570 # Per bank write bursts +system.physmem.perBankRdBursts::6 25628 # Per bank write bursts +system.physmem.perBankRdBursts::7 25343 # Per bank write bursts +system.physmem.perBankRdBursts::8 25590 # Per bank write bursts +system.physmem.perBankRdBursts::9 25698 # Per bank write bursts +system.physmem.perBankRdBursts::10 25929 # Per bank write bursts +system.physmem.perBankRdBursts::11 25525 # Per bank write bursts +system.physmem.perBankRdBursts::12 26076 # Per bank write bursts +system.physmem.perBankRdBursts::13 25420 # Per bank write bursts +system.physmem.perBankRdBursts::14 25099 # Per bank write bursts +system.physmem.perBankRdBursts::15 25608 # Per bank write bursts +system.physmem.perBankWrBursts::0 8587 # Per bank write bursts +system.physmem.perBankWrBursts::1 8090 # Per bank write bursts +system.physmem.perBankWrBursts::2 7940 # Per bank write bursts +system.physmem.perBankWrBursts::3 7436 # Per bank write bursts +system.physmem.perBankWrBursts::4 7275 # Per bank write bursts +system.physmem.perBankWrBursts::5 7415 # Per bank write bursts +system.physmem.perBankWrBursts::6 7544 # Per bank write bursts +system.physmem.perBankWrBursts::7 7156 # Per bank write bursts +system.physmem.perBankWrBursts::8 7532 # Per bank write bursts +system.physmem.perBankWrBursts::9 7639 # Per bank write bursts +system.physmem.perBankWrBursts::10 7820 # Per bank write bursts +system.physmem.perBankWrBursts::11 7739 # Per bank write bursts +system.physmem.perBankWrBursts::12 8260 # Per bank write bursts +system.physmem.perBankWrBursts::13 7848 # Per bank write bursts +system.physmem.perBankWrBursts::14 7518 # Per bank write bursts +system.physmem.perBankWrBursts::15 7790 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 24 # Number of times write queue was full causing retry -system.physmem.totGap 1906529083500 # Total gap between requests +system.physmem.numWrRetry 73 # Number of times write queue was full causing retry +system.physmem.totGap 1907545081500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410679 # Read request sizes (log2) +system.physmem.readPktSize::6 411070 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123513 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123616 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 316681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see @@ -159,130 +159,117 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64501 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 529.911784 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 323.379229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.310744 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14472 22.44% 22.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11319 17.55% 39.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5673 8.80% 48.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2735 4.24% 53.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2521 3.91% 56.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1561 2.42% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1592 2.47% 61.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1422 2.20% 64.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23206 35.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64501 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5582 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.544966 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2807.309852 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5579 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.308940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 323.701196 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.289256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14473 22.48% 22.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11513 17.88% 40.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5038 7.82% 48.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2819 4.38% 52.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2271 3.53% 56.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1853 2.88% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1969 3.06% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1608 2.50% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22844 35.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64388 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5502 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.686478 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2827.616380 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5499 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5582 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5582 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.123253 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.862531 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.587113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4829 86.51% 86.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 142 2.54% 89.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 15 0.27% 89.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 29 0.52% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 220 3.94% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.38% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.23% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 3 0.05% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.14% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.14% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.13% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 7 0.13% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 95.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 21 0.38% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.04% 95.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 16 0.29% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 179 3.21% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.04% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.04% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.09% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 6 0.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 13 0.23% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5582 # Writes before turning the bus around for reads -system.physmem.totQLat 4047296750 # Total ticks spent queuing -system.physmem.totMemAccLat 11745446750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9857.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5502 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5502 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.462559 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.761271 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.372868 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4982 90.55% 90.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 39 0.71% 91.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 171 3.11% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 6 0.11% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 13 0.24% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 3 0.05% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 6 0.11% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 29 0.53% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.11% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 149 2.71% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.15% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 12 0.22% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.04% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 11 0.20% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 6 0.11% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 14 0.25% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 8 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5502 # Writes before turning the bus around for reads +system.physmem.totQLat 8174654750 # Total ticks spent queuing +system.physmem.totMemAccLat 15879817250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2054710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19892.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28607.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 38642.48 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.79 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s @@ -290,78 +277,88 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.95 # Average write queue length when enqueuing -system.physmem.readRowHits 369870 # Number of row buffer hits during reads -system.physmem.writeRowHits 99689 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.71 # Row buffer hit rate for writes -system.physmem.avgGap 3568995.95 # Average gap between requests -system.physmem.pageHitRate 87.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245828520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134132625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1605310200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 401196240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 58054066515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1092995561250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1277961588390 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.306343 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1818124535500 # Time in different power states -system.physmem_0.memoryStateTime::REF 63663080000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24745773250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 241799040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 131934000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597120200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 399031920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57215830500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1093730864250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1277842072950 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.243651 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1819353589250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63663080000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23516733250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 16961800 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14485891 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 473040 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10754552 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4802971 # Number of BTB hits +system.physmem.avgRdQLen 2.34 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.44 # Average write queue length when enqueuing +system.physmem.readRowHits 370634 # Number of row buffer hits during reads +system.physmem.writeRowHits 99508 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes +system.physmem.avgGap 3567598.71 # Average gap between requests +system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229108320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121773960 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320732460 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3850104960.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4304249550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 244489440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8392475940 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4645539360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 448697608680 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 472278008880 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.583627 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1897458465500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 385946750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1635552000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1866968885000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 12097849250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8056520750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18404684750 # Time in different power states +system.physmem_1.actEnergy 230629140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122578500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1463307300 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 324402120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3763440720.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4252821870 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240122400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8356841250 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4387202880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 448891199505 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 472033988085 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.455703 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1897589722250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 380622500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1598754000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1867843123750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11424948500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7975953750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 18326036000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 16746871 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14324468 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 462281 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10727156 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4756454 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.659889 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 946597 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 35405 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5065158 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 501808 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4563350 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 210940 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.340308 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 926491 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 34071 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5119287 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 497756 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4621531 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 206577 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9542415 # DTB read hits -system.cpu0.dtb.read_misses 34570 # DTB read misses -system.cpu0.dtb.read_acv 614 # DTB read access violations -system.cpu0.dtb.read_accesses 570502 # DTB read accesses -system.cpu0.dtb.write_hits 5776455 # DTB write hits -system.cpu0.dtb.write_misses 8473 # DTB write misses -system.cpu0.dtb.write_acv 390 # DTB write access violations -system.cpu0.dtb.write_accesses 186760 # DTB write accesses -system.cpu0.dtb.data_hits 15318870 # DTB hits -system.cpu0.dtb.data_misses 43043 # DTB misses -system.cpu0.dtb.data_acv 1004 # DTB access violations -system.cpu0.dtb.data_accesses 757262 # DTB accesses -system.cpu0.itb.fetch_hits 1323023 # ITB hits -system.cpu0.itb.fetch_misses 7096 # ITB misses -system.cpu0.itb.fetch_acv 610 # ITB acv -system.cpu0.itb.fetch_accesses 1330119 # ITB accesses +system.cpu0.dtb.read_hits 9412979 # DTB read hits +system.cpu0.dtb.read_misses 34328 # DTB read misses +system.cpu0.dtb.read_acv 621 # DTB read access violations +system.cpu0.dtb.read_accesses 567042 # DTB read accesses +system.cpu0.dtb.write_hits 5709982 # DTB write hits +system.cpu0.dtb.write_misses 8326 # DTB write misses +system.cpu0.dtb.write_acv 453 # DTB write access violations +system.cpu0.dtb.write_accesses 184750 # DTB write accesses +system.cpu0.dtb.data_hits 15122961 # DTB hits +system.cpu0.dtb.data_misses 42654 # DTB misses +system.cpu0.dtb.data_acv 1074 # DTB access violations +system.cpu0.dtb.data_accesses 751792 # DTB accesses +system.cpu0.itb.fetch_hits 1307701 # ITB hits +system.cpu0.itb.fetch_misses 6903 # ITB misses +system.cpu0.itb.fetch_acv 605 # ITB acv +system.cpu0.itb.fetch_accesses 1314604 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -374,606 +371,604 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13007 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6504 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 284289977.091175 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 440390387.503353 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6503 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 12949 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6475 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 285376318.378378 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 440714536.369915 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6475 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 79500 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6504 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 57511518999 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849022011001 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 115029541 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6475 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 59737777000 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847811661500 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 119482029 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26105514 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 74391279 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16961800 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6251376 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 82220028 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1360432 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28534 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 140847 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 424678 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8564382 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 320281 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 109600123 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.678752 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.000671 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25760123 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 73391497 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16746871 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6180701 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 86881424 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1333696 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 31404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 137910 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 424032 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 391 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8451225 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 316387 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 113902133 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.644338 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.954525 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 95795479 87.40% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 897061 0.82% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1880834 1.72% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 785387 0.72% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2637004 2.41% 93.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 588358 0.54% 93.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 697546 0.64% 94.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 846325 0.77% 95.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5472129 4.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 100270966 88.03% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 886228 0.78% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1867927 1.64% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 772028 0.68% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2612142 2.29% 93.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 579506 0.51% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 682297 0.60% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 834861 0.73% 95.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5396178 4.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 109600123 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.147456 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.646715 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20981522 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 77286866 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8861450 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1818601 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 651683 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 621495 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 29133 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 64563390 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 88112 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 651683 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21851256 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 51776932 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17156942 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9742291 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8421017 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 62086646 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 197170 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2004328 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 218757 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4545100 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 41879351 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 74952395 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 74819888 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 123702 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34134806 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7744545 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1440211 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 234687 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12404512 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9945616 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6151141 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1474462 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 959878 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 54892526 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1879962 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 53219239 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 73531 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9606336 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4159079 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1308684 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 109600123 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.485576 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.229164 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 113902133 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.140162 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.614247 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20705856 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 82013409 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8738075 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1805880 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 638912 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 611998 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 28528 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 63750944 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 85334 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 638912 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21566893 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 55682864 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17571842 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9616135 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8825485 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 61313705 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 198555 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2000786 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 244905 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4945993 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 41348673 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 74029068 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 73897769 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 122571 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33810397 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7538276 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1420468 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 230583 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12282803 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9801073 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6065767 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1438850 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 936003 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 54214575 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1853218 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52616152 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 74253 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9353064 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4027640 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1289091 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 113902133 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.461942 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.202978 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 87964311 80.26% 80.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9240201 8.43% 88.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3866881 3.53% 92.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2775272 2.53% 94.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2892547 2.64% 97.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1421694 1.30% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 953270 0.87% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 366394 0.33% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 119553 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 92500805 81.21% 81.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9147500 8.03% 89.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3821730 3.36% 92.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2743420 2.41% 95.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2859412 2.51% 97.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1408857 1.24% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 945269 0.83% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 359735 0.32% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 115405 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 109600123 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 113902133 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 170160 16.71% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 520319 51.11% 67.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 327644 32.18% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 168885 16.84% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 512937 51.15% 67.99% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 321005 32.01% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36500931 68.59% 68.59% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56437 0.11% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25510 0.05% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9976302 18.75% 87.49% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5867670 11.03% 98.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 788585 1.48% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36110587 68.63% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 55774 0.11% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25398 0.05% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9844131 18.71% 87.50% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5797742 11.02% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 778716 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 53219239 # Type of FU issued -system.cpu0.iq.rate 0.462657 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1018124 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019131 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 216556534 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 66119650 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51474452 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 573722 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 277081 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260310 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53925009 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 309817 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 608784 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52616152 # Type of FU issued +system.cpu0.iq.rate 0.440369 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1002827 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019059 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 219643662 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65164078 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50897823 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 567855 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 274599 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 257683 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53309936 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 306506 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 606515 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1996070 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4265 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18313 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 688901 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1936563 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4258 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18275 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 663361 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18448 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 363376 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18355 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 359900 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 651683 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 48679015 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 759858 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 60350483 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 162315 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9945616 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6151141 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1664805 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40490 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 518912 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18313 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186521 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 513145 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 699666 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52530190 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9602772 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 689049 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 638912 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 52175649 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1047801 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 59607584 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 159494 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9801073 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6065767 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1641866 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39898 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 807337 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18275 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 179860 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 504304 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 684164 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51934418 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9472740 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 681734 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3577995 # number of nop insts executed -system.cpu0.iew.exec_refs 15404618 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8349417 # Number of branches executed -system.cpu0.iew.exec_stores 5801846 # Number of stores executed -system.cpu0.iew.exec_rate 0.456667 # Inst execution rate -system.cpu0.iew.wb_sent 51922146 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51734762 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26504573 # num instructions producing a value -system.cpu0.iew.wb_consumers 36648490 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.449752 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723211 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10116425 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 571278 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 623596 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 107842796 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.464314 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.394503 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3539791 # number of nop insts executed +system.cpu0.iew.exec_refs 15207952 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8258466 # Number of branches executed +system.cpu0.iew.exec_stores 5735212 # Number of stores executed +system.cpu0.iew.exec_rate 0.434663 # Inst execution rate +system.cpu0.iew.wb_sent 51337506 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51155506 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26224773 # num instructions producing a value +system.cpu0.iew.wb_consumers 36250862 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.428144 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723425 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9849450 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 564127 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 611071 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112190301 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.442089 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.364280 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 90117032 83.56% 83.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7061240 6.55% 90.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3809100 3.53% 93.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2021336 1.87% 95.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1578999 1.46% 96.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575276 0.53% 97.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 421394 0.39% 97.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 458654 0.43% 98.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1799765 1.67% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 94635636 84.35% 84.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6985533 6.23% 90.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3776917 3.37% 93.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2005568 1.79% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1565673 1.40% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 565948 0.50% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418764 0.37% 98.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 453132 0.40% 98.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1783130 1.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 107842796 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50072886 # Number of instructions committed -system.cpu0.commit.committedOps 50072886 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112190301 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49598051 # Number of instructions committed +system.cpu0.commit.committedOps 49598051 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13411786 # Number of memory references committed -system.cpu0.commit.loads 7949546 # Number of loads committed -system.cpu0.commit.membars 194670 # Number of memory barriers committed -system.cpu0.commit.branches 7579863 # Number of branches committed -system.cpu0.commit.fp_insts 251347 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46348996 # Number of committed integer instructions. -system.cpu0.commit.function_calls 640938 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2909270 5.81% 5.81% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32681197 65.27% 71.08% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55117 0.11% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 25038 0.05% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8144216 16.26% 87.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5468196 10.92% 98.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 788585 1.57% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13266916 # Number of memory references committed +system.cpu0.commit.loads 7864510 # Number of loads committed +system.cpu0.commit.membars 192309 # Number of memory barriers committed +system.cpu0.commit.branches 7509354 # Number of branches committed +system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45907115 # Number of committed integer instructions. +system.cpu0.commit.function_calls 632192 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2885858 5.82% 5.82% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32387672 65.30% 71.12% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54445 0.11% 71.23% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8056819 16.24% 87.53% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5408346 10.90% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 778715 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 50072886 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1799765 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166055766 # The number of ROB reads -system.cpu0.rob.rob_writes 122136916 # The number of ROB writes -system.cpu0.timesIdled 488999 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5429418 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3697477415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47166151 # Number of Instructions Simulated -system.cpu0.committedOps 47166151 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.438816 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.438816 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.410035 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.410035 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68768616 # number of integer regfile reads -system.cpu0.int_regfile_writes 37693548 # number of integer regfile writes -system.cpu0.fp_regfile_reads 122704 # number of floating regfile reads -system.cpu0.fp_regfile_writes 131478 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1676808 # number of misc regfile reads -system.cpu0.misc_regfile_writes 792469 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1260860 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.428743 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10814422 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1261290 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.574096 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.428743 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989119 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.989119 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 57625075 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 57625075 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6881291 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6881291 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3568585 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3568585 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177059 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 177059 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 182551 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 182551 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10449876 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10449876 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10449876 # number of overall hits -system.cpu0.dcache.overall_hits::total 10449876 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1562512 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1562512 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1693924 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1693924 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20209 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20209 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2828 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2828 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3256436 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3256436 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3256436 # number of overall misses -system.cpu0.dcache.overall_misses::total 3256436 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38980676000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 38980676000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74553561151 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 74553561151 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 291267500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 291267500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 15945500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 15945500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 113534237151 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 113534237151 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 113534237151 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 113534237151 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8443803 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8443803 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5262509 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5262509 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 197268 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 197268 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 185379 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 185379 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13706312 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13706312 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13706312 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13706312 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.185048 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.185048 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.321885 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.321885 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102444 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102444 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015255 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015255 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.237587 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.237587 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.237587 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.237587 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24947.441044 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24947.441044 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44012.341257 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44012.341257 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14412.761641 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14412.761641 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5638.437058 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5638.437058 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34864.568857 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34864.568857 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4192146 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2471 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 109181 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.396296 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 29.771084 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 743371 # number of writebacks -system.cpu0.dcache.writebacks::total 743371 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 555767 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 555767 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1440437 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1440437 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1996204 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1996204 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1996204 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1996204 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1006745 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1006745 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253487 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 253487 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14749 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14749 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2828 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2828 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1260232 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1260232 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1260232 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1260232 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7013 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7013 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10003 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10003 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17016 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17016 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29619600000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29619600000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11703772725 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11703772725 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170858500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170858500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 13117500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 13117500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41323372725 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 41323372725 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41323372725 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 41323372725 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563340000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563340000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1563340000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1563340000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119229 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119229 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048168 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048168 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074766 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074766 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015255 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015255 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.091945 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.091945 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29421.154314 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29421.154314 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46171.096447 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46171.096447 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11584.412503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11584.412503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4638.437058 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4638.437058 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222920.290888 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222920.290888 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91874.706159 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91874.706159 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 908505 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.512047 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7601055 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 909016 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.361850 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28452405500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.512047 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995141 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995141 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 49598051 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1783130 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 169680194 # The number of ROB reads +system.cpu0.rob.rob_writes 120607262 # The number of ROB writes +system.cpu0.timesIdled 481372 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5579896 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3694980588 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46714728 # Number of Instructions Simulated +system.cpu0.committedOps 46714728 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.557695 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.557695 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.390977 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.390977 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68002622 # number of integer regfile reads +system.cpu0.int_regfile_writes 37262146 # number of integer regfile writes +system.cpu0.fp_regfile_reads 121389 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130195 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1657828 # number of misc regfile reads +system.cpu0.misc_regfile_writes 782201 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1253317 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.016530 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10648438 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1253753 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.493250 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.016530 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988314 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988314 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 436 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 414 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.851562 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 56881554 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56881554 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6768789 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6768789 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3521179 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3521179 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174329 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174329 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179913 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 179913 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10289968 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10289968 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10289968 # number of overall hits +system.cpu0.dcache.overall_hits::total 10289968 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1553170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1553170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1684058 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1684058 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20354 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20354 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3039 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3039 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3237228 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3237228 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3237228 # number of overall misses +system.cpu0.dcache.overall_misses::total 3237228 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41477053500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41477053500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85173031211 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 85173031211 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394024000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 394024000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17098500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 17098500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 126650084711 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 126650084711 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 126650084711 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 126650084711 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8321959 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8321959 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205237 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5205237 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194683 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 194683 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182952 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182952 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13527196 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13527196 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13527196 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13527196 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186635 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.186635 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323531 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323531 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104549 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104549 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016611 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016611 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239313 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.239313 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239313 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.239313 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26704.773785 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26704.773785 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50576.067577 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50576.067577 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19358.553601 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19358.553601 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.357354 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.357354 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39123.004222 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39123.004222 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4484825 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 6096 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 108156 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 130 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.466262 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 46.892308 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 737739 # number of writebacks +system.cpu0.dcache.writebacks::total 737739 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 551343 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 551343 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432280 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1432280 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5686 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5686 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983623 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1983623 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983623 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1983623 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001827 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1556905500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1556905500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1556905500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048370 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048370 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075343 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075343 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016611 # 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average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11646.986638 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.357354 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.357354 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223148.272897 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223148.272897 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4250134 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3659200 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 108723 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2354380 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 849662 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 894430 # number of writebacks +system.cpu0.icache.writebacks::total 894430 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53904 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 53904 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 53904 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 53904 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 53904 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 53904 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895236 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 895236 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 895236 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 895236 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 895236 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 895236 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12277660991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12277660991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12277660991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12277660991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12277660991 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12277660991 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105930 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105930 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105930 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13714.440651 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency +system.cpu1.branchPred.lookups 4438770 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3818546 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 113828 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2325021 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 880835 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.088567 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 217108 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8204 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1308734 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 157441 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1151293 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 37897 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 37.885034 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 228893 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8586 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1265295 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 163281 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1102014 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 40695 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2331871 # DTB read hits -system.cpu1.dtb.read_misses 15400 # DTB read misses -system.cpu1.dtb.read_acv 73 # DTB read access violations -system.cpu1.dtb.read_accesses 429786 # DTB read accesses -system.cpu1.dtb.write_hits 1381774 # DTB write hits -system.cpu1.dtb.write_misses 3743 # DTB write misses -system.cpu1.dtb.write_acv 71 # DTB write access violations -system.cpu1.dtb.write_accesses 161427 # DTB write accesses -system.cpu1.dtb.data_hits 3713645 # DTB hits -system.cpu1.dtb.data_misses 19143 # DTB misses -system.cpu1.dtb.data_acv 144 # DTB access violations -system.cpu1.dtb.data_accesses 591213 # DTB accesses -system.cpu1.itb.fetch_hits 662529 # ITB hits -system.cpu1.itb.fetch_misses 3380 # ITB misses -system.cpu1.itb.fetch_acv 133 # ITB acv -system.cpu1.itb.fetch_accesses 665909 # ITB accesses +system.cpu1.dtb.read_hits 2431495 # DTB read hits +system.cpu1.dtb.read_misses 15697 # DTB read misses +system.cpu1.dtb.read_acv 126 # DTB read access violations +system.cpu1.dtb.read_accesses 432376 # DTB read accesses +system.cpu1.dtb.write_hits 1439190 # DTB write hits +system.cpu1.dtb.write_misses 3913 # DTB write misses +system.cpu1.dtb.write_acv 68 # DTB write access violations +system.cpu1.dtb.write_accesses 163232 # DTB write accesses +system.cpu1.dtb.data_hits 3870685 # DTB hits +system.cpu1.dtb.data_misses 19610 # DTB misses +system.cpu1.dtb.data_acv 194 # DTB access violations +system.cpu1.dtb.data_accesses 595608 # DTB accesses +system.cpu1.itb.fetch_hits 677547 # ITB hits +system.cpu1.itb.fetch_misses 3477 # ITB misses +system.cpu1.itb.fetch_acv 144 # ITB acv +system.cpu1.itb.fetch_accesses 681024 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -986,572 +981,572 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 4980 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2490 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 762354971.285141 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 386526411.344669 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2490 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 5082 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2541 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 747256549.980323 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 396382548.008070 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2541 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 975501000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2490 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 8269651500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898263878500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 16541794 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2541 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 8770545000 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898778893500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 17543632 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6749073 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 16895090 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4250134 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1224211 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 8698208 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 363130 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26231 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65753 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47571 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1900929 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 80768 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15768440 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.071450 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.476995 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7091057 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17620667 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4438770 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1273009 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9220507 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 378986 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 68380 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 52547 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1980567 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84330 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 16648116 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.058418 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.465473 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12797159 81.16% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 186632 1.18% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 321640 2.04% 84.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 225512 1.43% 85.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 384419 2.44% 88.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 144313 0.92% 89.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 169042 1.07% 90.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 202635 1.29% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1337088 8.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 13552832 81.41% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 195919 1.18% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 328483 1.97% 84.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 235159 1.41% 85.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 403136 2.42% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 149696 0.90% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 175199 1.05% 90.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 211449 1.27% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1396243 8.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15768440 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.256933 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.021358 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5523877 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7693314 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2103455 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 273251 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 174542 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 146034 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7171 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 13792543 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22640 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 174542 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5705734 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 782365 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5725411 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2195690 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1184696 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13060888 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4153 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 107025 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 30497 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 586772 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 8670673 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 15585724 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 15521516 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 57730 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6788049 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1882616 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 491915 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 50500 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2201368 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2434805 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1482534 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 303562 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 164759 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11452007 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 560044 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10991859 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27120 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2468765 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1174488 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 414117 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15768440 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.697080 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.421678 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 16648116 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.253013 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.004391 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5799032 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8189176 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2194913 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 283013 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 181981 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 153262 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7666 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14395116 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 24052 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 181981 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5988192 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 920488 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6008083 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2289928 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1259442 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13629732 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4042 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 109065 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 36629 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 635484 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9050413 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16252880 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16186853 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59441 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7085651 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1964754 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 511413 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 53676 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2285701 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2541438 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1543271 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 322798 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 171550 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11950332 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 586300 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11472464 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27528 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2575040 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1218372 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 432674 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 16648116 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.689115 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.415855 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11265469 71.44% 71.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1937394 12.29% 83.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 827410 5.25% 88.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 596936 3.79% 92.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 547934 3.47% 96.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 289502 1.84% 98.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 188780 1.20% 99.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 83209 0.53% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 31806 0.20% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11949949 71.78% 71.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2021085 12.14% 83.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 863131 5.18% 89.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 621327 3.73% 92.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 572760 3.44% 96.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 302852 1.82% 98.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 196760 1.18% 99.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 86740 0.52% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 33512 0.20% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15768440 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 16648116 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32091 10.27% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 173932 55.66% 65.93% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 106485 34.07% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 33628 10.30% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 182347 55.85% 66.15% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 110540 33.85% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6803980 61.90% 61.94% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16523 0.15% 62.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 13867 0.13% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2450394 22.29% 84.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1410696 12.83% 97.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 289273 2.63% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7109835 61.97% 62.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17232 0.15% 62.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2555661 22.28% 84.58% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1468866 12.80% 97.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 299742 2.61% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10991859 # Type of FU issued -system.cpu1.iq.rate 0.664490 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 312508 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028431 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 37874505 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 14381418 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10489971 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 217280 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 104295 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 101356 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11183979 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 115637 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 113432 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11472464 # Type of FU issued +system.cpu1.iq.rate 0.653939 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 326515 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028461 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 39721820 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15008897 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10951678 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 225266 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 107813 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 104885 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11674098 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120130 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 118360 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 527848 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1066 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 5067 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 174171 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 553503 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1124 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 5247 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 178223 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 475 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 99025 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 530 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 100466 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 174542 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 497039 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 226226 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 12632900 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 57966 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2434805 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1482534 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 508876 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6584 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 218362 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 5067 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 44763 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 141821 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 186584 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10809707 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2356029 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 182151 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 181981 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 560519 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 287887 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13187033 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 58459 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2541438 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1543271 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 532420 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6842 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 279702 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 5247 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 45694 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 148663 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 194357 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11283035 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2456415 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 189428 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 620849 # number of nop insts executed -system.cpu1.iew.exec_refs 3747857 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1612675 # Number of branches executed -system.cpu1.iew.exec_stores 1391828 # Number of stores executed -system.cpu1.iew.exec_rate 0.653479 # Inst execution rate -system.cpu1.iew.wb_sent 10644010 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 10591327 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5073681 # num instructions producing a value -system.cpu1.iew.wb_consumers 7144079 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.640277 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710194 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2479122 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 145927 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 162123 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 15327061 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.652859 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.628724 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 650401 # number of nop insts executed +system.cpu1.iew.exec_refs 3906085 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1687752 # Number of branches executed +system.cpu1.iew.exec_stores 1449670 # Number of stores executed +system.cpu1.iew.exec_rate 0.643141 # Inst execution rate +system.cpu1.iew.wb_sent 11111703 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11056563 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5287384 # num instructions producing a value +system.cpu1.iew.wb_consumers 7447136 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.630232 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709989 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2591726 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 153626 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 169211 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16186649 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.645421 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.620431 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11704556 76.37% 76.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1675096 10.93% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 596024 3.89% 91.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 370132 2.41% 93.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 281840 1.84% 95.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 119415 0.78% 96.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 109784 0.72% 96.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 115974 0.76% 97.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 354240 2.31% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12404611 76.63% 76.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1746252 10.79% 87.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 623750 3.85% 91.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 386653 2.39% 93.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 297145 1.84% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 125489 0.78% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 112472 0.69% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119580 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 370697 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 15327061 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10006417 # Number of instructions committed -system.cpu1.commit.committedOps 10006417 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16186649 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10447204 # Number of instructions committed +system.cpu1.commit.committedOps 10447204 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3215320 # Number of memory references committed -system.cpu1.commit.loads 1906957 # Number of loads committed -system.cpu1.commit.membars 46297 # Number of memory barriers committed -system.cpu1.commit.branches 1432968 # Number of branches committed -system.cpu1.commit.fp_insts 99355 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9296453 # Number of committed integer instructions. -system.cpu1.commit.function_calls 155642 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 467886 4.68% 4.68% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5954632 59.51% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16225 0.16% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13860 0.14% 64.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1953254 19.52% 84.03% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1308912 13.08% 97.11% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 289273 2.89% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3352983 # Number of memory references committed +system.cpu1.commit.loads 1987935 # Number of loads committed +system.cpu1.commit.membars 48912 # Number of memory barriers committed +system.cpu1.commit.branches 1499265 # Number of branches committed +system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9704534 # Number of committed integer instructions. +system.cpu1.commit.function_calls 163857 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 490367 4.69% 4.69% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6221313 59.55% 64.24% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16935 0.16% 64.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 2036847 19.50% 84.06% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1365632 13.07% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 299742 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 10006417 # Class of committed instruction -system.cpu1.commit.bw_lim_events 354240 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 27350454 # The number of ROB reads -system.cpu1.rob.rob_writes 25410376 # The number of ROB writes -system.cpu1.timesIdled 127916 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 773354 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3796525267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9543281 # Number of Instructions Simulated -system.cpu1.committedOps 9543281 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.733345 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.733345 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.576919 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.576919 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13915898 # number of integer regfile reads -system.cpu1.int_regfile_writes 7574327 # number of integer regfile writes -system.cpu1.fp_regfile_reads 57027 # number of floating regfile reads -system.cpu1.fp_regfile_writes 56084 # number of floating regfile writes -system.cpu1.misc_regfile_reads 548336 # number of misc regfile reads -system.cpu1.misc_regfile_writes 233992 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 125899 # number of replacements -system.cpu1.dcache.tags.tagsinuse 488.643443 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2930828 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 126411 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.184913 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 47496090500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.643443 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954382 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.954382 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 10447204 # Class of committed instruction +system.cpu1.commit.bw_lim_events 370697 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 28744557 # The number of ROB reads +system.cpu1.rob.rob_writes 26537349 # The number of ROB writes +system.cpu1.timesIdled 134728 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 895516 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3797555246 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9961587 # Number of Instructions Simulated +system.cpu1.committedOps 9961587 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.761128 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.761128 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.567818 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.567818 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 14521823 # number of integer regfile reads +system.cpu1.int_regfile_writes 7909607 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58779 # number of floating regfile reads +system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes +system.cpu1.misc_regfile_reads 571518 # number of misc regfile reads +system.cpu1.misc_regfile_writes 244969 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 130966 # number of replacements +system.cpu1.dcache.tags.tagsinuse 487.964655 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3061418 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 131478 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.284641 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 49531315500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.964655 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.953056 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.953056 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 13906652 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 13906652 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1865609 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1865609 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 981966 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 981966 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 38120 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 38120 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 34857 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 34857 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2847575 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2847575 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2847575 # number of overall hits -system.cpu1.dcache.overall_hits::total 2847575 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 231819 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 231819 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 282423 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 282423 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5078 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5078 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2912 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2912 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 514242 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 514242 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 514242 # number of overall misses -system.cpu1.dcache.overall_misses::total 514242 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3027811000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3027811000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10676531998 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10676531998 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51207500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 51207500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 16199500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 16199500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13704342998 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13704342998 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13704342998 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13704342998 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2097428 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2097428 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1264389 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1264389 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 43198 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 43198 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 37769 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 37769 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3361817 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3361817 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3361817 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3361817 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110525 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.110525 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223367 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.223367 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117552 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117552 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.077100 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.077100 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152965 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.152965 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152965 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.152965 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13061.099392 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13061.099392 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37803.337540 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37803.337540 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10084.186688 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10084.186688 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5563.015110 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5563.015110 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26649.598823 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 26649.598823 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 625764 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 300 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 24254 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.800445 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 15.789474 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 81179 # number of writebacks -system.cpu1.dcache.writebacks::total 81179 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 142547 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 142547 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 235954 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 235954 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 779 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 779 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 378501 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 378501 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 378501 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 378501 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 89272 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 89272 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 46469 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 46469 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4299 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4299 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2912 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2912 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 135741 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 135741 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 135741 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 135741 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 182 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 182 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3016 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3016 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3198 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3198 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1142608000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1142608000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1700967690 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1700967690 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38610000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38610000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 13287500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 13287500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2843575690 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2843575690 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2843575690 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2843575690 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 35749500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 35749500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 35749500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 35749500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042563 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042563 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036752 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036752 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.099518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.077100 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.077100 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040377 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040377 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12799.175553 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12799.175553 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36604.353225 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36604.353225 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8981.158409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8981.158409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4563.015110 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4563.015110 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196425.824176 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196425.824176 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11178.705441 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11178.705441 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 243897 # number of replacements -system.cpu1.icache.tags.tagsinuse 471.203096 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1645008 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 244406 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.730637 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1879506005500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.203096 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920319 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.920319 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2145410 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2145410 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1645008 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1645008 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1645008 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1645008 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1645008 # number of overall hits -system.cpu1.icache.overall_hits::total 1645008 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 255921 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 255921 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 255921 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 255921 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 255921 # number of overall misses -system.cpu1.icache.overall_misses::total 255921 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3476894499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3476894499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3476894499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3476894499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3476894499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3476894499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1900929 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1900929 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1900929 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1900929 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1900929 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1900929 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.134629 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.134629 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.134629 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.134629 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.134629 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.134629 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13585.811633 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13585.811633 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13585.811633 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13585.811633 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 470 # number of cycles access was blocked +system.cpu1.dcache.tags.tag_accesses 14512669 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14512669 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1946433 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1946433 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1026063 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1026063 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40785 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40785 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37242 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 37242 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2972496 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2972496 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2972496 # number of overall hits +system.cpu1.dcache.overall_hits::total 2972496 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 241711 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 241711 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 292248 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 292248 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5308 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5308 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3094 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3094 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 533959 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 533959 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 533959 # number of overall misses +system.cpu1.dcache.overall_misses::total 533959 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3394927000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3394927000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12114051455 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12114051455 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54394000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 54394000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17165000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 17165000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15508978455 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15508978455 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15508978455 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15508978455 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2188144 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2188144 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318311 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1318311 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46093 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46093 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40336 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 40336 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3506455 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3506455 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3506455 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3506455 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110464 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.110464 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221684 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.221684 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115158 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115158 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076706 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076706 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152279 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.152279 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152279 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.152279 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14045.397189 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14045.397189 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41451.272395 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41451.272395 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10247.550867 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10247.550867 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5547.834518 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5547.834518 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29045.260881 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29045.260881 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 715753 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 884 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24925 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.716269 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 84601 # number of writebacks +system.cpu1.dcache.writebacks::total 84601 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148639 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 148639 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243827 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 243827 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 846 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 846 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 392466 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 392466 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 392466 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 392466 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93072 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 93072 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48421 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 48421 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4462 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4462 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3093 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3093 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 141493 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 141493 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 141493 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 141493 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3153 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3371 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262526500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262526500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1947214752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1947214752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40086500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40086500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14072000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14072000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3209741252 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3209741252 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3209741252 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3209741252 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41866500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41866500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41866500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41866500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042535 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042535 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096804 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096804 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076681 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076681 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040352 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040352 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13565.051788 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13565.051788 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40214.261416 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40214.261416 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8983.975796 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8983.975796 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.628193 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.628193 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192048.165138 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192048.165138 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12419.608425 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12419.608425 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 256896 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.782709 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1710963 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 257408 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.646891 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1882016787500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.782709 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919497 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919497 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 2238053 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2238053 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1710963 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1710963 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1710963 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1710963 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1710963 # number of overall hits +system.cpu1.icache.overall_hits::total 1710963 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 269604 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 269604 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 269604 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 269604 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 269604 # number of overall misses +system.cpu1.icache.overall_misses::total 269604 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3754413998 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3754413998 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3754413998 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3754413998 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3754413998 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3754413998 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1980567 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1980567 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1980567 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1980567 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1980567 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1980567 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136125 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.136125 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136125 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.136125 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136125 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.136125 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13925.661333 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13925.661333 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13925.661333 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13925.661333 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 473 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.368421 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.261905 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 243897 # number of writebacks -system.cpu1.icache.writebacks::total 243897 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11440 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 11440 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 11440 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 11440 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 11440 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 11440 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244481 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 244481 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 244481 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 244481 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 244481 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 244481 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3131245499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3131245499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3131245499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3131245499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3131245499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3131245499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.128611 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.128611 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.128611 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12807.725341 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 256896 # number of writebacks +system.cpu1.icache.writebacks::total 256896 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12118 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12118 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12118 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12118 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12118 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12118 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257486 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 257486 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 257486 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 257486 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 257486 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 257486 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3368066498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3368066498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3368066498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3368066498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3368066498 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3368066498 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.130006 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.130006 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.130006 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13080.581072 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1564,12 +1559,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7374 # Transaction distribution system.iobus.trans_dist::ReadResp 7374 # Transaction distribution -system.iobus.trans_dist::WriteReq 54571 # Transaction distribution -system.iobus.trans_dist::WriteResp 54571 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11828 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54611 # Transaction distribution +system.iobus.trans_dist::WriteResp 54611 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11908 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1578,11 +1573,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40508 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123890 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1591,50 +1586,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 73858 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735194 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12271500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735514 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12353502 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 824500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14105000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13988000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6057000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6060500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216200796 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216282007 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27409000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.499134 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.490946 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712299837000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.499134 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031196 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031196 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714262123000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.490946 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030684 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030684 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375579 # Number of tag accesses system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1643,14 +1638,14 @@ system.iocache.demand_misses::tsunami.ide 41731 # n system.iocache.demand_misses::total 41731 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22562883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22562883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858746913 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4858746913 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4881309796 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4881309796 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4881309796 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4881309796 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22774383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22774383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4918988624 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4918988624 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4941763007 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4941763007 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4941763007 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4941763007 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1667,19 +1662,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126049.625698 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126049.625698 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116931.722011 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116931.722011 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116970.832139 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116970.832139 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127231.189944 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 127231.189944 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118381.512899 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118381.512899 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118419.472502 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118419.472502 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1165 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 145.625000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks @@ -1691,14 +1686,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41731 system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13612883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13612883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778734565 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2778734565 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2792347448 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2792347448 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2792347448 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2792347448 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13824383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13824383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2838948426 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2838948426 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2852772809 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2852772809 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2852772809 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2852772809 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1707,200 +1702,200 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76049.625698 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76049.625698 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66873.665889 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66873.665889 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66913.025041 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66913.025041 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66913.025041 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66913.025041 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 345621 # number of replacements -system.l2c.tags.tagsinuse 65429.949099 # Cycle average of tags in use -system.l2c.tags.total_refs 4347999 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411104 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.576397 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 5987439000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 292.894251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5335.962916 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58874.943819 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 203.860157 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 722.287955 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004469 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081420 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.898360 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003111 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011021 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998382 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65483 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1723 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1817 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5637 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56151 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999191 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38487323 # Number of tag accesses -system.l2c.tags.data_accesses 38487323 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 824550 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 824550 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 880861 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 880861 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 2842 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1401 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4243 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 470 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 444 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 914 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 147625 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 30184 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 177809 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 895088 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 243149 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1138237 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 727494 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 80955 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 808449 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 895088 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 875119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 243149 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 111139 # number of demand (read+write) hits -system.l2c.demand_hits::total 2124495 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 895088 # number of overall hits -system.l2c.overall_hits::cpu0.data 875119 # number of overall hits -system.l2c.overall_hits::cpu1.inst 243149 # number of overall hits -system.l2c.overall_hits::cpu1.data 111139 # number of overall hits -system.l2c.overall_hits::total 2124495 # number of overall hits +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77231.189944 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 77231.189944 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68322.786533 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68322.786533 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 345941 # number of replacements +system.l2c.tags.tagsinuse 65423.095027 # Cycle average of tags in use +system.l2c.tags.total_refs 4335515 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 411463 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.536828 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6416575000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 293.307825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5315.079150 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58827.069962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 210.319847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 777.318243 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004476 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081102 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.897630 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003209 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011861 # 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mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.272862 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019084 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253523 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.162131 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.162131 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19166.666667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 36888.888889 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002091 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003336 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.002518 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002137 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001032 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428804 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280399 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.407420 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013272 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273999 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022834 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254011 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162523 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162523 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45333.333333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19100 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 33409.090909 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79104.848165 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104314.292075 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 81439.691219 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74350.916230 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63857.855060 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84805.714286 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63978.016615 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210417.938115 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183925.824176 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209747.810980 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86721.967560 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10467.323327 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74657.935094 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 850516 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 398567 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 435 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93561.900643 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 115771.239121 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 95764.396687 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90231.858002 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71490.593495 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107172.606925 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71745.854000 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210644.188046 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179548.165138 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209702.015288 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87049.961500 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11611.242955 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74494.223363 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 852108 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 399805 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 437 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 297176 # Transaction distribution -system.membus.trans_dist::WriteReq 13019 # Transaction distribution -system.membus.trans_dist::WriteResp 13019 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123513 # Transaction distribution -system.membus.trans_dist::CleanEvict 262911 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6111 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4826 # Transaction distribution +system.membus.trans_dist::ReadResp 297167 # Transaction distribution +system.membus.trans_dist::WriteReq 13059 # Transaction distribution +system.membus.trans_dist::WriteResp 13059 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123616 # Transaction distribution +system.membus.trans_dist::CleanEvict 263125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6609 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5164 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121549 # Transaction distribution -system.membus.trans_dist::ReadExResp 121146 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290030 # Transaction distribution -system.membus.trans_dist::BadAddressError 49 # Transaction distribution +system.membus.trans_dist::ReadExReq 121953 # Transaction distribution +system.membus.trans_dist::ReadExResp 121548 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 290016 # Transaction distribution +system.membus.trans_dist::BadAddressError 44 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40428 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1177677 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 98 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1218203 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40508 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 88 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1220212 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1301648 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73538 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31530048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31603586 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1303657 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73858 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31561664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31635522 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34261826 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 11676 # Total snoops (count) -system.membus.snoopTraffic 28672 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 484282 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001355 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036780 # Request fanout histogram +system.membus.pkt_size::total 34293762 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 12507 # Total snoops (count) +system.membus.snoopTraffic 28800 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 485548 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001427 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037752 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 483626 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 656 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 484855 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 693 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 484282 # Request fanout histogram -system.membus.reqLayer0.occupancy 36370000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 485548 # Request fanout histogram +system.membus.reqLayer0.occupancy 36350498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1352579532 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1353965073 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 62000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2178718000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2179761000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 960113 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 960863 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5113699 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2556514 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 337557 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1071 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5108724 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2554049 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 343728 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2265500 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13019 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13019 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 906543 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1152402 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825837 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10249 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5740 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15989 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 300358 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 300358 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1153745 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1104612 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 49 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 203 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2726862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3834313 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 401077 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7695072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116326272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128153608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31253696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13151546 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288885122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 379909 # Total snoops (count) -system.toL2Bus.snoopTraffic 6725760 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2940742 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.121053 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.326514 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2263429 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13059 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13059 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 904436 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1151326 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 825788 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10854 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6132 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16986 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 300014 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 300014 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1152722 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1103559 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 44 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 238 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2684715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3812301 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771824 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417816 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7686656 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114526656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127297140 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32917632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13697806 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288439234 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382362 # Total snoops (count) +system.toL2Bus.snoopTraffic 6813696 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2939714 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.123574 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.329478 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2585068 87.91% 87.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 355364 12.08% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 309 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2576793 87.65% 87.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 362587 12.33% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 316 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 18 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2940742 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4550461413 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2939714 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4544765338 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1365446887 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1344393906 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1921756875 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1911305093 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 368286347 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 387758410 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 208891088 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 217734513 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2184,194 +2179,194 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6504 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 179089 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 63660 40.34% 40.34% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.42% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.22% 41.64% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 175 0.11% 41.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 91921 58.25% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 157813 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 62631 49.19% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.51% 50.81% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 175 0.14% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 62456 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 127319 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863112245000 97.74% 97.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 65536000 0.00% 97.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 577434000 0.03% 97.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 84972500 0.00% 97.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42413276000 2.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1906253463500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983836 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6475 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 176726 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 62785 40.28% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.23% 41.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 90860 58.29% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 155882 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 61770 49.18% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.53% 50.82% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 61589 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862335551000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64321000 0.00% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 576343500 0.03% 97.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 87551500 0.00% 97.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 44167527000 2.32% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907231294000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983834 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679453 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.806771 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed -system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed -system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed -system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed -system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed -system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed -system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed -system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed -system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed -system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed -system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed -system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed -system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 178 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.677845 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.805712 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 4.14% 4.14% # number of syscalls executed +system.cpu0.kern.syscall::3 14 8.28% 12.43% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.37% 14.79% # number of syscalls executed +system.cpu0.kern.syscall::6 26 15.38% 30.18% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.59% 30.77% # number of syscalls executed +system.cpu0.kern.syscall::17 5 2.96% 33.73% # number of syscalls executed +system.cpu0.kern.syscall::19 7 4.14% 37.87% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.37% 40.24% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.59% 40.83% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.78% 42.60% # number of syscalls executed +system.cpu0.kern.syscall::33 5 2.96% 45.56% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.18% 46.75% # number of syscalls executed +system.cpu0.kern.syscall::45 26 15.38% 62.13% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.78% 63.91% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.73% 68.64% # number of syscalls executed +system.cpu0.kern.syscall::54 8 4.73% 73.37% # number of syscalls executed +system.cpu0.kern.syscall::59 6 3.55% 76.92% # number of syscalls executed +system.cpu0.kern.syscall::71 15 8.88% 85.80% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.78% 87.57% # number of syscalls executed +system.cpu0.kern.syscall::74 3 1.78% 89.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.59% 89.94% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.18% 91.12% # number of syscalls executed +system.cpu0.kern.syscall::92 7 4.14% 95.27% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.18% 96.45% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.18% 97.63% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.59% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.59% 98.82% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.18% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 169 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 278 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3399 2.05% 2.22% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.25% # number of callpals executed +system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151231 91.28% 93.54% # number of callpals executed -system.cpu0.kern.callpal::rdps 5900 3.56% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::swpipl 149333 91.35% 93.61% # number of callpals executed +system.cpu0.kern.callpal::rdps 5683 3.48% 97.09% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed +system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed -system.cpu0.kern.callpal::rti 4349 2.63% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 315 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rti 4311 2.64% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 165676 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6738 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches +system.cpu0.kern.callpal::total 163475 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6664 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1097 -system.cpu0.kern.mode_good::user 1097 +system.cpu0.kern.mode_good::kernel 1070 +system.cpu0.kern.mode_good::user 1070 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.162808 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.160564 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280026 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1904214078500 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1672761500 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.276700 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1905216688000 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1682440000 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3400 # number of times the context was actually changed +system.cpu0.kern.swap_context 3350 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2490 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 60423 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18641 37.27% 37.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 3.85% 41.12% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 278 0.56% 41.67% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 29176 58.33% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 50020 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 18293 47.50% 47.50% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.00% 52.50% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 278 0.72% 53.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18016 46.78% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 38512 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1873859043000 98.29% 98.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 564907000 0.03% 98.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 133677500 0.01% 98.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31975089500 1.68% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1906532717000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981331 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2541 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 62895 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 19560 37.60% 37.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.70% 41.30% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 30244 58.14% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 52021 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 19198 47.61% 47.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 4.77% 52.38% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18906 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 40321 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872948111000 98.19% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 564456500 0.03% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 141435000 0.01% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33894599000 1.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907548601500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981493 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.617494 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769932 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed -system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed -system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed -system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed -system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed -system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed -system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed -system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed -system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed -system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 148 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.625116 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.775091 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.64% 0.64% # number of syscalls executed +system.cpu1.kern.syscall::3 16 10.19% 10.83% # number of syscalls executed +system.cpu1.kern.syscall::6 16 10.19% 21.02% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.64% 21.66% # number of syscalls executed +system.cpu1.kern.syscall::17 10 6.37% 28.03% # number of syscalls executed +system.cpu1.kern.syscall::19 3 1.91% 29.94% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.27% 31.21% # number of syscalls executed +system.cpu1.kern.syscall::23 3 1.91% 33.12% # number of syscalls executed +system.cpu1.kern.syscall::24 3 1.91% 35.03% # number of syscalls executed +system.cpu1.kern.syscall::33 6 3.82% 38.85% # number of syscalls executed +system.cpu1.kern.syscall::45 28 17.83% 56.69% # number of syscalls executed +system.cpu1.kern.syscall::47 3 1.91% 58.60% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.27% 59.87% # number of syscalls executed +system.cpu1.kern.syscall::54 2 1.27% 61.15% # number of syscalls executed +system.cpu1.kern.syscall::58 1 0.64% 61.78% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.64% 62.42% # number of syscalls executed +system.cpu1.kern.syscall::71 39 24.84% 87.26% # number of syscalls executed +system.cpu1.kern.syscall::74 13 8.28% 95.54% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.64% 96.18% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.27% 97.45% # number of syscalls executed +system.cpu1.kern.syscall::132 3 1.91% 99.36% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.64% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 157 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 175 0.33% 0.34% # number of callpals executed +system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1166 2.23% 2.57% # number of callpals executed -system.cpu1.kern.callpal::tbi 5 0.01% 2.58% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.59% # number of callpals executed -system.cpu1.kern.callpal::swpipl 44628 85.35% 87.94% # number of callpals executed -system.cpu1.kern.callpal::rdps 2858 5.47% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.42% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed -system.cpu1.kern.callpal::rti 3189 6.10% 99.52% # number of callpals executed -system.cpu1.kern.callpal::callsys 200 0.38% 99.91% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed +system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed +system.cpu1.kern.callpal::swpipl 46558 85.31% 87.92% # number of callpals executed +system.cpu1.kern.callpal::rdps 3077 5.64% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed +system.cpu1.kern.callpal::wrusp 6 0.01% 93.57% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed +system.cpu1.kern.callpal::rti 3246 5.95% 99.52% # number of callpals executed +system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 52290 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1624 # number of protection mode switches -system.cpu1.kern.mode_switch::user 640 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2399 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 844 -system.cpu1.kern.mode_good::user 640 -system.cpu1.kern.mode_good::idle 204 -system.cpu1.kern.mode_switch_good::kernel 0.519704 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 54577 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1699 # number of protection mode switches +system.cpu1.kern.mode_switch::user 669 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2429 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 888 +system.cpu1.kern.mode_good::user 669 +system.cpu1.kern.mode_good::idle 219 +system.cpu1.kern.mode_switch_good::kernel 0.522660 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.085035 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.361999 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4862135000 0.26% 0.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1013458000 0.05% 0.31% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1900657116000 99.69% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1167 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090161 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.370231 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5315508000 0.28% 0.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1058693000 0.06% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1901174392500 99.67% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1229 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal index 7e0283697..a10880583 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 42d27bf88..311af1e02 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -25,7 +25,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:134217727 +mem_ranges=0:134217727:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false @@ -60,7 +60,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=8796093022208:18446744073709551615 +ranges=8796093022208:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -194,7 +194,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -612,7 +612,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -775,7 +775,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=Cache children=tags -addr_ranges=0:134217727 +addr_ranges=0:134217727:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -820,7 +820,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -832,7 +832,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -864,29 +864,36 @@ update_data=false warn_access= pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -906,6 +913,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -915,7 +923,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -937,9 +945,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 04946a155..dd81d337e 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:28 -gem5 executing on e108600-lin, pid 39623 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28053 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1876794488000 because m5_exit instruction encountered +Exiting @ tick 1865011607500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index f5019500b..b9078b8f1 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.862042 # Number of seconds simulated -sim_ticks 1862042063000 # Number of ticks simulated -final_tick 1862042063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.865012 # Number of seconds simulated +sim_ticks 1865011607500 # Number of ticks simulated +final_tick 1865011607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137297 # Simulator instruction rate (inst/s) -host_op_rate 137297 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4825772422 # Simulator tick rate (ticks/s) -host_mem_usage 338492 # Number of bytes of host memory used -host_seconds 385.85 # Real time elapsed on the host -sim_insts 52976505 # Number of instructions simulated -sim_ops 52976505 # Number of ops (including micro ops) simulated +host_inst_rate 117207 # Simulator instruction rate (inst/s) +host_op_rate 117207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4126745503 # Simulator tick rate (ticks/s) +host_mem_usage 335896 # Number of bytes of host memory used +host_seconds 451.93 # Real time elapsed on the host +sim_insts 52969539 # Number of instructions simulated +sim_ops 52969539 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 963392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881792 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 962688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879872 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25846144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7528832 # Number of bytes written to this memory -system.physmem.bytes_written::total 7528832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15053 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388778 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25843520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 962688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 962688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7514368 # Number of bytes written to this memory +system.physmem.bytes_written::total 7514368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15042 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388748 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403846 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117638 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117638 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13362637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13880537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4043320 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4043320 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4043320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13362637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17923857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403846 # Number of read requests accepted -system.physmem.writeReqs 117638 # Number of write requests accepted -system.physmem.readBursts 403846 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117638 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25839232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue -system.physmem.bytesWritten 7527104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25846144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7528832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 403805 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117412 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117412 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 516183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13340331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13857029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 516183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4029127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4029127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4029127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 516183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13340331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17886156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403805 # Number of read requests accepted +system.physmem.writeReqs 117412 # Number of write requests accepted +system.physmem.readBursts 403805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117412 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25836672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue +system.physmem.bytesWritten 7513280 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25843520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7514368 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25618 # Per bank write bursts -system.physmem.perBankRdBursts::1 25426 # Per bank write bursts -system.physmem.perBankRdBursts::2 25537 # Per bank write bursts -system.physmem.perBankRdBursts::3 25512 # Per bank write bursts -system.physmem.perBankRdBursts::4 25419 # Per bank write bursts -system.physmem.perBankRdBursts::5 24740 # Per bank write bursts -system.physmem.perBankRdBursts::6 24937 # Per bank write bursts -system.physmem.perBankRdBursts::7 25096 # Per bank write bursts -system.physmem.perBankRdBursts::8 24930 # Per bank write bursts -system.physmem.perBankRdBursts::9 25035 # Per bank write bursts -system.physmem.perBankRdBursts::10 25569 # Per bank write bursts -system.physmem.perBankRdBursts::11 24892 # Per bank write bursts -system.physmem.perBankRdBursts::12 24450 # Per bank write bursts -system.physmem.perBankRdBursts::13 25273 # Per bank write bursts -system.physmem.perBankRdBursts::14 25713 # Per bank write bursts -system.physmem.perBankRdBursts::15 25591 # Per bank write bursts -system.physmem.perBankWrBursts::0 7930 # Per bank write bursts -system.physmem.perBankWrBursts::1 7514 # Per bank write bursts -system.physmem.perBankWrBursts::2 7945 # Per bank write bursts -system.physmem.perBankWrBursts::3 7523 # Per bank write bursts -system.physmem.perBankWrBursts::4 7351 # Per bank write bursts -system.physmem.perBankWrBursts::5 6673 # Per bank write bursts -system.physmem.perBankWrBursts::6 6769 # Per bank write bursts -system.physmem.perBankWrBursts::7 6726 # Per bank write bursts -system.physmem.perBankWrBursts::8 7138 # Per bank write bursts -system.physmem.perBankWrBursts::9 6708 # Per bank write bursts -system.physmem.perBankWrBursts::10 7428 # Per bank write bursts -system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 7147 # Per bank write bursts -system.physmem.perBankWrBursts::13 7895 # Per bank write bursts -system.physmem.perBankWrBursts::14 8063 # Per bank write bursts -system.physmem.perBankWrBursts::15 7810 # Per bank write bursts +system.physmem.perBankRdBursts::0 25445 # Per bank write bursts +system.physmem.perBankRdBursts::1 25617 # Per bank write bursts +system.physmem.perBankRdBursts::2 25496 # Per bank write bursts +system.physmem.perBankRdBursts::3 25620 # Per bank write bursts +system.physmem.perBankRdBursts::4 25117 # Per bank write bursts +system.physmem.perBankRdBursts::5 25178 # Per bank write bursts +system.physmem.perBankRdBursts::6 24740 # Per bank write bursts +system.physmem.perBankRdBursts::7 24558 # Per bank write bursts +system.physmem.perBankRdBursts::8 25032 # Per bank write bursts +system.physmem.perBankRdBursts::9 25302 # Per bank write bursts +system.physmem.perBankRdBursts::10 25290 # Per bank write bursts +system.physmem.perBankRdBursts::11 25006 # Per bank write bursts +system.physmem.perBankRdBursts::12 24377 # Per bank write bursts +system.physmem.perBankRdBursts::13 25425 # Per bank write bursts +system.physmem.perBankRdBursts::14 25800 # Per bank write bursts +system.physmem.perBankRdBursts::15 25695 # Per bank write bursts +system.physmem.perBankWrBursts::0 7802 # Per bank write bursts +system.physmem.perBankWrBursts::1 7592 # Per bank write bursts +system.physmem.perBankWrBursts::2 7774 # Per bank write bursts +system.physmem.perBankWrBursts::3 7602 # Per bank write bursts +system.physmem.perBankWrBursts::4 7239 # Per bank write bursts +system.physmem.perBankWrBursts::5 7182 # Per bank write bursts +system.physmem.perBankWrBursts::6 6741 # Per bank write bursts +system.physmem.perBankWrBursts::7 6416 # Per bank write bursts +system.physmem.perBankWrBursts::8 7149 # Per bank write bursts +system.physmem.perBankWrBursts::9 6926 # Per bank write bursts +system.physmem.perBankWrBursts::10 7200 # Per bank write bursts +system.physmem.perBankWrBursts::11 7003 # Per bank write bursts +system.physmem.perBankWrBursts::12 6957 # Per bank write bursts +system.physmem.perBankWrBursts::13 7880 # Per bank write bursts +system.physmem.perBankWrBursts::14 8017 # Per bank write bursts +system.physmem.perBankWrBursts::15 7915 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1862036687500 # Total gap between requests +system.physmem.numWrRetry 50 # Number of times write queue was full causing retry +system.physmem.totGap 1865006319500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403846 # Read request sizes (log2) +system.physmem.readPktSize::6 403805 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117638 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117412 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -149,195 +149,207 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61611 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 541.558358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 333.246769 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.180517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13396 21.74% 21.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10505 17.05% 38.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5359 8.70% 47.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2621 4.25% 51.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2461 3.99% 55.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1425 2.31% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1507 2.45% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1351 2.19% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22986 37.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5236 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.104660 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2917.579007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5233 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 103 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 544.625012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 334.721385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.137572 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13321 21.75% 21.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10685 17.45% 39.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4509 7.36% 46.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2718 4.44% 51.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2169 3.54% 54.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1832 2.99% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1887 3.08% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1551 2.53% 63.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22562 36.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61234 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.280396 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2939.585639 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5154 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5236 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.461994 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.033018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.013556 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4631 88.45% 88.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 42 0.80% 89.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 243 4.64% 93.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 21 0.40% 94.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 6 0.11% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 10 0.19% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 6 0.11% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 20 0.38% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 23 0.44% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 185 3.53% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 2 0.04% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 3 0.06% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 7 0.13% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 11 0.21% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5236 # Writes before turning the bus around for reads -system.physmem.totQLat 3726058000 # Total ticks spent queuing -system.physmem.totMemAccLat 11296145500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018690000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9228.90 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.764204 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.942160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.363230 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4631 89.80% 89.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 32 0.62% 90.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 183 3.55% 93.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 6 0.12% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 4 0.08% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 9 0.17% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 9 0.17% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 4 0.08% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 32 0.62% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.10% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 155 3.01% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 14 0.27% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 9 0.17% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 9 0.17% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 4 0.08% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 8 0.16% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.12% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.19% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.19% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.08% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads +system.physmem.totQLat 7801574500 # Total ticks spent queuing +system.physmem.totMemAccLat 15370912000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018490000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19325.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27978.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.88 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38075.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.03 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing -system.physmem.readRowHits 364089 # Number of row buffer hits during reads -system.physmem.writeRowHits 95648 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.31 # Row buffer hit rate for writes -system.physmem.avgGap 3570649.70 # Average gap between requests -system.physmem.pageHitRate 88.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230882400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125977500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577823000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378632880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56327619735 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1067810937000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1248070945155 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.272471 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1776230272500 # Time in different power states -system.physmem_0.memoryStateTime::REF 62177440000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23627517500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 234896760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 128167875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1571286600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383486400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 56258103960 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1067871924000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1248066938235 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.270314 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1776335363750 # Time in different power states -system.physmem_1.memoryStateTime::REF 62177440000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23523591750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 19539848 # Number of BP lookups -system.cpu.branchPred.condPredicted 16614646 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 591620 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12579114 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5416634 # Number of BTB hits +system.physmem.avgRdQLen 1.96 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.64 # Average write queue length when enqueuing +system.physmem.readRowHits 364428 # Number of row buffer hits during reads +system.physmem.writeRowHits 95430 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.28 # Row buffer hit rate for writes +system.physmem.avgGap 3578176.31 # Average gap between requests +system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 214821180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 114180165 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1440644940 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 304576560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3637439520.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4203799590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 238276320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7970182890 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4260887040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 438967517640 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 461353182075 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.372821 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1855132089750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 377139000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1545232000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1826595828250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 11096155750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7918821750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 17478430750 # Time in different power states +system.physmem_1.actEnergy 222396720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118202865 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1441758780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 308225340 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3641127360.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4165097730 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 227687040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8135120370 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4246672320 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 438904577085 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 461412058890 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.404390 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1855277049250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 349511250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1546624000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1826382821500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11059060000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7833171250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 17840419500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 19540652 # Number of BP lookups +system.cpu.branchPred.condPredicted 16609155 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 593501 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12781935 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5419166 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 43.060537 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1121926 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41569 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6087322 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 563395 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5523927 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 264320 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 42.397071 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1123794 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42287 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6265125 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 563559 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5701566 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 264926 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 11126873 # DTB read hits -system.cpu.dtb.read_misses 49288 # DTB read misses -system.cpu.dtb.read_acv 612 # DTB read access violations -system.cpu.dtb.read_accesses 995471 # DTB read accesses -system.cpu.dtb.write_hits 6773971 # DTB write hits -system.cpu.dtb.write_misses 12183 # DTB write misses -system.cpu.dtb.write_acv 423 # DTB write access violations -system.cpu.dtb.write_accesses 345274 # DTB write accesses -system.cpu.dtb.data_hits 17900844 # DTB hits -system.cpu.dtb.data_misses 61471 # DTB misses -system.cpu.dtb.data_acv 1035 # DTB access violations -system.cpu.dtb.data_accesses 1340745 # DTB accesses -system.cpu.itb.fetch_hits 1815480 # ITB hits -system.cpu.itb.fetch_misses 10441 # ITB misses -system.cpu.itb.fetch_acv 750 # ITB acv -system.cpu.itb.fetch_accesses 1825921 # ITB accesses +system.cpu.dtb.read_hits 11133148 # DTB read hits +system.cpu.dtb.read_misses 49550 # DTB read misses +system.cpu.dtb.read_acv 604 # DTB read access violations +system.cpu.dtb.read_accesses 995639 # DTB read accesses +system.cpu.dtb.write_hits 6779390 # DTB write hits +system.cpu.dtb.write_misses 12217 # DTB write misses +system.cpu.dtb.write_acv 419 # DTB write access violations +system.cpu.dtb.write_accesses 345330 # DTB write accesses +system.cpu.dtb.data_hits 17912538 # DTB hits +system.cpu.dtb.data_misses 61767 # DTB misses +system.cpu.dtb.data_acv 1023 # DTB access violations +system.cpu.dtb.data_accesses 1340969 # DTB accesses +system.cpu.itb.fetch_hits 1814760 # ITB hits +system.cpu.itb.fetch_misses 10379 # ITB misses +system.cpu.itb.fetch_acv 753 # ITB acv +system.cpu.itb.fetch_accesses 1825139 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -352,146 +364,146 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12878 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 279534848.967231 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439378966.267034 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279577818.217114 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 438970116.286468 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 96000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 62000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 62117170500 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1799924892500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 124240781 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64810036000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1800201571500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 129626512 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30188704 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85612379 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19539848 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7101955 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 86725868 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1678156 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 30190363 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85695972 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19540652 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7106519 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 91835709 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1682318 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31498 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 207275 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 432547 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9909625 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 405389 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.MiscStallCycles 29737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 207098 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 428060 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 576 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9928105 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 408572 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 118425370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.722923 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.060283 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 123532763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.693710 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.023135 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102607090 86.64% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1029926 0.87% 87.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2106958 1.78% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 967243 0.82% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2899427 2.45% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 665654 0.56% 93.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 809857 0.68% 93.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1032032 0.87% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6307183 5.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 107696719 87.18% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1032377 0.84% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2107068 1.71% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 968796 0.78% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2908740 2.35% 92.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 664008 0.54% 93.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 809572 0.66% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1033225 0.84% 94.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6312258 5.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 118425370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.157274 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.689084 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24239485 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 81100635 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 10246732 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2034421 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 804096 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 734883 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 35786 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 73972445 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 113808 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 804096 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25248689 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52456334 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19565246 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11202200 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9148803 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 70966243 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 196842 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2117370 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 228092 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4881037 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 47806174 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 85505184 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 85324382 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168350 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38176913 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9629253 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1728484 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 276268 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13926032 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 11656323 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7221031 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1724354 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1093863 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62666856 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2206869 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 60507866 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 96262 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11897215 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5284366 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1545682 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 118425370 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.510937 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.257755 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 123532763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150746 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.661099 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24222797 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86210181 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 10254650 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2038697 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 806437 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 738100 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 35530 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 74041720 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 113425 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 806437 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25231796 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56630169 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20045874 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11215615 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9602870 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 71021126 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 199714 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2114917 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 266619 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5298821 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 47846131 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 85558708 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 85377795 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168460 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38170817 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9675306 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1730146 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 277278 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13907871 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11664536 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7226725 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1727084 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1123210 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62712842 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2208202 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 60540114 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 93631 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11951500 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5299174 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1546957 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 123532763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.490073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.235792 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 93896241 79.29% 79.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10410761 8.79% 88.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4424184 3.74% 91.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3178503 2.68% 94.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3240709 2.74% 97.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1606797 1.36% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1097474 0.93% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 434045 0.37% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 136656 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 98992964 80.13% 80.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10407106 8.42% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4428528 3.58% 92.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3186499 2.58% 94.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3245157 2.63% 97.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1605158 1.30% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1098083 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 432605 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 136663 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 118425370 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123532763 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206587 16.63% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 638209 51.38% 68.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 397270 31.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 207032 16.67% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 637905 51.36% 68.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 397118 31.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7277 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40893641 67.58% 67.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62155 0.10% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7276 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40915146 67.58% 67.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62152 0.10% 67.70% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38558 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38560 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued @@ -517,95 +529,95 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11671611 19.29% 87.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6881999 11.37% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948989 1.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11677570 19.29% 87.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6886648 11.38% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 60507866 # Type of FU issued -system.cpu.iq.rate 0.487021 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1242066 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020527 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 240042364 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 76433076 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 58286910 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 737065 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 359346 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 336745 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61347086 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 395569 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 690461 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 60540114 # Type of FU issued +system.cpu.iq.rate 0.467035 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1242056 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020516 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 245211443 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 76534751 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 58316055 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 737234 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 359442 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 336937 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 61379174 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 395720 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 691177 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2564224 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22069 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 843181 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2573780 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 22128 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 849514 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17987 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 463704 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18020 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 462679 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 804096 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 49123510 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 920451 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 68850753 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 204809 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 11656323 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7221031 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1958834 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45972 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 671584 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22069 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 229357 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 628132 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 857489 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 59656852 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 11208773 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 851013 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 806437 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 52697038 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1357053 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 68903527 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 198807 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11664536 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7226725 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1959166 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45872 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1108146 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 22128 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 230653 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 630212 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 860865 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 59685899 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 11215511 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 854214 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3977028 # number of nop insts executed -system.cpu.iew.exec_refs 18015122 # number of memory reference insts executed -system.cpu.iew.exec_branches 9379233 # Number of branches executed -system.cpu.iew.exec_stores 6806349 # Number of stores executed -system.cpu.iew.exec_rate 0.480171 # Inst execution rate -system.cpu.iew.wb_sent 58867691 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 58623655 # cumulative count of insts written-back -system.cpu.iew.wb_producers 29756177 # num instructions producing a value -system.cpu.iew.wb_consumers 41250197 # num instructions consuming a value -system.cpu.iew.wb_rate 0.471855 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721358 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12492004 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661187 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 767634 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 116265516 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.483093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.421972 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3982483 # number of nop insts executed +system.cpu.iew.exec_refs 18027322 # number of memory reference insts executed +system.cpu.iew.exec_branches 9384105 # Number of branches executed +system.cpu.iew.exec_stores 6811811 # Number of stores executed +system.cpu.iew.exec_rate 0.460445 # Inst execution rate +system.cpu.iew.wb_sent 58897557 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 58652992 # cumulative count of insts written-back +system.cpu.iew.wb_producers 29769052 # num instructions producing a value +system.cpu.iew.wb_consumers 41264413 # num instructions consuming a value +system.cpu.iew.wb_rate 0.452477 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721422 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12552458 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 769809 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121361631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462746 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.395074 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 96403146 82.92% 82.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7978599 6.86% 89.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4192375 3.61% 93.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2264506 1.95% 95.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1757271 1.51% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 632678 0.54% 97.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 482043 0.41% 97.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 513720 0.44% 98.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2041178 1.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 101505032 83.64% 83.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7973925 6.57% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4190958 3.45% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2263923 1.87% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1758393 1.45% 96.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 630847 0.52% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 481222 0.40% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 521755 0.43% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2035576 1.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 116265516 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56167063 # Number of instructions committed -system.cpu.commit.committedOps 56167063 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 121361631 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56159642 # Number of instructions committed +system.cpu.commit.committedOps 56159642 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15469949 # Number of memory references committed -system.cpu.commit.loads 9092099 # Number of loads committed -system.cpu.commit.membars 226348 # Number of memory barriers committed -system.cpu.commit.branches 8440307 # Number of branches committed +system.cpu.commit.refs 15467967 # Number of memory references committed +system.cpu.commit.loads 9090756 # Number of loads committed +system.cpu.commit.membars 226364 # Number of memory barriers committed +system.cpu.commit.branches 8439956 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52016709 # Number of committed integer instructions. -system.cpu.commit.function_calls 740521 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197831 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36215597 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60674 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52009640 # Number of committed integer instructions. +system.cpu.commit.function_calls 740476 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197376 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36210459 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60672 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -633,544 +645,544 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9318447 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6383804 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 948989 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9317120 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383168 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56167063 # Class of committed instruction -system.cpu.commit.bw_lim_events 2041178 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 182633884 # The number of ROB reads -system.cpu.rob.rob_writes 139481914 # The number of ROB writes -system.cpu.timesIdled 555871 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5815411 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599843346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52976505 # Number of Instructions Simulated -system.cpu.committedOps 52976505 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.345205 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.345205 # CPI: Total CPI of All Threads -system.cpu.ipc 0.426402 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.426402 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 77842014 # number of integer regfile reads -system.cpu.int_regfile_writes 42572961 # number of integer regfile writes -system.cpu.fp_regfile_reads 166584 # number of floating regfile reads -system.cpu.fp_regfile_writes 175742 # number of floating regfile writes -system.cpu.misc_regfile_reads 2001057 # number of misc regfile reads -system.cpu.misc_regfile_writes 939419 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1405448 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994324 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 12624146 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1405960 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.979022 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 26885500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994324 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 56159642 # Class of committed instruction +system.cpu.commit.bw_lim_events 2035576 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 187788618 # The number of ROB reads +system.cpu.rob.rob_writes 139599579 # The number of ROB writes +system.cpu.timesIdled 556181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6093749 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3600396704 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52969539 # Number of Instructions Simulated +system.cpu.committedOps 52969539 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.447190 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.447190 # CPI: Total CPI of All Threads +system.cpu.ipc 0.408632 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.408632 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 77875565 # number of integer regfile reads +system.cpu.int_regfile_writes 42594378 # number of integer regfile writes +system.cpu.fp_regfile_reads 166655 # number of floating regfile reads +system.cpu.fp_regfile_writes 175866 # number of floating regfile writes +system.cpu.misc_regfile_reads 2002132 # number of misc regfile reads +system.cpu.misc_regfile_writes 939499 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1405977 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12626898 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1406489 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.977602 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 67117469 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 67117469 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 8015814 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8015814 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4179783 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4179783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 212605 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 212605 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215671 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215671 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 12195597 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12195597 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 12195597 # number of overall hits -system.cpu.dcache.overall_hits::total 12195597 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1813103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1813103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1967603 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1967603 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23208 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23208 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 90 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 90 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3780706 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3780706 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3780706 # number of overall misses -system.cpu.dcache.overall_misses::total 3780706 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 42125006500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 42125006500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 80961387023 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 80961387023 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 351774000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 351774000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1258000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 1258000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 123086393523 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 123086393523 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 123086393523 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 123086393523 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9828917 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9828917 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147386 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147386 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235813 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235813 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215761 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215761 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15976303 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15976303 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15976303 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15976303 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184466 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184466 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320071 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.320071 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098417 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098417 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000417 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000417 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.236645 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.236645 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.236645 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.236645 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23233.653300 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23233.653300 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41147.216701 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41147.216701 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15157.445708 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15157.445708 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13977.777778 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13977.777778 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32556.457319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32556.457319 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4549830 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3359 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 133574 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.062243 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 93.305556 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 843871 # number of writebacks -system.cpu.dcache.writebacks::total 843871 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 713283 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 713283 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1678038 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1678038 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6508 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6508 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2391321 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2391321 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2391321 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2391321 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1099820 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1099820 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289565 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289565 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16700 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16700 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 90 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 90 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389385 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389385 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389385 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389385 # number of overall MSHR misses +system.cpu.dcache.tags.tag_accesses 67141007 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 67141007 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 8018368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8018368 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4180367 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4180367 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 212226 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 212226 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215667 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215667 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 12198735 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 12198735 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 12198735 # number of overall hits +system.cpu.dcache.overall_hits::total 12198735 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1817070 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1817070 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1966374 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1966374 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23459 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23459 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 98 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 98 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3783444 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3783444 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3783444 # number of overall misses +system.cpu.dcache.overall_misses::total 3783444 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45126424500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45126424500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 92431305073 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 92431305073 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 416761500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 416761500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1368500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 1368500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137557729573 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137557729573 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137557729573 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137557729573 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9835438 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9835438 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146741 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146741 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235685 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 235685 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215765 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215765 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15982179 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15982179 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15982179 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15982179 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184747 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184747 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319905 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319905 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099535 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099535 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000454 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000454 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.236729 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.236729 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.236729 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.236729 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24834.719906 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24834.719906 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47005.963806 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47005.963806 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17765.527090 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17765.527090 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13964.285714 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13964.285714 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36357.807747 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36357.807747 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4938618 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4294 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 133157 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.088685 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 153.357143 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 844399 # number of writebacks +system.cpu.dcache.writebacks::total 844399 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716933 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 716933 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676859 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1676859 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6505 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6505 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2393792 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2393792 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2393792 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2393792 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100137 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1100137 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289515 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289515 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16954 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16954 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 98 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 98 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1389652 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1389652 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1389652 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1389652 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # 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average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31344.138453 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31344.138453 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31344.138453 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31344.138453 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221524.314574 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221524.314574 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92882.593175 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92882.593175 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # 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number of replacements +system.cpu.icache.tags.tagsinuse 509.003606 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8782144 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1077267 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.152245 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 30283847500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.003606 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994148 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994148 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10985459 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10985459 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 8765751 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8765751 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8765751 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8765751 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8765751 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15979138992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9909619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9909619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9909619 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9909619 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9909619 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9909619 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115430 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115430 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115430 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115430 # 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Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 8782144 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8782144 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8782144 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8782144 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8782144 # number of overall hits +system.cpu.icache.overall_hits::total 8782144 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1145952 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1145952 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1145952 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1145952 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1145952 # number of overall misses +system.cpu.icache.overall_misses::total 1145952 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16332614990 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16332614990 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16332614990 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16332614990 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16332614990 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16332614990 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9928096 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9928096 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9928096 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9928096 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9928096 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9928096 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115425 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.115425 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.115425 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.115425 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.115425 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.115425 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14252.442502 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14252.442502 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14252.442502 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14252.442502 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8348 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 228 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 326 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.578947 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.607362 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1075014 # number of writebacks -system.cpu.icache.writebacks::total 1075014 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68028 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448524000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097561 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097561 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382246 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382246 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013998 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248230 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248230 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.162919 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.162919 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 38437.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 38437.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80029.342017 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80029.342017 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74629.899030 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74629.899030 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63892.586157 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63892.586157 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209022.222222 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209022.222222 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87640.609874 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87640.609874 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4962480 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480820 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 950 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 328500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 328500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10897718500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10897718500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1366325500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1366325500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19653014500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19653014500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1366325500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30550733000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31917058500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1366325500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30550733000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31917058500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448486500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448486500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448486500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448486500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382415 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382415 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013965 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248043 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248043 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.162754 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.162754 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 36500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94989.919372 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94989.919372 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90827.993086 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90827.993086 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71604.289405 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71604.289405 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209016.810967 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209016.810967 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87633.038901 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87633.038901 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4967024 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483092 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2362 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2188821 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 919997 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1075014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 824089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 90 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 172 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 300066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 254 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3226322 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4251016 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7477338 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137630848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144043380 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 281674228 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 339580 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4905856 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2837598 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001208 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.034736 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 2191157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 920299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1076759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 824292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 78 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 98 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 300001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077581 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 40 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3231525 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252605 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7484130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137852416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144111100 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 281963516 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 339563 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4892928 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2839828 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001278 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.035720 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2834170 99.88% 99.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3428 0.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2836200 99.87% 99.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3628 0.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2837598 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4413188000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2839828 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4417734000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1614811393 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1617399440 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2121037981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2121770107 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1184,12 +1196,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51150 # Transaction distribution -system.iobus.trans_dist::WriteResp 51150 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51151 # Transaction distribution +system.iobus.trans_dist::WriteResp 51151 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1198,11 +1210,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1211,50 +1223,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5361000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5359000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14040000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14034000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2177500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6050500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6056500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 92500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216173801 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216222032 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.258860 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.265413 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712294555000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.258860 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078679 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078679 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714256790000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.079088 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1263,14 +1275,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21845883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21845883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858784918 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4858784918 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4880630801 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4880630801 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4880630801 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4880630801 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21932883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21932883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4939835149 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4939835149 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4961768032 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4961768032 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4961768032 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4961768032 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1287,19 +1299,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126276.780347 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126276.780347 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116932.636648 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116932.636648 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116971.379293 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116971.379293 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 8 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126779.670520 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126779.670520 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118883.210170 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118883.210170 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118915.950437 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118915.950437 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 2115 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 132.187500 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1311,14 +1323,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13195883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13195883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778792164 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2778792164 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2791988047 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2791988047 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2791988047 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2791988047 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13282883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13282883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2859804565 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2859804565 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2873087448 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2873087448 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2873087448 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2873087448 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1327,75 +1339,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76276.780347 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76276.780347 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66875.052079 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66875.052079 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 825555 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 380464 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76779.670520 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76779.670520 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68824.715176 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.715176 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 825525 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 380458 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 296639 # Transaction distribution -system.membus.trans_dist::WriteReq 9598 # Transaction distribution -system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117638 # Transaction distribution -system.membus.trans_dist::CleanEvict 261892 # Transaction distribution -system.membus.trans_dist::UpgradeReq 135 # Transaction distribution +system.membus.trans_dist::ReadResp 296573 # Transaction distribution +system.membus.trans_dist::WriteReq 9599 # Transaction distribution +system.membus.trans_dist::WriteResp 9599 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117412 # Transaction distribution +system.membus.trans_dist::CleanEvict 262094 # Transaction distribution +system.membus.trans_dist::UpgradeReq 137 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 114572 # Transaction distribution -system.membus.trans_dist::ReadExResp 114572 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289754 # Transaction distribution -system.membus.trans_dist::BadAddressError 45 # Transaction distribution +system.membus.trans_dist::ReadExReq 114597 # Transaction distribution +system.membus.trans_dist::ReadExResp 114597 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289683 # Transaction distribution +system.membus.trans_dist::BadAddressError 40 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179065 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 80 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178953 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262490 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30717248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30761396 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1262378 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30700160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30744316 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33419124 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33402044 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 438 # Total snoops (count) system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 462541 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001500 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038706 # Request fanout histogram +system.membus.snoop_fanout::samples 462498 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038232 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 461847 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 694 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 461821 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 462541 # Request fanout histogram -system.membus.reqLayer0.occupancy 28740000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 462498 # Request fanout histogram +system.membus.reqLayer0.occupancy 28738500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314155780 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313413567 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 57000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 48500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139053000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2137867250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 917617 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1427,52 +1439,52 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210996 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74658 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105558 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182227 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73291 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105578 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182260 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73291 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148593 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818067214500 97.64% 97.64% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 67498000 0.00% 97.64% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 564111500 0.03% 97.67% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 43342412500 2.33% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1862041236500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981690 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1819136783500 97.54% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 67099500 0.00% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 565538000 0.03% 97.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 45241360000 2.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865010781000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694320 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815428 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694302 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815418 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1511,29 +1523,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175110 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175141 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191955 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.callpal::total 191988 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29461996000 1.58% 1.58% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2701361000 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1829877871500 98.27% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29668657000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2761122500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832580993500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal index 2c979b67f..b49f55c8a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini index c192e9ff7..8732f763e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -208,7 +208,7 @@ useIndirect=true [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -688,7 +688,7 @@ opClass=InstPrefetch [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -748,7 +748,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -820,7 +820,7 @@ port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -1024,7 +1024,7 @@ useIndirect=true [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1504,7 +1504,7 @@ opClass=InstPrefetch [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1564,7 +1564,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -1636,7 +1636,7 @@ port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -1783,7 +1783,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -1829,7 +1829,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1927,27 +1927,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1967,6 +1967,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1976,7 +1977,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1998,9 +1999,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -2353,7 +2354,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -2670,6 +2671,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2677,7 +2679,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2908,6 +2910,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2915,7 +2918,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout index 2149b379f..4c439b2cd 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:42:06 -gem5 executing on e108600-lin, pid 23137 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:42:59 +gem5 executing on e108600-lin, pid 17317 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2647778082500 because m5_exit instruction encountered +Exiting @ tick 2848926718000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 14253ba3e..636a3faf7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848172 # Number of seconds simulated -sim_ticks 2848172284000 # Number of ticks simulated -final_tick 2848172284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848927 # Number of seconds simulated +sim_ticks 2848926718000 # Number of ticks simulated +final_tick 2848926718000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135409 # Simulator instruction rate (inst/s) -host_op_rate 163982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3007675070 # Simulator tick rate (ticks/s) -host_mem_usage 625764 # Number of bytes of host memory used -host_seconds 946.97 # Real time elapsed on the host -sim_insts 128228197 # Number of instructions simulated -sim_ops 155285827 # Number of ops (including micro ops) simulated +host_inst_rate 113585 # Simulator instruction rate (inst/s) +host_op_rate 137549 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2529912934 # Simulator tick rate (ticks/s) +host_mem_usage 622248 # Number of bytes of host memory used +host_seconds 1126.10 # Real time elapsed on the host +sim_insts 127907365 # Number of instructions simulated +sim_ops 154893549 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 9536 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1677760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1343340 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8401088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 221184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 660436 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 438272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1676224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1355764 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8486720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 229952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 664980 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 417216 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12753472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1677760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 221184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1898944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9008896 # Number of bytes written to this memory +system.physmem.bytes_read::total 12842440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1676224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 229952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1906176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9074368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9026460 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9091932 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 149 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131267 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10340 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26191 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 132605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10411 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6519 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199815 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 140764 # Number of write requests responded to by this memory +system.physmem.num_reads::total 201207 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141787 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145155 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3146 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 146178 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3347 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 589065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 471650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2949642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 231881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 153878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 588370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 475886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2978918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 233414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 146447 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4477774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 589065 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77658 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 666724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3163045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4507817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 588370 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80715 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 669086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3185188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3169211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3163045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3191353 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3185188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 589065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 477803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2949642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 231895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 153878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 588370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 482037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2978918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 233428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 146447 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7646985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199815 # Number of read requests accepted -system.physmem.writeReqs 145155 # Number of write requests accepted -system.physmem.readBursts 199815 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 145155 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12777984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 9038976 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12753472 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9026460 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 7699170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 201207 # Number of read requests accepted +system.physmem.writeReqs 146178 # Number of write requests accepted +system.physmem.readBursts 201207 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 146178 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12868352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue +system.physmem.bytesWritten 9104640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12842440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9091932 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12196 # Per bank write bursts -system.physmem.perBankRdBursts::1 12508 # Per bank write bursts -system.physmem.perBankRdBursts::2 12943 # Per bank write bursts -system.physmem.perBankRdBursts::3 12617 # Per bank write bursts -system.physmem.perBankRdBursts::4 14662 # Per bank write bursts -system.physmem.perBankRdBursts::5 11885 # Per bank write bursts -system.physmem.perBankRdBursts::6 12499 # Per bank write bursts -system.physmem.perBankRdBursts::7 12704 # Per bank write bursts -system.physmem.perBankRdBursts::8 12537 # Per bank write bursts -system.physmem.perBankRdBursts::9 12319 # Per bank write bursts -system.physmem.perBankRdBursts::10 11826 # Per bank write bursts -system.physmem.perBankRdBursts::11 10998 # Per bank write bursts -system.physmem.perBankRdBursts::12 12485 # Per bank write bursts -system.physmem.perBankRdBursts::13 13119 # Per bank write bursts -system.physmem.perBankRdBursts::14 12369 # Per bank write bursts -system.physmem.perBankRdBursts::15 11989 # Per bank write bursts -system.physmem.perBankWrBursts::0 8816 # Per bank write bursts -system.physmem.perBankWrBursts::1 9166 # Per bank write bursts -system.physmem.perBankWrBursts::2 9495 # Per bank write bursts -system.physmem.perBankWrBursts::3 9136 # Per bank write bursts -system.physmem.perBankWrBursts::4 8038 # Per bank write bursts -system.physmem.perBankWrBursts::5 8411 # Per bank write bursts -system.physmem.perBankWrBursts::6 8988 # Per bank write bursts -system.physmem.perBankWrBursts::7 8984 # Per bank write bursts -system.physmem.perBankWrBursts::8 9026 # Per bank write bursts -system.physmem.perBankWrBursts::9 8762 # Per bank write bursts -system.physmem.perBankWrBursts::10 8598 # Per bank write bursts -system.physmem.perBankWrBursts::11 8287 # Per bank write bursts -system.physmem.perBankWrBursts::12 9114 # Per bank write bursts -system.physmem.perBankWrBursts::13 9118 # Per bank write bursts -system.physmem.perBankWrBursts::14 8888 # Per bank write bursts -system.physmem.perBankWrBursts::15 8407 # Per bank write bursts +system.physmem.perBankRdBursts::0 12387 # Per bank write bursts +system.physmem.perBankRdBursts::1 12818 # Per bank write bursts +system.physmem.perBankRdBursts::2 13574 # Per bank write bursts +system.physmem.perBankRdBursts::3 13051 # Per bank write bursts +system.physmem.perBankRdBursts::4 15332 # Per bank write bursts +system.physmem.perBankRdBursts::5 12655 # Per bank write bursts +system.physmem.perBankRdBursts::6 12896 # Per bank write bursts +system.physmem.perBankRdBursts::7 13054 # Per bank write bursts +system.physmem.perBankRdBursts::8 12485 # Per bank write bursts +system.physmem.perBankRdBursts::9 12494 # Per bank write bursts +system.physmem.perBankRdBursts::10 11451 # Per bank write bursts +system.physmem.perBankRdBursts::11 10701 # Per bank write bursts +system.physmem.perBankRdBursts::12 11947 # Per bank write bursts +system.physmem.perBankRdBursts::13 12784 # Per bank write bursts +system.physmem.perBankRdBursts::14 11815 # Per bank write bursts +system.physmem.perBankRdBursts::15 11624 # Per bank write bursts +system.physmem.perBankWrBursts::0 9013 # Per bank write bursts +system.physmem.perBankWrBursts::1 9459 # Per bank write bursts +system.physmem.perBankWrBursts::2 10048 # Per bank write bursts +system.physmem.perBankWrBursts::3 9447 # Per bank write bursts +system.physmem.perBankWrBursts::4 8653 # Per bank write bursts +system.physmem.perBankWrBursts::5 8898 # Per bank write bursts +system.physmem.perBankWrBursts::6 9273 # Per bank write bursts +system.physmem.perBankWrBursts::7 9228 # Per bank write bursts +system.physmem.perBankWrBursts::8 8869 # Per bank write bursts +system.physmem.perBankWrBursts::9 8977 # Per bank write bursts +system.physmem.perBankWrBursts::10 8270 # Per bank write bursts +system.physmem.perBankWrBursts::11 7926 # Per bank write bursts +system.physmem.perBankWrBursts::12 8743 # Per bank write bursts +system.physmem.perBankWrBursts::13 8906 # Per bank write bursts +system.physmem.perBankWrBursts::14 8530 # Per bank write bursts +system.physmem.perBankWrBursts::15 8020 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 34 # Number of times write queue was full causing retry -system.physmem.totGap 2848171745000 # Total gap between requests +system.physmem.numWrRetry 92 # Number of times write queue was full causing retry +system.physmem.totGap 2848926179000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 552 # Read request sizes (log2) +system.physmem.readPktSize::2 554 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 199235 # Read request sizes (log2) +system.physmem.readPktSize::6 200625 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 140764 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3767 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 141787 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 84607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3992 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -185,162 +185,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 88 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88570 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.323767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 141.050118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.878369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 44937 50.74% 50.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18529 20.92% 71.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6585 7.43% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3856 4.35% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3004 3.39% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1517 1.71% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 921 1.04% 89.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1037 1.17% 90.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8184 9.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88570 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.368144 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 555.266808 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7037 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 262 # What write queue length does an incoming req see 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an incoming req see +system.physmem.wrQLenPdf::55 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 295 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 89804 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.676495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.021398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.276619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45910 51.12% 51.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18733 20.86% 71.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6663 7.42% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3737 4.16% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2991 3.33% 86.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1528 1.70% 88.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 943 1.05% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1048 1.17% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8251 9.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89804 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.382976 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 553.950604 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7082 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7038 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7038 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.067349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.571017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.392738 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5944 84.46% 84.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 388 5.51% 89.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 60 0.85% 90.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.65% 91.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 266 3.78% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.30% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.31% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.36% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.21% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 13 0.18% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.18% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 149 2.12% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.16% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 7 0.10% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.13% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.11% 99.83% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7084 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.081875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.511113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.183489 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5975 84.35% 84.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 419 5.91% 90.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 68 0.96% 91.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 50 0.71% 91.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 261 3.68% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.30% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.18% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.24% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.14% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.08% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.11% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 144 2.03% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.13% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.06% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.11% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.07% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.13% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.06% 99.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 3 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7038 # Writes before turning the bus around for reads -system.physmem.totQLat 5532611303 # Total ticks spent queuing -system.physmem.totMemAccLat 9276161303 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 998280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27710.72 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7084 # Writes before turning the bus around for reads +system.physmem.totQLat 9521946881 # Total ticks spent queuing +system.physmem.totMemAccLat 13291971881 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1005340000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47356.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46460.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 66106.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.18 # Average write queue length when enqueuing -system.physmem.readRowHits 165300 # Number of row buffer hits during reads -system.physmem.writeRowHits 87019 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.60 # Row buffer hit rate for writes -system.physmem.avgGap 8256288.21 # Average gap between requests -system.physmem.pageHitRate 74.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 339738840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 185373375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 795709200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 460300320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186028705200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83305465515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1635827969250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1906943261700 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.532441 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2721218544299 # Time in different power states -system.physmem_0.memoryStateTime::REF 95106700000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31846334451 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 329850360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179977875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 761599800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 454896000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186028705200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82993384530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1636101724500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1906850138265 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.499746 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2721674822130 # Time in different power states -system.physmem_1.memoryStateTime::REF 95106700000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31390664370 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 25.49 # Average write queue length when enqueuing +system.physmem.readRowHits 166479 # Number of row buffer hits during reads +system.physmem.writeRowHits 87044 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.18 # Row buffer hit rate for writes +system.physmem.avgGap 8201062.74 # Average gap between requests +system.physmem.pageHitRate 73.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 339864000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 180642000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 755176380 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 386379180 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5802201600.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5394350610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 323555040 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11564942040 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8568107520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 670261966035 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 703579433835 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.962980 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2836248193267 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 586826713 # Time in different power states +system.physmem_0.memoryStateTime::REF 2465512000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2788574898250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 22312648073 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9624892520 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25361940444 # Time in different power states +system.physmem_1.actEnergy 301343700 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 160164180 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 680449140 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 356218020 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5736435120.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5416162800 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 310781280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10711678260 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8807078880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 670588805775 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 703071916065 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.784837 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2836233678907 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 556712196 # Time in different power states +system.physmem_1.memoryStateTime::REF 2438058000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2789808007000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22935120354 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9698204397 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 23490616053 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -359,30 +375,30 @@ system.realview.nvmem.bw_inst_read::total 472 # I system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20844041 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13655604 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1017556 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13118749 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8767800 # Number of BTB hits +system.cpu0.branchPred.lookups 20832099 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13651765 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1014112 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13085676 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8745572 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.834117 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3422259 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 208349 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 764708 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 581484 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 183224 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 100888 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 66.833169 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3412344 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 213562 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 762387 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 580471 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 181916 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 99152 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -412,61 +428,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 67283 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67283 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46446 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20837 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 67283 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 67283 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 67283 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6844 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12453.243717 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11569.675575 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5895.982503 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6363 92.97% 92.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 412 6.02% 98.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 59 0.86% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 3 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6844 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5263 76.90% 76.90% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1581 23.10% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6844 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67283 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 65584 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65584 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44931 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20653 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 65584 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 65584 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 65584 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6815 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12330.961115 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11272.043541 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 9573.930789 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 6808 99.90% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 5 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6815 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5268 77.30% 77.30% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1547 22.70% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6815 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65584 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67283 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6844 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65584 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6815 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6844 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 74127 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6815 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 72399 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17352300 # DTB read hits -system.cpu0.dtb.read_misses 60872 # DTB read misses -system.cpu0.dtb.write_hits 14551648 # DTB write hits -system.cpu0.dtb.write_misses 6411 # DTB write misses +system.cpu0.dtb.read_hits 17333612 # DTB read hits +system.cpu0.dtb.read_misses 59171 # DTB read misses +system.cpu0.dtb.write_hits 14536785 # DTB write hits +system.cpu0.dtb.write_misses 6413 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3450 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1427 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3455 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1951 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 519 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17413172 # DTB read accesses -system.cpu0.dtb.write_accesses 14558059 # DTB write accesses +system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17392783 # DTB read accesses +system.cpu0.dtb.write_accesses 14543198 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31903948 # DTB hits -system.cpu0.dtb.misses 67283 # DTB misses -system.cpu0.dtb.accesses 31971231 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 31870397 # DTB hits +system.cpu0.dtb.misses 65584 # DTB misses +system.cpu0.dtb.accesses 31935981 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -496,42 +509,41 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3992 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3992 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3686 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3992 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3992 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3992 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2438 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12900.533224 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12073.120538 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5370.959057 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 392 16.08% 16.08% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1803 73.95% 90.03% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 168 6.89% 96.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 38 1.56% 98.48% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 34 1.39% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2438 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2137 87.65% 87.65% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 301 12.35% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2438 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 3993 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3993 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3689 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3993 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3993 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3993 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2420 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12562.190083 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11733.706609 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5199.448662 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 453 18.72% 18.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1764 72.89% 91.61% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 139 5.74% 97.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 98.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 1.12% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2420 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2121 87.64% 87.64% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.36% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2420 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3992 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3992 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3993 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3993 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2438 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2438 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6430 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38811638 # ITB inst hits -system.cpu0.itb.inst_misses 3992 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2420 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2420 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6413 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38722571 # ITB inst hits +system.cpu0.itb.inst_misses 3993 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -540,45 +552,44 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2175 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7061 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7056 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38815630 # ITB inst accesses -system.cpu0.itb.hits 38811638 # DTB hits -system.cpu0.itb.misses 3992 # DTB misses -system.cpu0.itb.accesses 38815630 # DTB accesses -system.cpu0.numPwrStateTransitions 3698 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1849 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1494392801.532720 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23960009045.887756 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1074 58.09% 58.09% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 768 41.54% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 38726564 # ITB inst accesses +system.cpu0.itb.hits 38722571 # DTB hits +system.cpu0.itb.misses 3993 # DTB misses +system.cpu0.itb.accesses 38726564 # DTB accesses +system.cpu0.numPwrStateTransitions 3692 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1846 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1496527734.232936 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23959432114.332718 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1066 57.75% 57.75% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 773 41.87% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963441540 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1849 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 85039993966 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763132290034 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 170082548 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963466540 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1846 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 86336520606 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762590197394 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 172675597 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79775908 # Number of instructions committed -system.cpu0.committedOps 96002231 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5290576 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5526291371 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.132004 # CPI: cycles per instruction -system.cpu0.ipc 0.469042 # IPC: instructions per cycle +system.cpu0.committedInsts 79702454 # Number of instructions committed +system.cpu0.committedOps 95912008 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5263315 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1846 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5525206368 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.166503 # CPI: cycles per instruction +system.cpu0.ipc 0.461573 # IPC: instructions per cycle system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 63778191 66.43% 66.44% # Class of committed instruction -system.cpu0.op_class_0::IntMult 92152 0.10% 66.53% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 63720470 66.44% 66.44% # Class of committed instruction +system.cpu0.op_class_0::IntMult 92091 0.10% 66.53% # Class of committed instruction system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction @@ -602,740 +613,739 @@ system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Cl system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8071 0.01% 66.54% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16825163 17.53% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15296337 15.93% 100.00% # Class of committed instruction +system.cpu0.op_class_0::MemRead 16807812 17.52% 84.07% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15281291 15.93% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 96002231 # Class of committed instruction +system.cpu0.op_class_0::total 95912008 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1849 # number of quiesce instructions executed -system.cpu0.tickCycles 121004168 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 49078380 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 716277 # number of replacements -system.cpu0.dcache.tags.tagsinuse 496.364938 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30460734 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 716789 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.496096 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.364938 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969463 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.969463 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1846 # number of quiesce instructions executed +system.cpu0.tickCycles 120803038 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 51872559 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 716043 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.070686 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30430864 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 716555 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.468288 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.070686 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970841 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.970841 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63863131 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63863131 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15863909 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15863909 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13436402 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13436402 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320993 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 320993 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365530 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365530 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361278 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361278 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29300311 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29300311 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29621304 # number of overall hits -system.cpu0.dcache.overall_hits::total 29621304 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 439369 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 439369 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 580672 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 580672 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135956 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135956 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21086 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21086 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20448 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20448 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1020041 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1020041 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1155997 # number of overall misses -system.cpu0.dcache.overall_misses::total 1155997 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6148409000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6148409000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10121621500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10121621500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 324178500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 324178500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 483049500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 483049500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 688000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 688000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 16270030500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16270030500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 16270030500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16270030500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16303278 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16303278 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14017074 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14017074 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386616 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386616 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381726 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381726 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30320352 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30320352 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30777301 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30777301 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026950 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.026950 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041426 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041426 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297530 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297530 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054540 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054540 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033642 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033642 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037560 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037560 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13993.725092 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13993.725092 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17430.875778 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17430.875778 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15374.110784 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15374.110784 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23623.312793 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23623.312793 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63800570 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63800570 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15847676 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15847676 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13422923 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13422923 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320765 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 320765 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365692 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365692 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361178 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361178 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29270599 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29270599 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29591364 # number of overall hits +system.cpu0.dcache.overall_hits::total 29591364 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 438302 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 438302 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 581071 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 581071 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135874 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 135874 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20748 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20748 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20391 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20391 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1019373 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1019373 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1155247 # number of overall misses +system.cpu0.dcache.overall_misses::total 1155247 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6426011500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6426011500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11337499000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11337499000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330321500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 330321500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481265000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 481265000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 655500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 655500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 17763510500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 17763510500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 17763510500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 17763510500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16285978 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16285978 # number of ReadReq accesses(hits+misses) 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accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30746611 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30746611 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026913 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.026913 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041493 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041493 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297552 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297552 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053690 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053690 # miss rate for LoadLockedReq accesses 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14074.457373 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17425.918187 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17425.918187 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15376.374490 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15376.374490 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 716277 # number of writebacks -system.cpu0.dcache.writebacks::total 716277 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44943 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 44943 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255413 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 255413 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14625 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14625 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 300356 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 300356 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 300356 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 300356 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394426 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 394426 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325259 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325259 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102388 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102388 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6461 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6461 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20448 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20448 # number of StoreCondReq MSHR misses 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uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4556252000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4556252000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024193 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024193 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023204 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023204 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224069 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224069 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016712 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016712 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023736 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023736 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026710 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026710 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12689.718731 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12689.718731 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17099.631371 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17099.631371 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16247.636442 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16247.636442 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15289.351494 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15289.351494 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22624.290884 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22624.290884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 716044 # number of writebacks +system.cpu0.dcache.writebacks::total 716044 # number of writebacks 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# number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6193589500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6193589500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1698431500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1698431500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 100630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 460892000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 460892000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 637500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 637500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11458801500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11458801500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13157233000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13157233000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4606601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4606601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4606601500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4606601500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024186 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024186 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023250 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023250 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224068 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224068 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016398 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016398 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053440 # mshr miss rate for StoreCondReq accesses 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16599.537716 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16599.537716 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15879.753827 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15879.753827 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22602.716885 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22602.716885 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14682.762598 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14682.762598 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14877.665365 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14877.665365 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223520.996860 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223520.996860 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115438.749398 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115438.749398 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1970602 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.774874 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36833218 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1971114 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.686498 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6638665000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774874 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15926.416015 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15926.416015 # average overall mshr miss latency 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+system.cpu0.icache.tags.total_refs 36750687 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1964588 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.706562 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6697445000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773099 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999557 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999557 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79579816 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79579816 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36833218 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36833218 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36833218 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36833218 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36833218 # number of overall hits -system.cpu0.icache.overall_hits::total 36833218 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1971127 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1971127 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1971127 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1971127 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1971127 # number of overall misses -system.cpu0.icache.overall_misses::total 1971127 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19380486500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 19380486500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 19380486500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 19380486500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 19380486500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 19380486500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38804345 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38804345 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38804345 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38804345 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38804345 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38804345 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050797 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050797 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050797 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050797 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050797 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050797 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9832.185597 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9832.185597 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9832.185597 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9832.185597 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9832.185597 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9832.185597 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79395176 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79395176 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 36750687 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36750687 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36750687 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36750687 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36750687 # number of overall hits +system.cpu0.icache.overall_hits::total 36750687 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1964601 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1964601 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1964601 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1964601 # number of demand (read+write) misses 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297666000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4441867000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4739533000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4441867000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4739533000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.011874 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027933 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.012902 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999951 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999951 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163902 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163902 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046599 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046599 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.226148 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.226148 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.011434 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032736 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046599 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.204489 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088642 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.011434 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032736 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046599 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.204489 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158868 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158868 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046702 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046702 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.225562 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.225562 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.011874 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027933 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046702 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.202322 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088262 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.011874 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027933 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046702 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.202322 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181851 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27466.938406 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54426.267559 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17296.446835 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17296.446835 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15079.795510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15079.795510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 515999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 515999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39199.922757 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39199.922757 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38321.366749 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24124.678165 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24124.678165 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28328.993195 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31984.995219 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28328.993195 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43487.383325 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215516.311813 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196580.794730 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111304.682156 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109162.185148 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5528539 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2785631 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 220679 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216467 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 119671 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2643248 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 716138 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2204203 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 105351 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 312801 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88645 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43001 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114336 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 287716 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284337 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1971127 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603215 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3113 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5919751 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2595390 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13207 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168847 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8697195 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 252491264 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99508828 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22116 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 322908 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 352345116 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 940127 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 19140516 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3787201 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.076346 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.269706 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181890 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38435.364728 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63655.903730 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17349.847789 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17349.847789 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15060.200981 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15060.200981 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 499499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 499499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50864.680672 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.680672 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43407.069133 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26866.440514 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26866.440514 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37131.537597 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50784.937791 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215865.626671 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198689.234510 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111473.059452 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109904.763009 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5514708 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2778846 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 220650 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216436 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4214 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 117829 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2634124 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 714129 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2198813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 105915 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 313152 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88836 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114292 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 287887 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284399 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1964601 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 602822 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3087 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5899831 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2594741 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13052 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164810 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8672434 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251644992 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99451448 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21480 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314292 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 351432212 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 940964 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 19090924 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3779220 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.076318 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.269673 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3502276 92.48% 92.48% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 280713 7.41% 99.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4212 0.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3495013 92.48% 92.48% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 279993 7.41% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4214 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3787201 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5519275492 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3779220 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5504902494 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116183079 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115882925 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2962129461 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2952081467 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1227256511 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1226789533 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7683988 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7686990 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 88134970 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 86252968 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19426531 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6224342 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 651829 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 10038478 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3634441 # Number of BTB hits +system.cpu1.branchPred.lookups 19393527 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6185527 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 769783 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9956759 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3606289 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.205100 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8674574 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 447731 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3678807 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 3614078 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 64729 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 23620 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 36.219507 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8702764 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 566393 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3646067 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3582470 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 63597 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 23601 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1365,66 +1375,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 27735 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 27735 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 21301 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6434 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 27735 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 27735 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 27735 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2744 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12429.118076 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11482.413236 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6276.586572 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 644 23.47% 23.47% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1820 66.33% 89.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 198 7.22% 97.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 63 2.30% 99.31% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 9 0.33% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.04% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2744 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1939283032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1939283032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1939283032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2036 74.20% 74.20% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 708 25.80% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2744 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 27735 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 26638 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26638 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20208 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6430 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26638 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26638 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26638 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12533.532042 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11490.379150 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8690.810286 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 2656 98.96% 98.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26 0.97% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1849661032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1849661032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1849661032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1998 74.44% 74.44% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 686 25.56% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2684 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26638 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 27735 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2744 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26638 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2684 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2744 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 30479 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 29322 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11374009 # DTB read hits -system.cpu1.dtb.read_misses 25676 # DTB read misses -system.cpu1.dtb.write_hits 7084428 # DTB write hits -system.cpu1.dtb.write_misses 2059 # DTB write misses +system.cpu1.dtb.read_hits 11320530 # DTB read hits +system.cpu1.dtb.read_misses 24586 # DTB read misses +system.cpu1.dtb.write_hits 7061626 # DTB write hits +system.cpu1.dtb.write_misses 2052 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 434 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1992 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 262 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11399685 # DTB read accesses -system.cpu1.dtb.write_accesses 7086487 # DTB write accesses +system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11345116 # DTB read accesses +system.cpu1.dtb.write_accesses 7063678 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18458437 # DTB hits -system.cpu1.dtb.misses 27735 # DTB misses -system.cpu1.dtb.accesses 18486172 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 18382156 # DTB hits +system.cpu1.dtb.misses 26638 # DTB misses +system.cpu1.dtb.accesses 18408794 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1454,46 +1456,45 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2480 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2480 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2499 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2499 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2300 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2480 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2480 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2480 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1130 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12659.734513 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11853.270475 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5315.711785 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 183 16.19% 16.19% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 614 54.34% 70.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 213 18.85% 89.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 45 3.98% 93.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 23 2.04% 95.40% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.48% 97.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 15 1.33% 99.20% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.35% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1130 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1939872532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1939872532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1939872532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 965 85.40% 85.40% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 165 14.60% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1130 # Table walker page sizes translated +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2319 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2499 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2499 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2499 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1128 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12699.024823 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11989.496313 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4984.320484 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 166 14.72% 14.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 634 56.21% 70.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 206 18.26% 89.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.34% 93.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 1.95% 95.48% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.48% 97.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.42% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1128 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1850303532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1850303532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1850303532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 963 85.37% 85.37% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 165 14.63% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1128 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2480 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2480 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2499 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2499 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1130 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1130 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3610 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39704875 # ITB inst hits -system.cpu1.itb.inst_misses 2480 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1128 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1128 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3627 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39699373 # ITB inst hits +system.cpu1.itb.inst_misses 2499 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1502,777 +1503,777 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1100 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1101 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1838 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39707355 # ITB inst accesses -system.cpu1.itb.hits 39704875 # DTB hits -system.cpu1.itb.misses 2480 # DTB misses -system.cpu1.itb.accesses 39707355 # DTB accesses -system.cpu1.numPwrStateTransitions 5533 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2767 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1008221990.514637 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25700822378.312321 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1966 71.05% 71.05% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 797 28.80% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 39701872 # ITB inst accesses +system.cpu1.itb.hits 39699373 # DTB hits +system.cpu1.itb.misses 2499 # DTB misses +system.cpu1.itb.accesses 39701872 # DTB accesses +system.cpu1.numPwrStateTransitions 5523 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2762 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1010212132.618392 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25718871891.755051 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1964 71.11% 71.11% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.75% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 949980874116 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2767 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 58422036246 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789750247754 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 116847616 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 949979704076 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2762 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 58720807708 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790205910292 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 117445100 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48452289 # Number of instructions committed -system.cpu1.committedOps 59283596 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5163197 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5578862239 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.411602 # CPI: cycles per instruction -system.cpu1.ipc 0.414662 # IPC: instructions per cycle +system.cpu1.committedInsts 48204911 # Number of instructions committed +system.cpu1.committedOps 58981541 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5132548 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2762 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5579768700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.436372 # CPI: cycles per instruction +system.cpu1.ipc 0.410446 # IPC: instructions per cycle system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 40834570 68.88% 68.88% # Class of committed instruction -system.cpu1.op_class_0::IntMult 45625 0.08% 68.96% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3333 0.01% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11200779 18.89% 87.86% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7199223 12.14% 100.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 40607989 68.85% 68.85% # Class of committed instruction +system.cpu1.op_class_0::IntMult 45709 0.08% 68.93% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3353 0.01% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::MemRead 11147247 18.90% 87.83% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 7177177 12.17% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 59283596 # Class of committed instruction +system.cpu1.op_class_0::total 58981541 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2767 # number of quiesce instructions executed -system.cpu1.tickCycles 94150450 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 22697166 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 195596 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.279573 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 18031187 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 195963 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 92.013222 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91237126000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.279573 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924374 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.924374 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36965565 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36965565 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 10998874 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10998874 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6796614 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6796614 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50142 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50142 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80008 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80008 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71567 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71567 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17795488 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17795488 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17845630 # number of overall hits -system.cpu1.dcache.overall_hits::total 17845630 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 148727 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 148727 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 145387 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 145387 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30687 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30687 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16966 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16966 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23611 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23611 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 294114 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 294114 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 324801 # number of overall misses -system.cpu1.dcache.overall_misses::total 324801 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2356620500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2356620500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3915884500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3915884500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322199000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 322199000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 556849500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 556849500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 389000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 389000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6272505000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6272505000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6272505000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6272505000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11147601 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11147601 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6942001 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6942001 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80829 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80829 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96974 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96974 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95178 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95178 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 18089602 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 18089602 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 18170431 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 18170431 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013342 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013342 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020943 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.020943 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379653 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379653 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174954 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174954 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248072 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248072 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016259 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.016259 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.017875 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.017875 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15845.276917 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15845.276917 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26934.213513 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26934.213513 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18990.864081 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18990.864081 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23584.325103 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23584.325103 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2762 # number of quiesce instructions executed +system.cpu1.tickCycles 94223774 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 23221326 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 197231 # number of replacements +system.cpu1.dcache.tags.tagsinuse 476.160023 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17961880 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 197583 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 90.908023 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91326739500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 476.160023 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.930000 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.930000 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36815018 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36815018 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 10942799 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10942799 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6773317 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6773317 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50710 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50710 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80304 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80304 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71747 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71747 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17716116 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17716116 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17766826 # number of overall hits +system.cpu1.dcache.overall_hits::total 17766826 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 150509 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 150509 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 145770 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 145770 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30651 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30651 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23697 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23697 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 296279 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 296279 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 326930 # number of overall misses +system.cpu1.dcache.overall_misses::total 326930 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2503108000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2503108000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4131089000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4131089000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325863000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 325863000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557327500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 557327500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 612000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 612000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6634197000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6634197000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6634197000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6634197000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11093308 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11093308 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6919087 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6919087 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81361 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 81361 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97264 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97264 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95444 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95444 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 18012395 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 18012395 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 18093756 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 18093756 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013568 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.013568 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021068 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.021068 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.376728 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.376728 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174371 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174371 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248282 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248282 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016449 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.016449 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018069 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.018069 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16630.952302 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16630.952302 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28339.774988 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28339.774988 # average WriteReq miss latency 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19311.840173 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22391.721992 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22391.721992 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20292.408161 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20292.408161 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 195596 # number of writebacks -system.cpu1.dcache.writebacks::total 195596 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5710 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 5710 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52879 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52879 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12082 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12082 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 58589 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 58589 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 58589 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 58589 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143017 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 143017 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92508 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92508 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29859 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29859 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23611 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23611 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 235525 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 235525 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265384 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265384 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14595 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14595 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11928 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11928 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26523 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26523 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2115141000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2115141000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2362860000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2362860000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 507235000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 507235000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82984000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82984000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533247500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533247500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 380000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 380000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4478001000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4478001000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4985236000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4985236000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2537758000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2537758000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2537758000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2537758000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012829 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012829 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013326 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013326 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369409 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369409 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050364 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050364 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248072 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248072 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013020 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013020 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014605 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14789.437619 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14789.437619 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25542.223375 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25542.223375 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16987.675408 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16987.675408 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16990.990991 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16990.990991 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22584.706281 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22584.706281 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 197231 # number of writebacks +system.cpu1.dcache.writebacks::total 197231 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5831 # number of ReadReq MSHR hits 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267197 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 267197 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14423 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14423 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11756 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11756 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26179 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2254716500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2254716500 # number of ReadReq MSHR miss cycles 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17325.149259 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17325.149259 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17691.812985 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17691.812985 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22519.496139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22519.496139 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19012.847893 # average overall mshr miss latency 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95705.357143 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95705.357143 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95705.357143 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199515 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199547 # number of prefetch candidates identified +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8340101000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8340101000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8340101000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8340101000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8340101000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8340101000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11130500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11130500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11130500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 11130500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023992 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023992 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.581531 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.581531 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.581531 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99379.464286 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99379.464286 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 201450 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 201482 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59237 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 51581 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14798.019682 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1058904 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 65844 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.082012 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 57990 # number of prefetches not generated due to page crossing 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-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 346.292455 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.879481 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002576 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.021136 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.903199 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 289 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13932 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14396.977583 # Average occupied blocks per requestor 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id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13981 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 101 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 185 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1267 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7924 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4741 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017639 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850342 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 39538104 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 39538104 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30011 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3192 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 33203 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 117770 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 117770 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 1005566 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 1005566 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27881 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27881 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 913030 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 913030 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 102798 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 102798 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 30011 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3192 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 913030 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 130679 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1076912 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 30011 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3192 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 913030 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 130679 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1076912 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 718 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 296 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1014 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29883 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29883 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23611 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23611 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34746 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34746 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 35508 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 35508 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 74962 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 74962 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 718 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 296 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 35508 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 109708 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 146230 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 718 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 296 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 35508 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 109708 # number of overall misses -system.cpu1.l2cache.overall_misses::total 146230 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 16837500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6001500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 22839000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13404000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 13404000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 19834500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 19834500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 366500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 366500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1396405497 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1396405497 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1255643000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1255643000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1755754987 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1755754987 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 16837500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6001500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1255643000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3152160484 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4430642484 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 16837500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6001500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1255643000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3152160484 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4430642484 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 30729 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3488 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 34217 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117770 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 117770 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 1005566 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 1005566 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29883 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29883 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23611 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23611 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62627 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 62627 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 948538 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 948538 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 177760 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 177760 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 30729 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3488 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 948538 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 240387 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1223142 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 30729 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3488 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 948538 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 240387 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1223142 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023366 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.084862 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.029634 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 82 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 194 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1305 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7821 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4855 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017029 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002502 # Percentage of cache occupancy per task id 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# mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140483 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16536.633663 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37807.650847 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.853763 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.853763 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15022.489518 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15022.489518 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140779 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18685.467480 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37862.608886 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.782271 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15343.782271 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.003249 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.003249 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.242913 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33746.242913 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29370.675082 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17415.614768 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17415.614768 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22570.243538 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24182.610894 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22570.243538 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26237.654282 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165877.423775 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165282.110560 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91278.550692 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91263.525436 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2396557 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1207646 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20286 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 118595 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110586 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8009 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 53656 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1217922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11928 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11928 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 153983 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1025852 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 34704 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31184 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74094 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41981 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86038 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69927 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67092 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 948538 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295426 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 64 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2845326 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 911410 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8268 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64898 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3829902 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121387264 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30723028 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13952 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122916 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 152247160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 369470 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5053360 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1597738 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.098519 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.314386 # Request fanout histogram +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36706.222761 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36706.222761 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32360.255723 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19121.057698 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19121.057698 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.848939 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28209.001949 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164866.601955 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164300.343997 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90831.238779 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90833.574227 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2407842 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1213344 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20026 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 118526 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110630 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7896 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 52421 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1221670 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11756 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11756 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 155519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1031415 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 35412 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 31701 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 73485 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69767 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67286 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952438 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295145 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 55 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2857026 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915642 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8405 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62913 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3843986 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121886464 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30908928 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14348 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119380 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 152929120 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 368607 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5126040 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1602092 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.097939 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1448339 90.65% 90.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141390 8.85% 99.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8009 0.50% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1453081 90.70% 90.70% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 141115 8.81% 99.51% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 7896 0.49% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1597738 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2375408982 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1602092 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2385821492 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79990687 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79306117 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1423068313 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 409788212 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1428899351 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 412338887 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4783493 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4820495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 34178481 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33080974 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31003 # Transaction distribution -system.iobus.trans_dist::ReadResp 31003 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) @@ -2295,9 +2296,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -2318,34 +2319,34 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48331500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48391001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 620000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 47000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) @@ -2353,58 +2354,58 @@ system.iobus.reqLayer19.occupancy 2500 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6355500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6378000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 39060500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38950500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187669353 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187782564 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36449 # number of replacements -system.iocache.tags.tagsinuse 14.473969 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36461 # number of replacements +system.iocache.tags.tagsinuse 14.472132 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 271637878000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.473969 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904623 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904623 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272036828000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.472132 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses -system.iocache.demand_misses::total 36467 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36467 # number of overall misses -system.iocache.overall_misses::total 36467 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31680877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31680877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4302277476 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4302277476 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4333958353 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4333958353 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4333958353 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4333958353 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses +system.iocache.demand_misses::total 36479 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36479 # number of overall misses +system.iocache.overall_misses::total 36479 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 33219876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33219876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4376166688 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4376166688 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4409386564 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4409386564 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4409386564 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4409386564 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2413,38 +2414,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130373.979424 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130373.979424 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118768.702407 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118768.702407 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118846.034853 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118846.034853 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118846.034853 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118846.034853 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130274.023529 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130274.023529 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120808.488516 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120808.488516 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120874.655665 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120874.655665 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 4.166667 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19530877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19530877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2488777487 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2488777487 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2508308364 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2508308364 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2508308364 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2508308364 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20469876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20469876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2562591001 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2562591001 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2583060877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2583060877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2583060877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2583060877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2453,592 +2454,591 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80373.979424 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80373.979424 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68705.208895 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68705.208895 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68782.964434 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68782.964434 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68782.964434 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68782.964434 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 143192 # number of replacements -system.l2c.tags.tagsinuse 65154.235518 # Cycle average of tags in use -system.l2c.tags.total_refs 608270 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 208652 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.915237 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 94157771000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6329.103935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 78.467327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034862 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8953.646572 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6857.938638 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35058.708510 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.060603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2144.069552 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3463.562714 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2252.642806 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.096574 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001197 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80274.023529 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80274.023529 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70742.905284 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70742.905284 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70809.530881 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70809.530881 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70809.530881 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70809.530881 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 145308 # number of replacements +system.l2c.tags.tagsinuse 65153.014694 # Cycle average of tags in use +system.l2c.tags.total_refs 608197 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 210799 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.885199 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 94570968000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6725.818981 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 88.835717 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.039308 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8741.022578 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6775.934473 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34864.204134 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.618119 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2235.319135 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3466.513349 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2242.708901 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.102628 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001356 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.136622 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.104644 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.534953 # Average percentage of cache occupancy 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of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2118238500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6426386500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4071417000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7882500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2118238500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6426386500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 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+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.240730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.406886 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.454412 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23063.492063 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21418.454936 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22584.375000 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26563.380282 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24096.491228 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25464.843750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129705.383936 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85368.527390 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 110484.100845 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 109547.806974 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 151834.587045 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108593.359665 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197862.516402 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146895.873786 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167414.851769 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102176.249153 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80922.925581 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92583.220481 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 519453 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 291586 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38536 # Transaction distribution -system.membus.trans_dist::ReadResp 214874 # Transaction distribution -system.membus.trans_dist::WriteReq 31013 # Transaction distribution -system.membus.trans_dist::WriteResp 31013 # Transaction distribution -system.membus.trans_dist::WritebackDirty 140764 # Transaction distribution -system.membus.trans_dist::CleanEvict 19586 # Transaction distribution -system.membus.trans_dist::UpgradeReq 64644 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38971 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38386 # Transaction distribution +system.membus.trans_dist::ReadResp 216245 # Transaction distribution +system.membus.trans_dist::WriteReq 31026 # Transaction distribution +system.membus.trans_dist::WriteResp 31026 # Transaction distribution +system.membus.trans_dist::WritebackDirty 141787 # Transaction distribution +system.membus.trans_dist::CleanEvict 20009 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64008 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38952 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 40377 # Transaction distribution -system.membus.trans_dist::ReadExResp 19925 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 176338 # Transaction distribution +system.membus.trans_dist::ReadExReq 40468 # Transaction distribution +system.membus.trans_dist::ReadExResp 19978 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 177859 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656690 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 778768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 851699 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14184 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 855389 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19461788 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19654168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19616228 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19808736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21972312 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123613 # Total snoops (count) -system.membus.snoopTraffic 36288 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 426105 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011500 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.106618 # Request fanout histogram +system.membus.pkt_size::total 22126880 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123082 # Total snoops (count) +system.membus.snoopTraffic 37120 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 426925 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011573 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106956 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421205 98.85% 98.85% # Request fanout histogram -system.membus.snoop_fanout::1 4900 1.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 421984 98.84% 98.84% # Request fanout histogram +system.membus.snoop_fanout::1 4941 1.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426105 # Request fanout histogram -system.membus.reqLayer0.occupancy 95080500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 426925 # Request fanout histogram +system.membus.reqLayer0.occupancy 95052999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12459499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12480499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1008366249 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1015492813 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1144784655 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1151697269 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1337127 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1408128 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3070,77 +3070,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1122676 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 592030 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 210689 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 28909 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 27742 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1167 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38539 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 569123 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31013 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31013 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 372658 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 153621 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 113203 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44029 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 157232 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51954 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51954 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 530586 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4329 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1344687 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 405982 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1750669 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38363344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7028808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45392152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 398871 # Total snoops (count) -system.toL2Bus.snoopTraffic 16195724 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 956902 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.408687 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.494066 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1122951 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 592347 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 209143 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 29689 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 28433 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1256 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38389 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 568851 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31026 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31026 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 374622 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 155080 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 112572 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44056 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 156628 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51647 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51647 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 530464 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4356 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1342563 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408877 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1751440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38341228 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7151796 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45493024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 399228 # Total snoops (count) +system.toL2Bus.snoopTraffic 16183244 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 957878 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.406657 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.493872 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 566996 59.25% 59.25% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 388739 40.62% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1167 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 569606 59.47% 59.47% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 387016 40.40% 99.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1256 0.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 956902 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 952868265 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 957878 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 953761642 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 724877328 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 722683237 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 285789223 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 286574903 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini index f97cdd248..6291ea543 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -208,7 +208,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -688,7 +688,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -748,7 +748,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -820,7 +820,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -937,7 +937,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -982,7 +982,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -994,7 +994,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1026,29 +1026,36 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1068,6 +1075,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1077,7 +1085,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1099,9 +1107,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1454,7 +1462,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1771,6 +1779,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1778,7 +1787,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2009,6 +2018,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2016,7 +2026,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout index 6bd9bc23a..f91395bf5 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:21 -gem5 executing on e108600-lin, pid 23070 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:53:08 +gem5 executing on e108600-lin, pid 17485 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2858997339500 because m5_exit instruction encountered +Exiting @ tick 2854925996500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 4972770ec..f3f991d90 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.853344 # Number of seconds simulated -sim_ticks 2853343899500 # Number of ticks simulated -final_tick 2853343899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.854926 # Number of seconds simulated +sim_ticks 2854925996500 # Number of ticks simulated +final_tick 2854925996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139312 # Simulator instruction rate (inst/s) -host_op_rate 168444 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3544495637 # Simulator tick rate (ticks/s) -host_mem_usage 589148 # Number of bytes of host memory used -host_seconds 805.01 # Real time elapsed on the host -sim_insts 112146750 # Number of instructions simulated -sim_ops 135598813 # Number of ops (including micro ops) simulated +host_inst_rate 115917 # Simulator instruction rate (inst/s) +host_op_rate 140154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2954234125 # Simulator tick rate (ticks/s) +host_mem_usage 584856 # Number of bytes of host memory used +host_seconds 966.38 # Real time elapsed on the host +sim_insts 112020669 # Number of instructions simulated +sim_ops 135443008 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1675712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9177004 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 7040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1667200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9190572 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10861420 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1675712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1675712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7976832 # Number of bytes written to this memory +system.physmem.bytes_read::total 10865900 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1667200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1667200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7979712 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7994356 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26183 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143912 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7997236 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 110 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144124 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170231 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124638 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170301 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124683 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129019 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 587280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3216228 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129064 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 583973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3219198 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3806558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 587280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 587280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2795608 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6142 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2801750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2795608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 587280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3222369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3806018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 583973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 583973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2795068 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2801206 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2795068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 583973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3225336 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6608308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170231 # Number of read requests accepted -system.physmem.writeReqs 129019 # Number of write requests accepted -system.physmem.readBursts 170231 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129019 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10886144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue -system.physmem.bytesWritten 8006976 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10861420 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7994356 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6607224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170301 # Number of read requests accepted +system.physmem.writeReqs 129064 # Number of write requests accepted +system.physmem.readBursts 170301 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129064 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10890496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 8010048 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10865900 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7997236 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10508 # Per bank write bursts -system.physmem.perBankRdBursts::1 10518 # Per bank write bursts -system.physmem.perBankRdBursts::2 10699 # Per bank write bursts -system.physmem.perBankRdBursts::3 10590 # Per bank write bursts -system.physmem.perBankRdBursts::4 13367 # Per bank write bursts -system.physmem.perBankRdBursts::5 10649 # Per bank write bursts -system.physmem.perBankRdBursts::6 10947 # Per bank write bursts -system.physmem.perBankRdBursts::7 11320 # Per bank write bursts -system.physmem.perBankRdBursts::8 10289 # Per bank write bursts -system.physmem.perBankRdBursts::9 10353 # Per bank write bursts -system.physmem.perBankRdBursts::10 10214 # Per bank write bursts -system.physmem.perBankRdBursts::11 9210 # Per bank write bursts -system.physmem.perBankRdBursts::12 10497 # Per bank write bursts -system.physmem.perBankRdBursts::13 11112 # Per bank write bursts -system.physmem.perBankRdBursts::14 10041 # Per bank write bursts -system.physmem.perBankRdBursts::15 9782 # Per bank write bursts -system.physmem.perBankWrBursts::0 7781 # Per bank write bursts -system.physmem.perBankWrBursts::1 7920 # Per bank write bursts -system.physmem.perBankWrBursts::2 8383 # Per bank write bursts -system.physmem.perBankWrBursts::3 8149 # Per bank write bursts -system.physmem.perBankWrBursts::4 7457 # Per bank write bursts -system.physmem.perBankWrBursts::5 7755 # Per bank write bursts -system.physmem.perBankWrBursts::6 7974 # Per bank write bursts -system.physmem.perBankWrBursts::7 8419 # Per bank write bursts -system.physmem.perBankWrBursts::8 7882 # Per bank write bursts -system.physmem.perBankWrBursts::9 7909 # Per bank write bursts -system.physmem.perBankWrBursts::10 7627 # Per bank write bursts -system.physmem.perBankWrBursts::11 7117 # Per bank write bursts -system.physmem.perBankWrBursts::12 7926 # Per bank write bursts -system.physmem.perBankWrBursts::13 8274 # Per bank write bursts -system.physmem.perBankWrBursts::14 7391 # Per bank write bursts -system.physmem.perBankWrBursts::15 7145 # Per bank write bursts +system.physmem.perBankRdBursts::0 10638 # Per bank write bursts +system.physmem.perBankRdBursts::1 10529 # Per bank write bursts +system.physmem.perBankRdBursts::2 10665 # Per bank write bursts +system.physmem.perBankRdBursts::3 10242 # Per bank write bursts +system.physmem.perBankRdBursts::4 13390 # Per bank write bursts +system.physmem.perBankRdBursts::5 10196 # Per bank write bursts +system.physmem.perBankRdBursts::6 10392 # Per bank write bursts +system.physmem.perBankRdBursts::7 10920 # Per bank write bursts +system.physmem.perBankRdBursts::8 10199 # Per bank write bursts +system.physmem.perBankRdBursts::9 10416 # Per bank write bursts +system.physmem.perBankRdBursts::10 10277 # Per bank write bursts +system.physmem.perBankRdBursts::11 9652 # Per bank write bursts +system.physmem.perBankRdBursts::12 10777 # Per bank write bursts +system.physmem.perBankRdBursts::13 11476 # Per bank write bursts +system.physmem.perBankRdBursts::14 10256 # Per bank write bursts +system.physmem.perBankRdBursts::15 10139 # Per bank write bursts +system.physmem.perBankWrBursts::0 7926 # Per bank write bursts +system.physmem.perBankWrBursts::1 7916 # Per bank write bursts +system.physmem.perBankWrBursts::2 8341 # Per bank write bursts +system.physmem.perBankWrBursts::3 7830 # Per bank write bursts +system.physmem.perBankWrBursts::4 7635 # Per bank write bursts +system.physmem.perBankWrBursts::5 7427 # Per bank write bursts +system.physmem.perBankWrBursts::6 7524 # Per bank write bursts +system.physmem.perBankWrBursts::7 8090 # Per bank write bursts +system.physmem.perBankWrBursts::8 7812 # Per bank write bursts +system.physmem.perBankWrBursts::9 7846 # Per bank write bursts +system.physmem.perBankWrBursts::10 7622 # Per bank write bursts +system.physmem.perBankWrBursts::11 7450 # Per bank write bursts +system.physmem.perBankWrBursts::12 8154 # Per bank write bursts +system.physmem.perBankWrBursts::13 8593 # Per bank write bursts +system.physmem.perBankWrBursts::14 7575 # Per bank write bursts +system.physmem.perBankWrBursts::15 7416 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2853343449000 # Total gap between requests +system.physmem.numWrRetry 56 # Number of times write queue was full causing retry +system.physmem.totGap 2854925546000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169674 # Read request sizes (log2) +system.physmem.readPktSize::6 169744 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124638 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 162184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124683 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 160221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9636 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -160,120 +160,124 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.085896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.679507 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.366687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22012 36.36% 36.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14640 24.18% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6552 10.82% 71.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3435 5.67% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2639 4.36% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1745 2.88% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1057 1.75% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1062 1.75% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7396 12.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60538 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.253805 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 580.495916 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6239 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5947 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::30 6851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 138 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.849340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.889118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.883375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21657 35.85% 35.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14616 24.19% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6864 11.36% 71.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3516 5.82% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2636 4.36% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1611 2.67% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1067 1.77% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 953 1.58% 87.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7494 12.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60414 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.463041 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 582.417033 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6195 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.046307 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.379346 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.281323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5473 87.69% 87.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 55 0.88% 88.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 66 1.06% 89.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 37 0.59% 90.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 284 4.55% 94.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 48 0.77% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.27% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.18% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.14% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.10% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.21% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 157 2.52% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.08% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 5 0.08% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.13% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.24% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads -system.physmem.totQLat 1691091750 # Total ticks spent queuing -system.physmem.totMemAccLat 4880391750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 850480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9941.98 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.199645 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.300177 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.412164 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5485 88.52% 88.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 67 1.08% 89.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 0.69% 90.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 35 0.56% 90.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 272 4.39% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 29 0.47% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 8 0.13% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.18% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.18% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.05% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 138 2.23% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 7 0.11% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.10% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 13 0.21% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.19% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.10% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.06% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads +system.physmem.totQLat 4595967000 # Total ticks spent queuing +system.physmem.totMemAccLat 7786542000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27009.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28691.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 45759.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s @@ -282,42 +286,52 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.93 # Average write queue length when enqueuing -system.physmem.readRowHits 140142 # Number of row buffer hits during reads -system.physmem.writeRowHits 94524 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.54 # Row buffer hit rate for writes -system.physmem.avgGap 9534982.29 # Average gap between requests -system.physmem.pageHitRate 79.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 235894680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128712375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 691064400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 413670240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186366389040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83561921055 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638705050250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1910102702040 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.426569 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725994839000 # Time in different power states -system.physmem_0.memoryStateTime::REF 95279340000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32067469750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 221772600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121006875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 635676600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 397036080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186366389040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82367679285 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639752630750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909862191230 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.342278 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727746913750 # Time in different power states -system.physmem_1.memoryStateTime::REF 95279340000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30317548250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing +system.physmem.readRowHits 140583 # Number of row buffer hits during reads +system.physmem.writeRowHits 94323 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.35 # Row buffer hit rate for writes +system.physmem.avgGap 9536604.30 # Average gap between requests +system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 218405460 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 116085255 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 620980080 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 327236580 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6016710960.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4587085260 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 376629120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12457025670 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8414413920 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 671932680540 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 705069857835 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.966071 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2843548486750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 708499000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2558586000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2794649429000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21912527500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7778804250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 27318150750 # Time in different power states +system.physmem_1.actEnergy 212957640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 113185875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 593990880 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 326082960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6113824080.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4455367380 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 374460480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 12365716800 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8661645120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 671979444945 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 705199696980 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.011550 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2844173514000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 705782750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2600572000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2794499397250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22556418250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7446062750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 27117763500 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory @@ -330,30 +344,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 179 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31062999 # Number of BP lookups -system.cpu.branchPred.condPredicted 16869066 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2486744 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18728785 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10415318 # Number of BTB hits +system.cpu.branchPred.lookups 31074836 # Number of BP lookups +system.cpu.branchPred.condPredicted 16867509 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2481345 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18655029 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10408802 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.611285 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7833584 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1520957 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3075291 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2886933 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 188358 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 109527 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 55.796225 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7856601 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1514233 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3068747 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2872226 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 196521 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 109392 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,59 +397,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 68003 # Table walker walks requested -system.cpu.dtb.walker.walksShort 68003 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44606 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23397 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 68003 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 68003 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 68003 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7897 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10035.266557 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8419.099443 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6813.200210 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 7021 88.91% 88.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 869 11.00% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7897 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 271390000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 271390000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 271390000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6503 82.35% 82.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1394 17.65% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7897 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 68003 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 68070 # Table walker walks requested +system.cpu.dtb.walker.walksShort 68070 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44787 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23283 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 68070 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 68070 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 68070 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7877 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10134.378571 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8445.879455 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 9567.630419 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 7869 99.90% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7877 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 276581000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 276581000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6513 82.68% 82.68% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1364 17.32% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7877 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 68070 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 68003 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7897 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 68070 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7877 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7897 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 75900 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7877 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 75947 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24771188 # DTB read hits -system.cpu.dtb.read_misses 61134 # DTB read misses -system.cpu.dtb.write_hits 19449290 # DTB write hits -system.cpu.dtb.write_misses 6869 # DTB write misses +system.cpu.dtb.read_hits 24743648 # DTB read hits +system.cpu.dtb.read_misses 61017 # DTB read misses +system.cpu.dtb.write_hits 19435570 # DTB write hits +system.cpu.dtb.write_misses 7053 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4279 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1418 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 770 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24832322 # DTB read accesses -system.cpu.dtb.write_accesses 19456159 # DTB write accesses +system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24804665 # DTB read accesses +system.cpu.dtb.write_accesses 19442623 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44220478 # DTB hits -system.cpu.dtb.misses 68003 # DTB misses -system.cpu.dtb.accesses 44288481 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44179218 # DTB hits +system.cpu.dtb.misses 68070 # DTB misses +system.cpu.dtb.accesses 44247288 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,39 +478,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 5856 # Table walker walks requested -system.cpu.itb.walker.walksShort 5856 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5531 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5856 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5856 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5856 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3193 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10411.838396 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8598.635311 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 6896.589649 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1843 57.72% 57.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 807 25.27% 82.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 535 16.76% 99.75% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 7 0.22% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3193 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 270980500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 270980500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 270980500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2883 90.29% 90.29% # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 5855 # Table walker walks requested +system.cpu.itb.walker.walksShort 5855 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 322 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5533 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5855 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5855 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5855 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3194 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10424.389480 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8603.860466 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 6932.586443 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1846 57.80% 57.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 798 24.98% 82.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 544 17.03% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 5 0.16% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3194 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 276141500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 276141500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2884 90.29% 90.29% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3193 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3194 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5856 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5856 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5855 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5855 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3193 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3193 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3194 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3194 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 9049 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57483193 # ITB inst hits -system.cpu.itb.inst_misses 5856 # ITB inst misses +system.cpu.itb.inst_hits 57481594 # ITB inst hits +system.cpu.itb.inst_misses 5855 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -506,45 +519,45 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2912 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2915 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8279 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8308 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57489049 # ITB inst accesses -system.cpu.itb.hits 57483193 # DTB hits -system.cpu.itb.misses 5856 # DTB misses -system.cpu.itb.accesses 57489049 # DTB accesses +system.cpu.itb.inst_accesses 57487449 # ITB inst accesses +system.cpu.itb.hits 57481594 # DTB hits +system.cpu.itb.misses 5855 # DTB misses +system.cpu.itb.accesses 57487449 # DTB accesses system.cpu.numPwrStateTransitions 6066 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 888351102.639301 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17445509399.919735 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887934091.386746 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17437787888.707882 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499967553028 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499966196768 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 158975005195 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2694368894305 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 317952965 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 161821897324 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2693104099176 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 323646748 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112146750 # Number of instructions committed -system.cpu.committedOps 135598813 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7821624 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112020669 # Number of instructions committed +system.cpu.committedOps 135443008 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7814596 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5388799101 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.835151 # CPI: cycles per instruction -system.cpu.ipc 0.352715 # IPC: instructions per cycle +system.cpu.quiesceCycles 5386269471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.889170 # CPI: cycles per instruction +system.cpu.ipc 0.346120 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 90918529 67.05% 67.05% # Class of committed instruction -system.cpu.op_class_0::IntMult 113133 0.08% 67.13% # Class of committed instruction +system.cpu.op_class_0::IntAlu 90804901 67.04% 67.04% # Class of committed instruction +system.cpu.op_class_0::IntMult 113201 0.08% 67.13% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction @@ -568,663 +581,663 @@ system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Cl system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 8487 0.01% 67.14% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.14% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.14% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.14% # Class of committed instruction -system.cpu.op_class_0::MemRead 24279497 17.91% 85.05% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20276830 14.95% 100.00% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 8481 0.01% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::MemRead 24250620 17.90% 85.04% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20263468 14.96% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 135598813 # Class of committed instruction +system.cpu.op_class_0::total 135443008 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.tickCycles 217828985 # Number of cycles that the object actually ticked -system.cpu.idleCycles 100123980 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 845168 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.946266 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42678256 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 845680 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.466200 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 322165500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.946266 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999895 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999895 # Average percentage of cache occupancy +system.cpu.tickCycles 217947056 # Number of cycles that the object actually ticked +system.cpu.idleCycles 105699692 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 844723 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.945160 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637807 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 845235 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.444914 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 330588500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.945160 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999893 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176368054 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176368054 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23126363 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23126363 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18288488 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18288488 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 357151 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 357151 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443374 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443374 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 459996 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 459996 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41414851 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41414851 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41772002 # number of overall hits -system.cpu.dcache.overall_hits::total 41772002 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 466466 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 466466 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 547177 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 547177 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 169147 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 169147 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22423 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22423 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176206878 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176206878 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23101260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23101260 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18273431 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18273431 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356861 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356861 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443340 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443340 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460050 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460050 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41374691 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41374691 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41731552 # number of overall hits +system.cpu.dcache.overall_hits::total 41731552 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 465078 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 465078 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 548776 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 548776 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169103 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169103 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22503 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22503 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1013643 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1013643 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1182790 # number of overall misses -system.cpu.dcache.overall_misses::total 1182790 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6859105500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6859105500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23368526480 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23368526480 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 290513500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 290513500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 169000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 169000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30227631980 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30227631980 # number of demand (read+write) miss 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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12956.049592 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 84500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 84500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29820.786983 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29820.786983 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25556.211990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25556.211990 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.023918 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023918 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 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# average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33742.081680 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28918.671160 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28918.671160 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 224 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 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of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1605906500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1605906500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 111255000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 111255000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 167000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18477053500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18477053500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20082960000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20082960000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6301797000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6301797000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6301797000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6301797000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017838 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017838 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015838 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015838 # mshr miss rate for WriteReq accesses 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number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 121747500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 121747500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20751294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20751294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22404460500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22404460500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305636000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305636000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017798 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017798 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230337 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230337 # mshr miss rate for SoftPFReq accesses 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41808.960667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41808.960667 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.419125 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.419125 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13359.149856 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13359.149856 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 83500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 83500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25692.084519 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25692.084519 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23902.964459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23902.964459 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202447.860447 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.860447 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107335.882543 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107335.882543 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2889133 # number of replacements -system.cpu.icache.tags.tagsinuse 511.392140 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54584955 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2889645 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.889848 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15688442500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.392140 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998813 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998813 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016955 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016955 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 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Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 54584955 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54584955 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54584955 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54584955 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54584955 # number of overall hits -system.cpu.icache.overall_hits::total 54584955 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2889657 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2889657 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2889657 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2889657 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2889657 # number of overall misses -system.cpu.icache.overall_misses::total 2889657 # number of overall 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latency -system.cpu.icache.demand_avg_miss_latency::total 13581.409316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13581.409316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13581.409316 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60365128 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60365128 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 54580851 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54580851 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54580851 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54580851 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54580851 # number of overall hits +system.cpu.icache.overall_hits::total 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36355958500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 258265000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 258265000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 258265000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 258265000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050277 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050277 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for overall accesses 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+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 146000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10769142500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10769142500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2149471500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2149471500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1592398000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1592398000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34653500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2149471500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12361540500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14545838500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34653500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2149471500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12361540500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14545838500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916431500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6133251000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916431500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6133251000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001558 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002151 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437328 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437328 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007934 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026388 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026388 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169986 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.043821 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169986 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.043821 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75723.140496 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69230.609718 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69230.609718 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70851.594190 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70851.594190 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74260.848602 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74260.848602 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70851.594190 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69738.609330 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69895.927005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70851.594190 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69738.609330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69895.927005 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63513.774105 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189945.451041 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 177936.371566 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63513.774105 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100707.226925 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98746.676240 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 7504035 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768706 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58030 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 170 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 170 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437730 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437730 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007933 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025878 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025878 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.043847 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.043847 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 310950.892857 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82987.658745 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82987.658745 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93691.548252 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93691.548252 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112124.911984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112124.911984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190055.621587 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179078.250460 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100766.963586 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99190.577847 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 7507397 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770030 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58003 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 175 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 175 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 137182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3577165 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 788847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2889133 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 153180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2809 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 136990 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3578080 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 790742 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2891615 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2790 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295522 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295522 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889657 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 550405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2792 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2892139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 549026 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 4412 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8674948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2659767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159313 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11508730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370049536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99142941 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 271652 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 469477389 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133226 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5798108 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 4004431 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.022424 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.148057 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8682092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2658406 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14762 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11515114 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370357376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99233193 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 274004 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 469878069 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132782 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5798856 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 4006498 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.022233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.147442 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3914637 97.76% 97.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 89794 2.24% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3917420 97.78% 97.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 89078 2.22% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4004431 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7421943500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4006498 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7428208500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 275377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 281377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4339894977 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4343459350 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1315039189 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1314433554 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 11390493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 11390994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 91431936 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 91384437 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1275,66 +1288,66 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46364500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46308000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 107000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 618000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 618500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6096500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6088500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 39117500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39091500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187733842 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187755828 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.032370 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.033906 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270830421000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.032370 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064523 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064523 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272036495000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.033906 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064619 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064619 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1343,14 +1356,14 @@ system.iocache.demand_misses::realview.ide 36458 # system.iocache.demand_misses::total 36458 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36458 # number of overall misses system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29494377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29494377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4278402465 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4278402465 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4307896842 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4307896842 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4307896842 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4307896842 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 37411877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 37411877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4363182951 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4363182951 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4400594828 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4400594828 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4400594828 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4400594828 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1367,14 +1380,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 126044.346154 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126044.346154 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118109.608685 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118109.608685 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118160.536563 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118160.536563 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118160.536563 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118160.536563 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 159879.816239 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 159879.816239 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120450.059381 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120450.059381 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120703.133140 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120703.133140 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1391,14 +1404,14 @@ system.iocache.demand_mshr_misses::realview.ide 36458 system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17794377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17794377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465093924 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2465093924 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2482888301 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2482888301 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2482888301 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2482888301 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 25711877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 25711877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2549871160 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2549871160 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2575583037 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2575583037 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2575583037 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2575583037 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1407,90 +1420,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76044.346154 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76044.346154 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68051.400287 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68051.400287 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68102.701766 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68102.701766 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68102.701766 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68102.701766 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 336558 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 137845 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109879.816239 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 109879.816239 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.761263 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.761263 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 337068 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 138136 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 489 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 34395 # Transaction distribution -system.membus.trans_dist::ReadResp 72195 # Transaction distribution -system.membus.trans_dist::WriteReq 27583 # Transaction distribution -system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124638 # Transaction distribution -system.membus.trans_dist::CleanEvict 8645 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 34249 # Transaction distribution +system.membus.trans_dist::ReadResp 71739 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124683 # Transaction distribution +system.membus.trans_dist::CleanEvict 8839 # Transaction distribution system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 129117 # Transaction distribution -system.membus.trans_dist::ReadExResp 129117 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37800 # Transaction distribution +system.membus.trans_dist::ReadExReq 129646 # Transaction distribution +system.membus.trans_dist::ReadExResp 129646 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37490 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554414 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 626925 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 627311 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16538656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16702429 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16546016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16709801 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19019549 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 504 # Total snoops (count) -system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 265249 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018541 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.134898 # Request fanout histogram +system.membus.pkt_size::total 19026921 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 505 # Total snoops (count) +system.membus.snoopTraffic 32192 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 265323 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018540 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134893 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 260331 98.15% 98.15% # Request fanout histogram -system.membus.snoop_fanout::1 4918 1.85% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 260404 98.15% 98.15% # Request fanout histogram +system.membus.snoop_fanout::1 4919 1.85% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 265249 # Request fanout histogram -system.membus.reqLayer0.occupancy 92904500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 265323 # Request fanout histogram +system.membus.reqLayer0.occupancy 92820000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1700500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 906764526 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 905922529 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 989491000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 989794500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1228623 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1230123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1522,28 +1535,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 567a187d7..18a433388 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -229,7 +229,7 @@ useIndirect=true [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ pipelined=true [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -723,7 +723,7 @@ port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -948,7 +948,7 @@ useIndirect=true [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1310,7 +1310,7 @@ pipelined=true [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1442,7 +1442,7 @@ port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -1589,7 +1589,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -1635,7 +1635,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1733,27 +1733,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1773,6 +1773,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1782,7 +1783,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1804,9 +1805,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -2159,7 +2160,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -2476,6 +2477,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2483,7 +2485,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2714,6 +2716,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2721,7 +2724,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 8041988f0..716e8ee64 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -35,7 +35,6 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] warn: allocating bonus target for snoop -warn: allocating bonus target for snoop warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr @@ -46,3 +45,4 @@ warn: Ignoring write to miscreg pmintenclr warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmcr warn: instruction 'mcr dcisw' unimplemented +warn: CP14 unimplemented crn[3], opc1[5], crm[8], opc2[0] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index e697726d2..78776277c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:31:02 -gem5 executing on e108600-lin, pid 12561 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:00:48 +gem5 executing on e108600-lin, pid 17551 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2825947406000 because m5_exit instruction encountered +Exiting @ tick 2826594924500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index ab0dc0047..a281a2cd6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.826111 # Number of seconds simulated -sim_ticks 2826111083000 # Number of ticks simulated -final_tick 2826111083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826595 # Number of seconds simulated +sim_ticks 2826594924500 # Number of ticks simulated +final_tick 2826594924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93135 # Simulator instruction rate (inst/s) -host_op_rate 112984 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2190118612 # Simulator tick rate (ticks/s) -host_mem_usage 627176 # Number of bytes of host memory used -host_seconds 1290.39 # Real time elapsed on the host -sim_insts 120180681 # Number of instructions simulated -sim_ops 145794019 # Number of ops (including micro ops) simulated +host_inst_rate 79087 # Simulator instruction rate (inst/s) +host_op_rate 95944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1861516367 # Simulator tick rate (ticks/s) +host_mem_usage 623016 # Number of bytes of host memory used +host_seconds 1518.44 # Real time elapsed on the host +sim_insts 120088860 # Number of instructions simulated +sim_ops 145685275 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 1920 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1301824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1315176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8404800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1324752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1304168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8428096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 186528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 599252 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 416192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 175008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 586900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 427200 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12227420 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1301824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 186528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1488352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8794944 # Number of bytes written to this memory +system.physmem.bytes_read::total 12249452 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1324752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 175008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1499760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8803008 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8812508 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 30 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8820572 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22588 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22950 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2982 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9384 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9191 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6675 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193909 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 137421 # Number of write requests responded to by this memory +system.physmem.num_reads::total 194257 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137547 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141812 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 679 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 141938 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 460641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 465366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2973981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 468674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 461392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2981713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 66002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 212041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 147267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 61915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 207635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 151136 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4326589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 460641 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 66002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 526643 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3112031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4333643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 468674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 61915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 530589 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3114351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3118245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3112031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3120565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3114351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 460641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 471567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2973981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 468674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 467592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2981713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 66002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 212055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 147267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 61915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 207649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 151136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7444834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 193910 # Number of read requests accepted -system.physmem.writeReqs 141812 # Number of write requests accepted -system.physmem.readBursts 193910 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141812 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12399936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.physmem.bytesWritten 8824960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12227484 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8812508 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 7454207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 194258 # Number of read requests accepted +system.physmem.writeReqs 141938 # Number of write requests accepted +system.physmem.readBursts 194258 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141938 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12422976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 8833536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12249516 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8820572 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12140 # Per bank write bursts -system.physmem.perBankRdBursts::1 12135 # Per bank write bursts -system.physmem.perBankRdBursts::2 12398 # Per bank write bursts -system.physmem.perBankRdBursts::3 12886 # Per bank write bursts -system.physmem.perBankRdBursts::4 14558 # Per bank write bursts -system.physmem.perBankRdBursts::5 12353 # Per bank write bursts -system.physmem.perBankRdBursts::6 12494 # Per bank write bursts -system.physmem.perBankRdBursts::7 12590 # Per bank write bursts -system.physmem.perBankRdBursts::8 12207 # Per bank write bursts -system.physmem.perBankRdBursts::9 12490 # Per bank write bursts -system.physmem.perBankRdBursts::10 11644 # Per bank write bursts -system.physmem.perBankRdBursts::11 10772 # Per bank write bursts -system.physmem.perBankRdBursts::12 11273 # Per bank write bursts -system.physmem.perBankRdBursts::13 11534 # Per bank write bursts -system.physmem.perBankRdBursts::14 11359 # Per bank write bursts -system.physmem.perBankRdBursts::15 10916 # Per bank write bursts -system.physmem.perBankWrBursts::0 8885 # Per bank write bursts -system.physmem.perBankWrBursts::1 8987 # Per bank write bursts -system.physmem.perBankWrBursts::2 9257 # Per bank write bursts -system.physmem.perBankWrBursts::3 9509 # Per bank write bursts -system.physmem.perBankWrBursts::4 8433 # Per bank write bursts -system.physmem.perBankWrBursts::5 8902 # Per bank write bursts -system.physmem.perBankWrBursts::6 9078 # Per bank write bursts -system.physmem.perBankWrBursts::7 8908 # Per bank write bursts -system.physmem.perBankWrBursts::8 8674 # Per bank write bursts -system.physmem.perBankWrBursts::9 9007 # Per bank write bursts -system.physmem.perBankWrBursts::10 8474 # Per bank write bursts -system.physmem.perBankWrBursts::11 8031 # Per bank write bursts -system.physmem.perBankWrBursts::12 8318 # Per bank write bursts -system.physmem.perBankWrBursts::13 8000 # Per bank write bursts -system.physmem.perBankWrBursts::14 7983 # Per bank write bursts -system.physmem.perBankWrBursts::15 7444 # Per bank write bursts +system.physmem.perBankRdBursts::0 12130 # Per bank write bursts +system.physmem.perBankRdBursts::1 12140 # Per bank write bursts +system.physmem.perBankRdBursts::2 12480 # Per bank write bursts +system.physmem.perBankRdBursts::3 12151 # Per bank write bursts +system.physmem.perBankRdBursts::4 14882 # Per bank write bursts +system.physmem.perBankRdBursts::5 12677 # Per bank write bursts +system.physmem.perBankRdBursts::6 12709 # Per bank write bursts +system.physmem.perBankRdBursts::7 12606 # Per bank write bursts +system.physmem.perBankRdBursts::8 11844 # Per bank write bursts +system.physmem.perBankRdBursts::9 11522 # Per bank write bursts +system.physmem.perBankRdBursts::10 11334 # Per bank write bursts +system.physmem.perBankRdBursts::11 10175 # Per bank write bursts +system.physmem.perBankRdBursts::12 11497 # Per bank write bursts +system.physmem.perBankRdBursts::13 12486 # Per bank write bursts +system.physmem.perBankRdBursts::14 11961 # Per bank write bursts +system.physmem.perBankRdBursts::15 11515 # Per bank write bursts +system.physmem.perBankWrBursts::0 8842 # Per bank write bursts +system.physmem.perBankWrBursts::1 8923 # Per bank write bursts +system.physmem.perBankWrBursts::2 9151 # Per bank write bursts +system.physmem.perBankWrBursts::3 8834 # Per bank write bursts +system.physmem.perBankWrBursts::4 8743 # Per bank write bursts +system.physmem.perBankWrBursts::5 9257 # Per bank write bursts +system.physmem.perBankWrBursts::6 9174 # Per bank write bursts +system.physmem.perBankWrBursts::7 9022 # Per bank write bursts +system.physmem.perBankWrBursts::8 8380 # Per bank write bursts +system.physmem.perBankWrBursts::9 8199 # Per bank write bursts +system.physmem.perBankWrBursts::10 8228 # Per bank write bursts +system.physmem.perBankWrBursts::11 7543 # Per bank write bursts +system.physmem.perBankWrBursts::12 8493 # Per bank write bursts +system.physmem.perBankWrBursts::13 8795 # Per bank write bursts +system.physmem.perBankWrBursts::14 8486 # Per bank write bursts +system.physmem.perBankWrBursts::15 7954 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2826110796000 # Total gap between requests +system.physmem.numWrRetry 65 # Number of times write queue was full causing retry +system.physmem.totGap 2826594637500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 3086 # Read request sizes (log2) +system.physmem.readPktSize::4 3091 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190245 # Read request sizes (log2) +system.physmem.readPktSize::6 190588 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 137421 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 59620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 262 # What read queue length does an incoming req see +system.physmem.writePktSize::6 137547 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 58416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 270 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see @@ -189,162 +189,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 84734 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 250.487785 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.325533 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 306.970890 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42837 50.55% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17738 20.93% 71.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6168 7.28% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3519 4.15% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2713 3.20% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1549 1.83% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 945 1.12% 89.07% # Bytes accessed per row activation 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an incoming req see +system.physmem.wrQLenPdf::54 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 84597 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.267917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.709069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.432600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42654 50.42% 50.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17739 20.97% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6092 7.20% 78.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3470 4.10% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2903 3.43% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1534 1.81% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 962 1.14% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 998 1.18% 90.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8245 9.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84597 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6823 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.448923 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.375084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6821 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6846 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.141689 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.636499 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.164291 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5708 83.38% 83.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 378 5.52% 88.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 91 1.33% 90.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 47 0.69% 90.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 276 4.03% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 33 0.48% 95.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 21 0.31% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.34% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.28% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.15% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.03% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 166 2.42% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.13% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.16% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6846 # Writes before turning the bus around for reads -system.physmem.totQLat 6600075879 # Total ticks spent queuing -system.physmem.totMemAccLat 10232869629 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 968745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34065.08 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52815.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s +system.physmem.rdPerTurnAround::total 6823 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6823 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.229225 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.516304 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.191757 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5762 84.45% 84.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 386 5.66% 90.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 77 1.13% 91.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.64% 91.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 244 3.58% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 18 0.26% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.21% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.18% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.25% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.03% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.12% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 140 2.05% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.15% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.18% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.12% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.19% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6823 # Writes before turning the bus around for reads +system.physmem.totQLat 10063104165 # Total ticks spent queuing +system.physmem.totMemAccLat 13702647915 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 970545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51842.28 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 70592.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing -system.physmem.readRowHits 161373 # Number of row buffer hits during reads -system.physmem.writeRowHits 85531 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes -system.physmem.avgGap 8418008.94 # Average gap between requests -system.physmem.pageHitRate 74.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 338612400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 184758750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 792121200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 466294320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79311033765 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626092117250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891772383845 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.392029 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705053539598 # Time in different power states -system.physmem_0.memoryStateTime::REF 94369860000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 26681946652 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 301976640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 164769000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 719113200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 427232880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78534447525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626773333250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891508318655 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.298592 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2706191706230 # Time in different power states -system.physmem_1.memoryStateTime::REF 94369860000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 25549496770 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.32 # Average write queue length when enqueuing +system.physmem.readRowHits 161915 # Number of row buffer hits during reads +system.physmem.writeRowHits 85621 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.41 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.03 # Row buffer hit rate for writes +system.physmem.avgGap 8407579.62 # Average gap between requests +system.physmem.pageHitRate 74.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 318172680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169112790 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 726673500 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 375558120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4535428560.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4774700760 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 244257600 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 9148762200 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6477825120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 667571113185 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 694343780025 # Total energy per rank (pJ) +system.physmem_0.averagePower 245.646723 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2815396783365 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 428149701 # Time in different power states +system.physmem_0.memoryStateTime::REF 1926538000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2778550744250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16869300047 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8757031934 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 20063160568 # Time in different power states +system.physmem_1.actEnergy 285849900 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 151932825 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 659264760 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 344927160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4569848400.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4671042840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 250741920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8727797820 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6816319680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 667684488600 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 694164121065 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.583162 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2815694283339 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 440101951 # Time in different power states +system.physmem_1.memoryStateTime::REF 1941710000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2778803468000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17750764755 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8518829210 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 19140050584 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -363,30 +380,30 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 23913557 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15655751 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 926443 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14584665 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 9536401 # Number of BTB hits +system.cpu0.branchPred.lookups 53161527 # Number of BP lookups +system.cpu0.branchPred.condPredicted 24432585 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 935077 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32150468 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 13984916 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.386493 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3854213 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33180 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 1360238 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 1204672 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 155566 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 48773 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 43.498328 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15489494 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33173 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 10133739 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 9977658 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 156081 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 49006 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -416,84 +433,83 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 65918 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65918 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25327 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18922 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 21669 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44249 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 506.926710 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3129.335275 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 43005 97.19% 97.19% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 929 2.10% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.33% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 23 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 66483 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 66483 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25519 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19054 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 21910 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44573 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 499.046508 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3114.296115 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43354 97.27% 97.27% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 917 2.06% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 116 0.26% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 24 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44249 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 16055 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11307.848022 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9898.999015 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6813.334576 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 14595 90.91% 90.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1294 8.06% 98.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 134 0.83% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 9 0.06% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 17 0.11% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 16055 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 85920956152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.541941 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.508329 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 85862493152 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 40323000 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 8212500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 5190500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2626000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 886000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 336500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 44000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 85920956152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5102 78.63% 78.63% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1387 21.37% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6489 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65918 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 44573 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16394 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11498.017567 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9809.718618 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10152.442305 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14883 90.78% 90.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1339 8.17% 98.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 129 0.79% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 18 0.11% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.01% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 6 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::245760-262143 16 0.10% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 16394 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 86404933652 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.566419 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.506005 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 86345641152 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 41095500 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 8202000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4970000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2695000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 946000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 940000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 429500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 86404933652 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5203 78.33% 78.33% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1439 21.67% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6642 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66483 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65918 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6489 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66483 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6642 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6489 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 72407 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6642 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 73125 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17729387 # DTB read hits -system.cpu0.dtb.read_misses 55806 # DTB read misses -system.cpu0.dtb.write_hits 14606301 # DTB write hits -system.cpu0.dtb.write_misses 10112 # DTB write misses +system.cpu0.dtb.read_hits 23680324 # DTB read hits +system.cpu0.dtb.read_misses 56461 # DTB read misses +system.cpu0.dtb.write_hits 17598903 # DTB write hits +system.cpu0.dtb.write_misses 10022 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3431 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 353 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2188 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2246 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 939 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17785193 # DTB read accesses -system.cpu0.dtb.write_accesses 14616413 # DTB write accesses +system.cpu0.dtb.perms_faults 902 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23736785 # DTB read accesses +system.cpu0.dtb.write_accesses 17608925 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32335688 # DTB hits -system.cpu0.dtb.misses 65918 # DTB misses -system.cpu0.dtb.accesses 32401606 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 41279227 # DTB hits +system.cpu0.dtb.misses 66483 # DTB misses +system.cpu0.dtb.accesses 41345710 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -523,58 +539,58 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 10845 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10845 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3752 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6021 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1072 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 438.606364 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2276.348067 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9409 96.28% 96.28% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 121 1.24% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 47 0.48% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 16 0.16% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 6 0.06% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3657 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12272.627837 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11484.483595 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4878.254960 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 514 14.06% 14.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2884 78.86% 92.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 170 4.65% 97.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 55 1.50% 99.07% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 31 0.85% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3657 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 21495635712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.820169 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.384194 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3866725500 17.99% 17.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 17627832712 82.01% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 1008500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 69000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 21495635712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2254 87.20% 87.20% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 331 12.80% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2585 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 11041 # Table walker walks requested +system.cpu0.itb.walker.walksShort 11041 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4028 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5930 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1083 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9958 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 410.574413 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2129.037976 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9588 96.28% 96.28% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 186 1.87% 98.15% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 118 1.18% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.38% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 5 0.05% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9958 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3663 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12262.353262 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11250.035596 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5522.553888 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 663 18.10% 18.10% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2695 73.57% 91.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 173 4.72% 96.40% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 79 2.16% 98.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 3663 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 21980185712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.834654 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.371618 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3635314000 16.54% 16.54% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 18343952712 83.46% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 868500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 50500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 21980185712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2243 86.94% 86.94% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 337 13.06% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2580 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10845 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10845 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11041 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11041 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2585 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2585 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13430 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 37503849 # ITB inst hits -system.cpu0.itb.inst_misses 10845 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2580 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2580 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13621 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 72829698 # ITB inst hits +system.cpu0.itb.inst_misses 11041 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -583,1055 +599,1039 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2291 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1944 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1929 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37514694 # ITB inst accesses -system.cpu0.itb.hits 37503849 # DTB hits -system.cpu0.itb.misses 10845 # DTB misses -system.cpu0.itb.accesses 37514694 # DTB accesses -system.cpu0.numPwrStateTransitions 3712 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1856 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1487215700.959052 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23895599673.728432 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1080 58.19% 58.19% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 769 41.43% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 72840739 # ITB inst accesses +system.cpu0.itb.hits 72829698 # DTB hits +system.cpu0.itb.misses 11041 # DTB misses +system.cpu0.itb.accesses 72840739 # DTB accesses +system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1456796210.372727 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23672658216.113400 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1093 58.45% 58.45% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.28% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499971395296 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1856 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 65838742020 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2760272340980 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 131678547 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499970757520 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 102386011103 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724208913397 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 204773026 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19262499 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 112028029 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 23913557 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14595286 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 106047706 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2739238 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 149116 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 57008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 423158 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 407524 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 94244 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37503537 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 259263 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5228 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 127810874 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.056272 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.258048 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 20714269 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 196101622 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53161527 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39452068 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 175603283 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5698298 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 148281 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 57647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 420719 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 418648 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 100050 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 72829386 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 258768 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5384 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 200312046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.196487 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.307164 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 65678610 51.39% 51.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21331326 16.69% 68.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8731054 6.83% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 32069884 25.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 95293979 47.57% 47.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 30393228 15.17% 62.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14596992 7.29% 70.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 60027847 29.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 127810874 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.181606 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.850769 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19867897 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 60850603 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 41086114 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4967748 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1038512 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3035925 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 335186 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 110135169 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3776324 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1038512 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 25520251 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12577304 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 37369361 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40264186 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11041260 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 105172145 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1006076 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1476626 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 165177 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 58768 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6832387 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 109365921 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 480109573 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 120259513 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9447 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 98266494 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11099416 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1228555 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1085594 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12372656 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18663457 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 16076197 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1697816 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2228906 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 102290291 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1693186 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 100457201 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 451571 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9045594 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21384310 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 120136 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 127810874 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.785983 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.028831 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 200312046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.259612 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.957654 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 25714917 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108196913 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 58914772 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4966892 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2518552 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3065050 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 334861 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 154468947 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3822056 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2518552 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 34338225 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12857218 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 83619486 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 55122113 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11856452 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 137773765 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1037168 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1494015 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 163408 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 59807 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7647937 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 141868428 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 635547314 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 152852010 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9442 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 130675877 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11192540 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2699923 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2556575 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22590232 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 24607184 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19088589 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1696558 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2229617 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 134839557 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1714900 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 132985122 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 452743 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10598058 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21682682 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 119247 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 200312046 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.663890 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.961819 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 71664386 56.07% 56.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 23315575 18.24% 74.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22454220 17.57% 91.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9273638 7.26% 99.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1103003 0.86% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 52 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 123495652 61.65% 61.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 33655276 16.80% 78.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 31282184 15.62% 94.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10750314 5.37% 99.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1128564 0.56% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 56 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 127810874 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 200312046 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9324082 40.55% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 74 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5582954 24.28% 64.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8086742 35.17% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10816144 43.95% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 73 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5628152 22.87% 66.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8167261 33.18% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 66279940 65.98% 65.98% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 93468 0.09% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8018 0.01% 66.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18419781 18.34% 84.42% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15653721 15.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 89847428 67.56% 67.56% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 110447 0.08% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 7864 0.01% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 24369410 18.32% 85.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 18647698 14.02% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 100457201 # Type of FU issued -system.cpu0.iq.rate 0.762897 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 22993852 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228892 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 352138149 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 113036952 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 98428366 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32549 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 123427553 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21227 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 365954 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 132985122 # Type of FU issued +system.cpu0.iq.rate 0.649427 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 24611630 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.185071 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 491314323 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 147160457 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 129454820 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32339 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11262 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 157573424 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21055 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 367821 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1901526 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2478 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19250 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 882682 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1916447 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2461 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19267 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 901714 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 110051 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 360569 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 120909 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362204 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1038512 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1592668 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 210705 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 104136429 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2518552 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1651189 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 246744 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 136707359 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18663457 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 16076197 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876152 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 28505 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 158159 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19250 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 253073 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 398879 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 651952 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 99436169 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17977378 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 955231 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 24607184 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19088589 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876464 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27795 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 194810 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19267 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 261439 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 400306 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 661745 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 131953488 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 23926851 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 965273 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 152952 # number of nop insts executed -system.cpu0.iew.exec_refs 33471315 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16838084 # Number of branches executed -system.cpu0.iew.exec_stores 15493937 # Number of stores executed -system.cpu0.iew.exec_rate 0.755143 # Inst execution rate -system.cpu0.iew.wb_sent 98890175 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 98438082 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 51269761 # num instructions producing a value -system.cpu0.iew.wb_consumers 84681895 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.747564 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.605439 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 8044326 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1573050 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 595336 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 126126769 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.753686 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.472161 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152902 # number of nop insts executed +system.cpu0.iew.exec_refs 42414312 # number of memory reference insts executed +system.cpu0.iew.exec_branches 25613561 # Number of branches executed +system.cpu0.iew.exec_stores 18487461 # Number of stores executed +system.cpu0.iew.exec_rate 0.644389 # Inst execution rate +system.cpu0.iew.wb_sent 131398393 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 129464537 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 66052971 # num instructions producing a value +system.cpu0.iew.wb_consumers 106772912 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.632234 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618630 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9569777 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1595653 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 604480 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 197147849 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.639512 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.336739 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 81783872 64.84% 64.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24707932 19.59% 84.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8259395 6.55% 90.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3211630 2.55% 93.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3438301 2.73% 96.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1493917 1.18% 97.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1163537 0.92% 98.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 551177 0.44% 98.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1517008 1.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 136598241 69.29% 69.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 33559109 17.02% 86.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12649949 6.42% 92.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3238672 1.64% 94.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4912875 2.49% 96.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2898818 1.47% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1203082 0.61% 98.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 557487 0.28% 99.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1529616 0.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 126126769 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 79016795 # Number of instructions committed -system.cpu0.commit.committedOps 95059926 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 197147849 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 104125280 # Number of instructions committed +system.cpu0.commit.committedOps 126078442 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31955445 # Number of memory references committed -system.cpu0.commit.loads 16761930 # Number of loads committed -system.cpu0.commit.membars 647782 # Number of memory barriers committed -system.cpu0.commit.branches 16235143 # Number of branches committed +system.cpu0.commit.refs 40877611 # Number of memory references committed +system.cpu0.commit.loads 22690736 # Number of loads committed +system.cpu0.commit.membars 648887 # Number of memory barriers committed +system.cpu0.commit.branches 25008531 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 81982870 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1931434 # Number of function calls committed. +system.cpu0.commit.int_insts 110051272 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4840996 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 63005341 66.28% 66.28% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 91123 0.10% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8017 0.01% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16761930 17.63% 84.02% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 15193515 15.98% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 85084925 67.49% 67.49% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 108043 0.09% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 7863 0.01% 67.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 22690736 18.00% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18186875 14.43% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 95059926 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1517008 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 223519030 # The number of ROB reads -system.cpu0.rob.rob_writes 207883288 # The number of ROB writes -system.cpu0.timesIdled 136700 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3867673 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5520543918 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 78894743 # Number of Instructions Simulated -system.cpu0.committedOps 94937874 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.669041 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.669041 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.599147 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.599147 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 110427579 # number of integer regfile reads -system.cpu0.int_regfile_writes 59611828 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads +system.cpu0.commit.op_class_0::total 126078442 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1529616 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 307952651 # The number of ROB reads +system.cpu0.rob.rob_writes 274451297 # The number of ROB writes +system.cpu0.timesIdled 137106 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4460980 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5448417066 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 104003228 # Number of Instructions Simulated +system.cpu0.committedOps 125956390 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.968910 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.968910 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.507895 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.507895 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 142940096 # number of integer regfile reads +system.cpu0.int_regfile_writes 81795281 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8203 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 350340790 # number of cc regfile reads -system.cpu0.cc_regfile_writes 41062621 # number of cc regfile writes -system.cpu0.misc_regfile_reads 252371624 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1225237 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 711089 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.347987 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28802334 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 711601 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.475398 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.347987 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965523 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965523 # Average percentage of cache occupancy +system.cpu0.cc_regfile_reads 465685863 # number of cc regfile reads +system.cpu0.cc_regfile_writes 49834738 # number of cc regfile writes +system.cpu0.misc_regfile_reads 394201906 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1226279 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 711042 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.782039 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 37710898 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 711554 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.997943 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.782039 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972231 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.972231 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63463455 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63463455 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15558905 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15558905 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12019658 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12019658 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308619 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 308619 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363044 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363044 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361281 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361281 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27578563 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27578563 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27887182 # number of overall hits -system.cpu0.dcache.overall_hits::total 27887182 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 648058 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 648058 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1895809 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1895809 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147818 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147818 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25317 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25317 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20174 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20174 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2543867 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2543867 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2691685 # number of overall misses -system.cpu0.dcache.overall_misses::total 2691685 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8928091500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8928091500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29690163364 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29690163364 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 404195500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 404195500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 475433000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 475433000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 570500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 570500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38618254864 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38618254864 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38618254864 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38618254864 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16206963 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16206963 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13915467 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13915467 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456437 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456437 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388361 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388361 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381455 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381455 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30122430 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30122430 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30578867 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30578867 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039986 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039986 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136238 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136238 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323852 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323852 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065189 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065189 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052887 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052887 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084451 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084451 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088024 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088024 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13776.685883 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13776.685883 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15660.946522 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15660.946522 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15965.378994 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15965.378994 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23566.620402 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23566.620402 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81278285 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81278285 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 21483760 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21483760 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15003255 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15003255 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307803 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 307803 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363087 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363087 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361616 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361616 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 36487015 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 36487015 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 36794818 # number of overall hits +system.cpu0.dcache.overall_hits::total 36794818 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 647587 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 647587 # number of ReadReq misses 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overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9361035000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 9361035000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33017805879 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 33017805879 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 412521000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 412521000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 476921000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 476921000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 443000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 443000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 42378840879 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 42378840879 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 42378840879 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 42378840879 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22131347 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22131347 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16898051 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16898051 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456581 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456581 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388647 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388647 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381781 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381781 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 39029398 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 39029398 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39485979 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39485979 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029261 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029261 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112131 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.112131 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325852 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325852 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065767 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065767 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052818 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052818 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065140 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.065140 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068155 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.068155 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14455.254661 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14455.254661 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17425.520150 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17425.520150 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16139.319249 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16139.319249 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23650.929829 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23650.929829 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15180.925286 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15180.925286 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14347.241547 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14347.241547 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1034 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4271446 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 202383 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.541667 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21.105755 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 711089 # number of writebacks -system.cpu0.dcache.writebacks::total 711089 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260039 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 260039 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570278 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1570278 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18696 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18696 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830317 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1830317 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830317 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1830317 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388019 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 388019 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325531 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325531 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101607 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101607 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6621 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6621 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20174 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20174 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 713550 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 713550 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 815157 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 815157 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20336 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20336 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39368 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39368 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4833813000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4833813000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5968230399 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5968230399 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1672759500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1672759500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104692000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104692000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 455274000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 455274000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 555500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 555500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10802043399 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10802043399 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12474802899 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12474802899 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534406000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534406000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534406000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534406000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023941 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023941 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023393 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023393 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222609 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222609 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052887 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052887 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023688 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023688 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026658 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026658 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12457.670887 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12457.670887 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18333.831184 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18333.831184 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16463.034043 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16463.034043 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15812.112974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15812.112974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22567.363934 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22567.363934 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16668.944403 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16668.944403 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15747.419377 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15747.419377 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4996394 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 202489 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 24.674891 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 711042 # number of writebacks +system.cpu0.dcache.writebacks::total 711042 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260652 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 260652 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569869 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1569869 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18798 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18798 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830521 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1830521 # number of demand (read+write) MSHR hits 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misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20165 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 711862 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 711862 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 814380 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 814380 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28457 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses 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uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6624172500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6624172500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6624172500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017484 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017484 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224534 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224534 # mshr miss rate for SoftPFReq accesses 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12931.321798 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20393.775845 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20393.775845 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16642.345734 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16642.345734 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15850.783792 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15850.783792 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22651.475329 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22651.475329 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15138.453366 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15138.453366 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15303.558577 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15303.558577 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222974.331235 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222974.331235 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115179.993904 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115179.993904 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1254577 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.762789 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36189840 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1255088 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.834504 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6511134000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762789 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999537 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999537 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16337.533685 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16337.533685 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16375.904865 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16375.904865 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208425.287899 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208425.287899 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109964.848354 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109964.848354 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1252192 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.757674 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 71518552 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1252703 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 57.091387 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6585004000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757674 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 76255085 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 76255085 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36189843 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36189843 # number of ReadReq hits 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miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13674177457 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13674177457 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13674177457 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13674177457 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37499969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37499969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37499969 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37499969 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37499969 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37499969 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034937 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034937 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034937 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034937 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034937 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034937 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10437.299509 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10437.299509 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10437.299509 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10437.299509 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1615389 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 855 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 113956 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.175550 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 85.500000 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1254577 # number of writebacks -system.cpu0.icache.writebacks::total 1254577 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54978 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54978 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54978 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54978 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54978 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54978 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1255148 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1255148 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1255148 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1255148 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1255148 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1255148 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12423139434 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12423139434 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12423139434 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12423139434 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12423139434 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12423139434 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033471 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033471 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033471 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9897.748659 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9897.748659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9897.748659 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846782 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1849282 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2270 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.tags.tag_accesses 146904258 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 146904258 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 71518555 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 71518555 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 71518555 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 71518555 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 71518555 # number of overall hits +system.cpu0.icache.overall_hits::total 71518555 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1307201 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1307201 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1307201 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1307201 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1307201 # number of overall misses +system.cpu0.icache.overall_misses::total 1307201 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14223203310 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14223203310 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14223203310 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14223203310 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14223203310 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14223203310 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 72825756 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 72825756 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 72825756 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 72825756 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 72825756 # number of overall (read+write) accesses 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accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999928 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159667 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159667 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056741 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216654 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216654 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.106420 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158377 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158377 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056611 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.215206 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.215206 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105901 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.233472 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20918.262150 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 57534.711912 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17299.214716 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17299.214716 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15017.203768 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15017.203768 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 110499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 110499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40813.341067 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40813.341067 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 40940.561110 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24257.326226 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24257.326226 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32794.577145 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46257.816810 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214957.194138 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197865.825442 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111038.648141 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108989.414930 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4083931 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2062737 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 216422 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 214567 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 102316 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1901889 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19032 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19032 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 714747 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1482534 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 90142 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 335134 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87548 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42677 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113494 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288350 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285091 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1255148 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586492 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3253 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3770830 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2574893 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29200 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119227 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6494150 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160667312 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98708808 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53624 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 224224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 259653968 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 933771 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18925704 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3041721 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.089004 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.286883 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231756 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22466.666667 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66098.421047 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.843753 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.843753 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15088.941185 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15088.941185 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52429.478915 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52429.478915 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47251.752048 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26304.300160 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26304.300160 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38054.574604 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53283.753527 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200414.826002 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190706.237425 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105738.541476 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104900.943918 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4079155 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2060991 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31388 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 213571 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 211819 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1752 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 114320 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1911393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28457 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28457 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 712151 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1482098 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 89271 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 330960 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87226 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42590 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113358 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 287646 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1252747 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 585259 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3214 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3763658 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2614734 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29156 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119485 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6527033 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160361408 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98721444 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53072 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223432 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 259359356 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 926756 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18862496 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3052726 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.087981 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.285286 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2772852 91.16% 91.16% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 267014 8.78% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1855 0.06% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2785896 91.26% 91.26% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 265078 8.68% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1752 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3041721 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4067278494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3052726 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4077518993 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114026414 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113316466 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1886176090 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1882577097 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1218391120 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1233739845 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15802982 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15895485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63205426 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63655441 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 33853439 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11509465 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 280542 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18730917 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5987349 # Number of BTB hits +system.cpu1.branchPred.lookups 4630228 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2728889 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 266806 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2406642 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1541904 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 31.965061 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12496464 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7318 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 9007806 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 8970953 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 36853 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 10907 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 64.068690 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 874664 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7405 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 249240 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 213278 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 35962 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10619 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1661,89 +1661,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 21636 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21636 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8665 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5933 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7038 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14598 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 649.780792 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3376.631612 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13908 95.27% 95.27% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 186 1.27% 96.55% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 234 1.60% 98.15% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 108 0.74% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 46 0.32% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.21% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 8 0.05% 99.47% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 4 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 21137 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21137 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8393 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5852 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6892 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14245 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 645.419445 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3393.467484 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 13571 95.27% 95.27% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 196 1.38% 96.64% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 230 1.61% 98.26% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 102 0.72% 98.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.20% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 27 0.19% 99.36% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 10 0.07% 99.43% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.45% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.04% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 10 0.07% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14598 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5531 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11435.002712 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10101.039860 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6336.393968 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1833 33.14% 33.14% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3041 54.98% 88.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 457 8.26% 96.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 138 2.50% 98.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 31 0.56% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 23 0.42% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5531 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 68460974968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.179525 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.388721 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 68438733968 99.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 17027000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 2383000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 1817500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 437500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 205000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 153500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 216500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 68460974968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1927 75.51% 75.51% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 625 24.49% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2552 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21636 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14245 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5483 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11374.338866 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9975.216104 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6340.433585 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1893 34.52% 34.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2927 53.38% 87.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 431 7.86% 95.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 169 3.08% 98.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 33 0.60% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.44% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5483 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 77531116060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.220578 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.418371 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 60476667848 78.00% 78.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 17032378712 21.97% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 12865500 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 4248000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1183000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 1086000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 1322500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 461500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 217000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 174500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 136000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 33500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 198000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 27000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 21000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 77531116060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1915 74.80% 74.80% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 645 25.20% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2560 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21137 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21636 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2552 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21137 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2560 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2552 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2560 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 23697 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10130487 # DTB read hits -system.cpu1.dtb.read_misses 18672 # DTB read misses -system.cpu1.dtb.write_hits 6476473 # DTB write hits -system.cpu1.dtb.write_misses 2964 # DTB write misses +system.cpu1.dtb.read_hits 4149269 # DTB read hits +system.cpu1.dtb.read_misses 18244 # DTB read misses +system.cpu1.dtb.write_hits 3464998 # DTB write hits +system.cpu1.dtb.write_misses 2893 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1961 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 63 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 385 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1955 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 370 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10149159 # DTB read accesses -system.cpu1.dtb.write_accesses 6479437 # DTB write accesses +system.cpu1.dtb.perms_faults 410 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4167513 # DTB read accesses +system.cpu1.dtb.write_accesses 3467891 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16606960 # DTB hits -system.cpu1.dtb.misses 21636 # DTB misses -system.cpu1.dtb.accesses 16628596 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7614267 # DTB hits +system.cpu1.dtb.misses 21137 # DTB misses +system.cpu1.dtb.accesses 7635404 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1773,57 +1777,63 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 6064 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6064 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2840 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2623 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 601 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5463 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 343.950211 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2166.504505 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 5312 97.24% 97.24% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.04% 98.28% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 43 0.79% 99.07% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 29 0.53% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 6 0.11% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.09% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-32767 5 0.09% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5463 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1764 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12147.108844 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11115.999882 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5636.944380 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 277 15.70% 15.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1298 73.58% 89.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 111 6.29% 95.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 59 3.34% 98.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.51% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.40% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 5745 # Table walker walks requested +system.cpu1.itb.walker.walksShort 5745 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2522 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2644 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 579 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5166 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 354.045683 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2100.129090 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-2047 4967 96.15% 96.15% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.83% 96.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-6143 47 0.91% 97.89% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.41% 98.30% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-10239 19 0.37% 98.66% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::10240-12287 23 0.45% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-14335 19 0.37% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::14336-16383 7 0.14% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.12% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::18432-20479 1 0.02% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-22527 4 0.08% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::22528-24575 1 0.02% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.04% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::26624-28671 3 0.06% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-30719 3 0.06% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5166 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1734 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12119.088812 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10982.617612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5990.262254 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 321 18.51% 18.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1223 70.53% 89.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 108 6.23% 95.27% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 58 3.34% 98.62% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 14 0.81% 99.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.23% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 5 0.29% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1764 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16901758916 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.861276 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.345783 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2345411264 13.88% 13.88% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14555617152 86.12% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 730500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16901758916 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 989 85.04% 85.04% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 174 14.96% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1163 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 1734 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 17381208916 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.871345 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.334946 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2236929264 12.87% 12.87% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 15143532152 87.13% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 747500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 17381208916 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 985 85.28% 85.28% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 14.72% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1155 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6064 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6064 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5745 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5745 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1163 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1163 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7227 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 43493383 # ITB inst hits -system.cpu1.itb.inst_misses 6064 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6900 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 8164971 # ITB inst hits +system.cpu1.itb.inst_misses 5745 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1832,1023 +1842,1024 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1129 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1122 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 581 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43499447 # ITB inst accesses -system.cpu1.itb.hits 43493383 # DTB hits -system.cpu1.itb.misses 6064 # DTB misses -system.cpu1.itb.accesses 43499447 # DTB accesses -system.cpu1.numPwrStateTransitions 5513 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2757 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1005805033.413856 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25768715425.209221 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1955 70.91% 70.91% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.94% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 8170716 # ITB inst accesses +system.cpu1.itb.hits 8164971 # DTB hits +system.cpu1.itb.misses 5745 # DTB misses +system.cpu1.itb.accesses 8170716 # DTB accesses +system.cpu1.numPwrStateTransitions 5463 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2732 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1028238405.084919 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25963867647.326580 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1944 71.16% 71.16% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 782 28.62% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 959983620244 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2757 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 53106605878 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773004477122 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 106214002 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 959984033604 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2732 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 17447601808 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809147322692 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 34895980 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 10283907 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108683336 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 33853439 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27454766 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 92513470 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3739662 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 81877 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 30058 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 180666 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 303073 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23077 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43492215 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 108878 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2205 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 105285959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.278787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339334 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8706814 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 24545743 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4630228 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2629846 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 24236084 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 776070 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 77763 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 35252 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 165739 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 299959 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23654 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8163829 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 107624 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2029 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 33933300 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.881300 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.218696 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 48617714 46.18% 46.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 13927599 13.23% 59.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7511266 7.13% 66.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35229380 33.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20192419 59.51% 59.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4836103 14.25% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1645003 4.85% 78.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 7259775 21.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 105285959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.318729 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.023249 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13161149 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 62754723 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 26539387 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1087783 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1742917 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 736717 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 129511 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 67619846 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1094387 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1742917 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17542611 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2352209 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 57806856 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23225004 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2616362 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 54744976 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 213737 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 258070 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 37169 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15433 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1611507 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 54654605 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 258629758 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 58168286 # Number of integer rename lookups +system.cpu1.fetch.rateDist::total 33933300 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.132687 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.703397 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7185713 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16755217 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8648276 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1081250 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 262844 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 705359 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 127834 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 23145137 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1030723 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 262844 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8592488 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2388926 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11714810 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8302740 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2671492 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 21985761 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 184128 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 260119 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 36299 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 16259 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1667149 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 21955593 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 102445019 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 25352022 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 1683 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 52142746 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2511859 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1875660 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1802517 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13071586 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10382439 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6812181 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 622946 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 790955 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 53883918 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 580977 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 53654093 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93763 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3608749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5111945 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 44050 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 105285959 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.509603 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.847754 # Number of insts issued each cycle +system.cpu1.rename.CommittedMaps 19598713 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2356880 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 406325 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 333389 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2861472 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4400097 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3772059 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 619281 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 624174 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 21175375 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 559463 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 20999121 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 90560 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2005952 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4627057 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 43664 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 33933300 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.618835 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.947092 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72150462 68.53% 68.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16497460 15.67% 84.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13036209 12.38% 96.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3323109 3.16% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 278707 0.26% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 21549433 63.51% 63.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6114741 18.02% 81.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4178352 12.31% 93.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1835426 5.41% 99.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 255342 0.75% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 6 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 105285959 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 33933300 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2901953 45.47% 45.47% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 671 0.01% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1666030 26.11% 71.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1813313 28.41% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1405486 29.50% 29.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 669 0.01% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1602534 33.64% 63.16% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1754875 36.84% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36596131 68.21% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45838 0.09% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3311 0.01% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10338451 19.27% 87.57% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6670296 12.43% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 12960054 61.72% 61.72% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 27621 0.13% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3265 0.02% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4356029 20.74% 82.61% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3652086 17.39% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 53654093 # Type of FU issued -system.cpu1.iq.rate 0.505151 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6381967 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.118947 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 219063644 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58081406 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 51689844 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6231 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2072 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1788 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 60031897 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4097 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 89933 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 20999121 # Type of FU issued +system.cpu1.iq.rate 0.601763 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4763564 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226846 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 80779382 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 23748142 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20541259 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6284 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2076 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1790 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 25758471 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4148 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 87109 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 434041 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 639 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 9872 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 275866 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 405898 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 640 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9457 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 249525 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 52151 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 77961 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 40585 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 76754 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1742917 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 520776 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 103336 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 54505946 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 262844 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 543765 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 103558 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 21775845 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10382439 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6812181 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 296650 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 7746 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 89089 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 9872 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 44543 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 120099 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 164642 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 53411917 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10242028 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 220561 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 4400097 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3772059 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 296163 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7694 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 88949 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9457 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 34239 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 118390 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 152629 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 20771745 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4261184 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 206260 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41051 # number of nop insts executed -system.cpu1.iew.exec_refs 16861277 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11793508 # Number of branches executed -system.cpu1.iew.exec_stores 6619249 # Number of stores executed -system.cpu1.iew.exec_rate 0.502871 # Inst execution rate -system.cpu1.iew.wb_sent 53270244 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 51691632 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25129407 # num instructions producing a value -system.cpu1.iew.wb_consumers 38339279 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.486674 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.655448 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 3369485 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 536927 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 153628 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103395222 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.492179 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.152090 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41007 # number of nop insts executed +system.cpu1.iew.exec_refs 7864490 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3010595 # Number of branches executed +system.cpu1.iew.exec_stores 3603306 # Number of stores executed +system.cpu1.iew.exec_rate 0.595248 # Inst execution rate +system.cpu1.iew.wb_sent 20641556 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 20543049 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10275425 # num instructions producing a value +system.cpu1.iew.wb_consumers 16109782 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.588694 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.637838 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1795274 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 515799 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 141615 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 33527734 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.589415 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.349112 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 77830115 75.27% 75.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14293086 13.82% 89.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6071280 5.87% 94.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 693599 0.67% 95.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1980010 1.91% 97.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1625143 1.57% 99.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 382099 0.37% 99.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 124911 0.12% 99.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 394979 0.38% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 24087304 71.84% 71.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 5545630 16.54% 88.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1675188 5.00% 93.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 660381 1.97% 95.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 508267 1.52% 96.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 330740 0.99% 97.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 223183 0.67% 98.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 117603 0.35% 98.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 379438 1.13% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103395222 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41318794 # Number of instructions committed -system.cpu1.commit.committedOps 50889001 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 33527734 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 16118487 # Number of instructions committed +system.cpu1.commit.committedOps 19761740 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16484713 # Number of memory references committed -system.cpu1.commit.loads 9948398 # Number of loads committed -system.cpu1.commit.membars 208127 # Number of memory barriers committed -system.cpu1.commit.branches 11637916 # Number of branches committed +system.cpu1.commit.refs 7516733 # Number of memory references committed +system.cpu1.commit.loads 3994199 # Number of loads committed +system.cpu1.commit.membars 208310 # Number of memory barriers committed +system.cpu1.commit.branches 2858693 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 45745086 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3368055 # Number of function calls committed. +system.cpu1.commit.int_insts 17575462 # Number of committed integer instructions. +system.cpu1.commit.function_calls 459876 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 34356210 67.51% 67.51% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 44767 0.09% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3311 0.01% 67.61% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.61% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.61% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.61% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9948398 19.55% 87.16% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6536315 12.84% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 12215165 61.81% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 26577 0.13% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3265 0.02% 61.96% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.96% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.96% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3994199 20.21% 82.17% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3522534 17.83% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 50889001 # Class of committed instruction -system.cpu1.commit.bw_lim_events 394979 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 137189075 # The number of ROB reads -system.cpu1.rob.rob_writes 110398979 # The number of ROB writes -system.cpu1.timesIdled 58975 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 928043 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5545446856 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41285938 # Number of Instructions Simulated -system.cpu1.committedOps 50856145 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.572644 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.572644 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.388705 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.388705 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 55995090 # number of integer regfile reads -system.cpu1.int_regfile_writes 35603094 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 19761740 # Class of committed instruction +system.cpu1.commit.bw_lim_events 379438 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 53719965 # The number of ROB reads +system.cpu1.rob.rob_writes 43510270 # The number of ROB writes +system.cpu1.timesIdled 58110 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 962680 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5617725351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 16085632 # Number of Instructions Simulated +system.cpu1.committedOps 19728885 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.169388 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.169388 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.460959 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.460959 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 23317955 # number of integer regfile reads +system.cpu1.int_regfile_writes 13332838 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1403 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 190376100 # number of cc regfile reads -system.cpu1.cc_regfile_writes 15518701 # number of cc regfile writes -system.cpu1.misc_regfile_reads 209095836 # number of misc regfile reads -system.cpu1.misc_regfile_writes 386203 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 187149 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.748213 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 15687000 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187502 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 83.663108 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 93899473000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.748213 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917477 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.917477 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 32860265 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 32860265 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 9540081 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9540081 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5893568 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5893568 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48959 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48959 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77987 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 77987 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70168 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70168 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15433649 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15433649 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15482608 # number of overall hits -system.cpu1.dcache.overall_hits::total 15482608 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 215586 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 215586 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 396166 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 396166 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30156 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30156 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18335 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18335 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23429 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23429 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 611752 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 611752 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 641908 # number of overall misses -system.cpu1.dcache.overall_misses::total 641908 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3514528500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3514528500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9742278459 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9742278459 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360181500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 360181500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551095500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 551095500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 166500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 166500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13256806959 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13256806959 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13256806959 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13256806959 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9755667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6289734 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6289734 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79115 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79115 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96322 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96322 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93597 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93597 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16045401 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16045401 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16124516 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16124516 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022099 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022099 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062986 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.062986 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381167 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381167 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190351 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190351 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250318 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250318 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038126 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038126 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039809 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039809 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16302.211183 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16302.211183 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24591.404762 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24591.404762 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19644.477775 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19644.477775 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23521.938623 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23521.938623 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 74580678 # number of cc regfile reads +system.cpu1.cc_regfile_writes 6681708 # number of cc regfile writes +system.cpu1.misc_regfile_reads 69976526 # number of misc regfile reads +system.cpu1.misc_regfile_writes 387406 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 185136 # number of replacements +system.cpu1.dcache.tags.tagsinuse 468.617373 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6737062 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 185477 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.322897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89354157500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.617373 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915268 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.915268 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14947542 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14947542 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3587773 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3587773 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2897885 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2897885 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49072 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49072 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78768 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78768 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70845 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70845 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6485658 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6485658 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6534730 # number of overall hits +system.cpu1.dcache.overall_hits::total 6534730 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 212319 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 212319 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 390908 # number of WriteReq misses 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ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3545506500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9944995958 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9944995958 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362846000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 362846000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551070500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 551070500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 640500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 640500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13490502458 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13490502458 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13490502458 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13490502458 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3800092 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3800092 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3288793 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3288793 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 78959 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 78959 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97123 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97123 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94310 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94310 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7088885 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7088885 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7167844 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7167844 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055872 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.055872 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118861 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.118861 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378513 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378513 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188987 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188987 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248807 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248807 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085095 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.085095 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088327 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.088327 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16698.960055 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16698.960055 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25440.758332 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25440.758332 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19768.237537 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19768.237537 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23484.785851 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23484.785851 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21670.230680 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21670.230680 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20652.191527 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20652.191527 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1431753 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39808 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.210526 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 35.966464 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 187150 # number of writebacks -system.cpu1.dcache.writebacks::total 187150 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79090 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 79090 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306284 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 306284 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13036 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13036 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 385374 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 385374 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 385374 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 385374 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136496 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 136496 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89882 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 89882 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28741 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28741 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5299 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5299 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23429 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23429 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 226378 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 226378 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 255119 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 255119 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14517 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14517 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11855 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11855 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26372 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26372 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1963325500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1963325500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2363104967 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2363104967 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488593500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488593500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93065000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93065000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527670500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527670500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 162500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 162500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326430467 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4326430467 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4815023967 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4815023967 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2528366000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2528366000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2528366000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2528366000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014290 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014290 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.363281 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.363281 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055013 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055013 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250318 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250318 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014109 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014109 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015822 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015822 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14383.758498 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14383.758498 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26291.192530 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26291.192530 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16999.878223 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16999.878223 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17562.747688 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17562.747688 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22522.109352 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22522.109352 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22363.890307 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22363.890307 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21308.172711 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21308.172711 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1473013 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39225 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37.552913 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 185136 # number of writebacks +system.cpu1.dcache.writebacks::total 185136 # number of writebacks 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of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 252253 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 252253 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3386 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3386 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2740 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6126 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6126 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1970715500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1970715500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2395378969 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2395378969 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 480267000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 480267000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 94406500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 94406500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527620500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527620500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 625500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 625500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4366094469 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4366094469 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846361469 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4846361469 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 459425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 459425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 459425000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 459425000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035457 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035457 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027054 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027054 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361441 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361441 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054230 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054230 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248807 # mshr miss rate for StoreCondReq accesses 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16828.445285 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16828.445285 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17924.150370 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17924.150370 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22485.425101 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22485.425101 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19111.532335 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19111.532335 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18873.639231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18873.639231 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174165.874492 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174165.874492 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95873.123009 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95873.123009 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 589510 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.449637 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 42880129 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 590022 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 72.675475 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79021423000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.449637 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975488 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975488 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19516.411440 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19516.411440 # average overall mshr miss latency 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9316.925575 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9316.925575 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9316.925575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9316.925575 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 502398 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 16911139 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 16911139 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 7557735 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 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overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9382.021605 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 514122 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42118 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 41357 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.928344 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.431318 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 589510 # number of writebacks -system.cpu1.icache.writebacks::total 589510 # number of writebacks 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(read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5243631193 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5243631193 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5243631193 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8747999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8747999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8747999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8747999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013566 # mshr miss rate for ReadReq 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8887.118861 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86613.851485 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86613.851485 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 195371 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 196016 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 576 # number of redundant prefetches already in prefetch queue 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overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92297.019802 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92297.019802 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 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30 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13830 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14183.524826 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.708728 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.055002 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 436.823115 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.865694 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000715 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026662 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.893195 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 321 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13723 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 183 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8625 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3420 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017944 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001831 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.844116 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 27388422 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 27388422 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17107 # 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# number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17107 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6359 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 565476 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 126115 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 715057 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17107 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6359 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 565476 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 126115 # number of overall hits -system.cpu1.l2cache.overall_hits::total 715057 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 487 # number of ReadReq misses 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ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 487 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 295 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 24548 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 105277 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 130607 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 487 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 295 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 24548 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 105277 # number of overall misses -system.cpu1.l2cache.overall_misses::total 130607 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10682500 # number of ReadReq miss cycles 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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153839 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546381 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546381 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040822 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.419871 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.419871 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153553 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183275 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15346.794872 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41062.935524 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15478.018461 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15478.018461 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15006.316958 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15006.316958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183602 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15722.715736 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44579.958058 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15354.338666 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15354.338666 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14973.513744 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14973.513744 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33744.960910 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33744.960910 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31362.871348 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16784.184169 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16784.184169 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23897.821570 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26654.734523 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166162.395812 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165560.918046 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91467.446534 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91420.296151 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1661462 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 840058 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12360 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 115637 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106952 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8685 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 43235 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 842502 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 146735 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 662812 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 29649 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30154 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41626 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86297 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 68185 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 65527 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 590026 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 275295 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 251 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1769762 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885483 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14740 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38125 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2708110 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75491792 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29665722 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26616 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70376 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 105254506 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 347103 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4899396 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1195777 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.122893 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.349738 # Request fanout histogram +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35586.719554 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35586.719554 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33327.579698 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17122.279522 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17122.279522 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24870.952536 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28096.655324 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127673.656232 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126431.603097 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 70568.560235 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70799.261282 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1644268 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 831312 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115055 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106415 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8640 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 31394 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 822139 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 144852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 655914 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 29483 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71834 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 67721 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 64923 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 584003 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 271211 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 307 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1751691 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 836213 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14098 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37121 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2639123 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74720720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29257698 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25152 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68096 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 104071666 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 343275 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4808780 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1162877 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.125522 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.353024 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1057509 88.44% 88.44% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 129583 10.84% 99.27% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8685 0.73% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1025550 88.19% 88.19% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 128687 11.07% 99.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8640 0.74% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1195777 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1635737987 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1162877 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1604189995 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81718473 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80522049 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 885241795 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 876204799 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 395391898 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 375699214 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 8093984 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 7819481 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20543974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20111970 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution @@ -2899,33 +2910,33 @@ system.iobus.pkt_size_system.bridge.master::total 162794 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40381000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40380000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 328000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 575500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 570500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -2933,32 +2944,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6080500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6100500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33803000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33792000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187681355 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187796551 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.555440 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.553749 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255145986000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.555440 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909715 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909715 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255488373000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.553749 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909609 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909609 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2967,14 +2978,14 @@ system.iocache.demand_misses::realview.ide 36476 # system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32543877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32543877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4303510478 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4303510478 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4336054355 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4336054355 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4336054355 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4336054355 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 40604377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 40604377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4366091174 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4366091174 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4406695551 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4406695551 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4406695551 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4406695551 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2991,19 +3002,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129142.369048 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129142.369048 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118802.740669 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118802.740669 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118874.173566 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118874.173566 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 161128.480159 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 161128.480159 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120530.343805 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120530.343805 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120810.822212 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120810.822212 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5.750000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -3015,14 +3026,14 @@ system.iocache.demand_mshr_misses::realview.ide 36476 system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19943877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19943877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489987873 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2489987873 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2509931750 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2509931750 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2509931750 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2509931750 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 28004377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 28004377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2552566881 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2552566881 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2580571258 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2580571258 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2580571258 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2580571258 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3031,618 +3042,612 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79142.369048 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79142.369048 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68738.622819 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68738.622819 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 136926 # number of replacements -system.l2c.tags.tagsinuse 65153.135165 # Cycle average of tags in use -system.l2c.tags.total_refs 554455 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 202299 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.740770 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 87124800000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6156.009081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.876446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.073086 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8059.392106 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7027.702710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37061.403814 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.474451 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906071 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1853.985065 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2995.751440 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1972.560896 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.093933 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000273 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111128.480159 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111128.480159 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70466.179356 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70466.179356 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 137609 # number of replacements +system.l2c.tags.tagsinuse 65136.051895 # Cycle average of tags in use +system.l2c.tags.total_refs 548833 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 202971 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.703997 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 87466496000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 5939.611941 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.674941 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.061639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8089.660546 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7047.830837 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37514.795432 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.739703 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.908322 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1674.813935 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2903.059558 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1945.895041 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.090631 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000239 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.122977 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.107234 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.565512 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000099 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.123438 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.107541 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572430 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.028290 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994158 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 33193 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32156 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 172 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5974 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 27047 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.025556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044297 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029692 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993897 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33502 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31839 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 401 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6111 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26990 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4634 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27347 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.506485 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.490662 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6339538 # Number of tag accesses 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-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 230 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 51619 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 58109 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47216 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 63 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 17 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 21642 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11731 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5163 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 195876 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 230 # number of demand (read+write) hits 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of overall (read+write) accesses -system.l2c.overall_accesses::total 391951 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.014494 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.102835 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.024550 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018235 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.059814 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.037007 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.739622 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.846586 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.781348 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for 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64124.708625 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196956.087726 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148192.365991 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167436.910471 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101739.966470 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81567.901703 # average overall mshr uncacheable latency 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+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078286 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470961 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.490865 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.490865 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22259.668508 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20685.567010 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21710.431655 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26375 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22187.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24153.061224 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137616.578778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 81790.674966 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 114003.691327 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105678.857876 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113259.938838 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113151.993367 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182412.592065 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109767.070647 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166861.720777 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96240.591660 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60647.068431 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 91929.949202 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 504773 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 283620 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 37954 # Transaction distribution -system.membus.trans_dist::ReadResp 209195 # Transaction distribution -system.membus.trans_dist::WriteReq 30887 # Transaction distribution -system.membus.trans_dist::WriteResp 30887 # Transaction distribution -system.membus.trans_dist::WritebackDirty 137421 # Transaction distribution -system.membus.trans_dist::CleanEvict 16935 # Transaction distribution -system.membus.trans_dist::UpgradeReq 65286 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38770 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38274 # Transaction distribution +system.membus.trans_dist::ReadResp 210079 # Transaction distribution +system.membus.trans_dist::WriteReq 31197 # Transaction distribution +system.membus.trans_dist::WriteResp 31197 # Transaction distribution +system.membus.trans_dist::WritebackDirty 137547 # Transaction distribution +system.membus.trans_dist::CleanEvict 17007 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64594 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38710 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 39566 # Transaction distribution -system.membus.trans_dist::ReadExResp 19573 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171242 # Transaction distribution +system.membus.trans_dist::ReadExReq 38808 # Transaction distribution +system.membus.trans_dist::ReadExResp 19352 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171806 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638853 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 760423 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638456 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 761276 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 834225 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18721784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18912106 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18751880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18944702 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21230250 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123250 # Total snoops (count) +system.membus.pkt_size::total 21262846 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 122284 # Total snoops (count) system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 419934 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012350 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.110440 # Request fanout histogram +system.membus.snoop_fanout::samples 419616 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012440 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.110839 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 414748 98.77% 98.77% # Request fanout histogram -system.membus.snoop_fanout::1 5186 1.23% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 414396 98.76% 98.76% # Request fanout histogram +system.membus.snoop_fanout::1 5220 1.24% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 419934 # Request fanout histogram -system.membus.reqLayer0.occupancy 81570000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 419616 # Request fanout histogram +system.membus.reqLayer0.occupancy 81572000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11357000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12355500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 987545766 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 987789803 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1099710840 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1102143190 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1385881 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1335877 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3674,81 +3679,81 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1051858 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 557134 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 188416 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 28173 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 27109 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1064 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 37957 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 525508 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30887 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30887 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 364306 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 131438 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 111511 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43584 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 155095 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50612 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50612 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 487554 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1267106 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 367019 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1634125 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36291756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5905726 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 42197482 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 390713 # Total snoops (count) -system.toL2Bus.snoopTraffic 15836620 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 903686 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.404217 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.493133 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1044068 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 554075 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 185190 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 28829 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27647 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38277 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 522605 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31197 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31197 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 362967 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 130325 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 110585 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43604 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 154189 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50073 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50073 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 484331 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4646 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1303151 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320962 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1624113 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36235416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5679078 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41914494 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 390245 # Total snoops (count) +system.toL2Bus.snoopTraffic 15796172 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 900374 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.402074 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.492987 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 539465 59.70% 59.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 363157 40.19% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1064 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 539539 59.92% 59.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 359653 39.94% 99.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1182 0.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 903686 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 901600874 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 900374 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 896925065 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 679704118 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 692605391 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 260937433 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 242340870 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2757 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2732 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal index d38aec98b..263610058 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal @@ -159,9 +159,9 @@ ata1.00: configured for UDMA/33 scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
sd 0:0:0:0: [sda] Write Protect is off
+sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-sd 0:0:0:0: Attached scsi generic sg0 type 0
sda: sda1
sd 0:0:0:0: [sda] Attached SCSI disk
e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 39155f2aa..c0b6f00cc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -229,7 +229,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -723,7 +723,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -840,7 +840,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -885,7 +885,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -897,7 +897,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -929,29 +929,36 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -971,6 +978,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -980,7 +988,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1002,9 +1010,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1357,7 +1365,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1674,6 +1682,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1681,7 +1690,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -1912,6 +1921,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1919,7 +1929,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index af03e613f..2d99e9ceb 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:36:45 -gem5 executing on e108600-lin, pid 13212 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:43:01 +gem5 executing on e108600-lin, pid 17340 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2832894126500 because m5_exit instruction encountered +Exiting @ tick 2829112944500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index fdcb3cf4d..85eda68ae 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827853 # Number of seconds simulated -sim_ticks 2827853096000 # Number of ticks simulated -final_tick 2827853096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.829113 # Number of seconds simulated +sim_ticks 2829112944500 # Number of ticks simulated +final_tick 2829112944500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94322 # Simulator instruction rate (inst/s) -host_op_rate 114411 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2357194570 # Simulator tick rate (ticks/s) -host_mem_usage 589152 # Number of bytes of host memory used -host_seconds 1199.67 # Real time elapsed on the host -sim_insts 113155640 # Number of instructions simulated -sim_ops 137255479 # Number of ops (including micro ops) simulated +host_inst_rate 77107 # Simulator instruction rate (inst/s) +host_op_rate 93526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1927521729 # Simulator tick rate (ticks/s) +host_mem_usage 584852 # Number of bytes of host memory used +host_seconds 1467.75 # Real time elapsed on the host +sim_insts 113173049 # Number of instructions simulated +sim_ops 137272583 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1322240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9790440 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1316512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9473064 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11115048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1322240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1322240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8407168 # Number of bytes written to this memory +system.physmem.bytes_read::total 10791880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1316512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1316512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8091648 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8424692 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 153496 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8109172 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22822 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148537 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176440 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131362 # Number of write requests responded to by this memory +system.physmem.num_reads::total 171395 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126432 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135743 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 467577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3462146 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 130813 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 465344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3348422 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3930561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 467577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 467577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2972986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2979183 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2972986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 467577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3468343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3814581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 465344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2860136 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2866330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2860136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 465344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3354616 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6909744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 176441 # Number of read requests accepted -system.physmem.writeReqs 135743 # Number of write requests accepted -system.physmem.readBursts 176441 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 135743 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11282432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue -system.physmem.bytesWritten 8437824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11115112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8424692 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 6680911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 171396 # Number of read requests accepted +system.physmem.writeReqs 130813 # Number of write requests accepted +system.physmem.readBursts 171396 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 130813 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10959744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue +system.physmem.bytesWritten 8121728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10791944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8109172 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11743 # Per bank write bursts -system.physmem.perBankRdBursts::1 11227 # Per bank write bursts -system.physmem.perBankRdBursts::2 11041 # Per bank write bursts -system.physmem.perBankRdBursts::3 10652 # Per bank write bursts -system.physmem.perBankRdBursts::4 13485 # Per bank write bursts -system.physmem.perBankRdBursts::5 11002 # Per bank write bursts -system.physmem.perBankRdBursts::6 11432 # Per bank write bursts -system.physmem.perBankRdBursts::7 11844 # Per bank write bursts -system.physmem.perBankRdBursts::8 10383 # Per bank write bursts -system.physmem.perBankRdBursts::9 10947 # Per bank write bursts -system.physmem.perBankRdBursts::10 10471 # Per bank write bursts -system.physmem.perBankRdBursts::11 9569 # Per bank write bursts -system.physmem.perBankRdBursts::12 10361 # Per bank write bursts -system.physmem.perBankRdBursts::13 11110 # Per bank write bursts -system.physmem.perBankRdBursts::14 10361 # Per bank write bursts -system.physmem.perBankRdBursts::15 10660 # Per bank write bursts -system.physmem.perBankWrBursts::0 8764 # Per bank write bursts -system.physmem.perBankWrBursts::1 8604 # Per bank write bursts -system.physmem.perBankWrBursts::2 8676 # Per bank write bursts -system.physmem.perBankWrBursts::3 8310 # Per bank write bursts -system.physmem.perBankWrBursts::4 8074 # Per bank write bursts -system.physmem.perBankWrBursts::5 8230 # Per bank write bursts -system.physmem.perBankWrBursts::6 8228 # Per bank write bursts -system.physmem.perBankWrBursts::7 8800 # Per bank write bursts -system.physmem.perBankWrBursts::8 7938 # Per bank write bursts -system.physmem.perBankWrBursts::9 8472 # Per bank write bursts -system.physmem.perBankWrBursts::10 8080 # Per bank write bursts -system.physmem.perBankWrBursts::11 7388 # Per bank write bursts -system.physmem.perBankWrBursts::12 8035 # Per bank write bursts -system.physmem.perBankWrBursts::13 8487 # Per bank write bursts -system.physmem.perBankWrBursts::14 7854 # Per bank write bursts -system.physmem.perBankWrBursts::15 7901 # Per bank write bursts +system.physmem.perBankRdBursts::0 10680 # Per bank write bursts +system.physmem.perBankRdBursts::1 10044 # Per bank write bursts +system.physmem.perBankRdBursts::2 10837 # Per bank write bursts +system.physmem.perBankRdBursts::3 10904 # Per bank write bursts +system.physmem.perBankRdBursts::4 13724 # Per bank write bursts +system.physmem.perBankRdBursts::5 10680 # Per bank write bursts +system.physmem.perBankRdBursts::6 11438 # Per bank write bursts +system.physmem.perBankRdBursts::7 11401 # Per bank write bursts +system.physmem.perBankRdBursts::8 10103 # Per bank write bursts +system.physmem.perBankRdBursts::9 10404 # Per bank write bursts +system.physmem.perBankRdBursts::10 10359 # Per bank write bursts +system.physmem.perBankRdBursts::11 9493 # Per bank write bursts +system.physmem.perBankRdBursts::12 10229 # Per bank write bursts +system.physmem.perBankRdBursts::13 11052 # Per bank write bursts +system.physmem.perBankRdBursts::14 10015 # Per bank write bursts +system.physmem.perBankRdBursts::15 9883 # Per bank write bursts +system.physmem.perBankWrBursts::0 8063 # Per bank write bursts +system.physmem.perBankWrBursts::1 7694 # Per bank write bursts +system.physmem.perBankWrBursts::2 8368 # Per bank write bursts +system.physmem.perBankWrBursts::3 8157 # Per bank write bursts +system.physmem.perBankWrBursts::4 8127 # Per bank write bursts +system.physmem.perBankWrBursts::5 8035 # Per bank write bursts +system.physmem.perBankWrBursts::6 8542 # Per bank write bursts +system.physmem.perBankWrBursts::7 8476 # Per bank write bursts +system.physmem.perBankWrBursts::8 7684 # Per bank write bursts +system.physmem.perBankWrBursts::9 7982 # Per bank write bursts +system.physmem.perBankWrBursts::10 7772 # Per bank write bursts +system.physmem.perBankWrBursts::11 7097 # Per bank write bursts +system.physmem.perBankWrBursts::12 7777 # Per bank write bursts +system.physmem.perBankWrBursts::13 8429 # Per bank write bursts +system.physmem.perBankWrBursts::14 7462 # Per bank write bursts +system.physmem.perBankWrBursts::15 7237 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2827852861000 # Total gap between requests +system.physmem.numWrRetry 78 # Number of times write queue was full causing retry +system.physmem.totGap 2829112709500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2996 # Read request sizes (log2) +system.physmem.readPktSize::4 3002 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 172889 # Read request sizes (log2) +system.physmem.readPktSize::6 167838 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131362 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 155219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126432 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -160,164 +160,181 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.434251 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.571710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.070143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24166 37.18% 37.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15993 24.61% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6821 10.50% 72.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3792 5.83% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2758 4.24% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1633 2.51% 84.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1086 1.67% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1085 1.67% 88.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7656 11.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64990 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6662 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.461423 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 559.657587 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6661 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6662 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.790003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.288798 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.351415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5875 88.19% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 70 1.05% 89.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 75 1.13% 90.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 36 0.54% 90.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 259 3.89% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 62 0.93% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 25 0.38% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.29% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.14% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.11% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 160 2.40% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.12% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 10 0.15% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6662 # Writes before turning the bus around for reads -system.physmem.totQLat 2116192000 # Total ticks spent queuing -system.physmem.totMemAccLat 5421592000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 881440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12004.17 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30754.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.93 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s +system.physmem.wrQLenPdf::15 1809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 207 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.483382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.687105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.840241 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22553 36.82% 36.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14650 23.91% 60.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6334 10.34% 71.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3752 6.12% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2675 4.37% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1648 2.69% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1058 1.73% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1036 1.69% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7554 12.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61260 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6323 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.072592 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 535.871052 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6321 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6323 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6323 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.069904 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.255220 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.875839 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5596 88.50% 88.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 82 1.30% 89.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 53 0.84% 90.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 37 0.59% 91.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 252 3.99% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 36 0.57% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.14% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 7 0.11% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 139 2.20% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 10 0.16% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.05% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 12 0.19% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.06% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.24% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6323 # Writes before turning the bus around for reads +system.physmem.totQLat 4766161750 # Total ticks spent queuing +system.physmem.totMemAccLat 7977024250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 856230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27832.09 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 46581.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.03 # Average write queue length when enqueuing -system.physmem.readRowHits 145153 # Number of row buffer hits during reads -system.physmem.writeRowHits 97985 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.31 # Row buffer hit rate for writes -system.physmem.avgGap 9058288.90 # Average gap between requests -system.physmem.pageHitRate 78.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 256087440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 139730250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 720922800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 438605280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81077227785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625589296250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892923233405 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.386141 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704185411500 # Time in different power states -system.physmem_0.memoryStateTime::REF 94428100000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29235954750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 235236960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 128353500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654115800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 415724400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80292349755 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626277785750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892704929765 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.308944 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705344853000 # Time in different power states -system.physmem_1.memoryStateTime::REF 94428100000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28080129500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.57 # Average write queue length when enqueuing +system.physmem.readRowHits 141751 # Number of row buffer hits during reads +system.physmem.writeRowHits 95137 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.96 # Row buffer hit rate for writes +system.physmem.avgGap 9361444.26 # Average gap between requests +system.physmem.pageHitRate 79.45 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229201140 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121823295 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 640515120 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 341711640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5262547680.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4339877970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 323354400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10814226390 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7334392800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 667253476395 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 696663805260 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.248141 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2818581671250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 598120000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2237496000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2775932271000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 19100075750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7529604250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23715377500 # Time in different power states +system.physmem_1.actEnergy 208195260 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 110658405 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 582181320 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 320716800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5105199840.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4092887280 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 324388800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10096669920 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 7288782240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 667807505910 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 695939317005 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.992058 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2819287837500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 611681500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2171134000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2778164795750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 18981177000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7042291500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22141864750 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -330,30 +347,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46859222 # Number of BP lookups -system.cpu.branchPred.condPredicted 23995015 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1174256 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29489294 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13535968 # Number of BTB hits +system.cpu.branchPred.lookups 46887151 # Number of BP lookups +system.cpu.branchPred.condPredicted 24003532 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1173792 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29506695 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13539046 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 45.901296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11745095 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 35189 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7931554 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7786304 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 145250 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60170 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 45.884658 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11754270 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 34776 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7941183 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7796256 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 144927 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 60295 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,83 +400,91 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 72426 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72426 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29716 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23400 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19310 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 53116 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 407.485503 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2469.018740 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-8191 51917 97.74% 97.74% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-16383 937 1.76% 99.51% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-24575 190 0.36% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-32767 37 0.07% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 53116 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17396 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9637.387905 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7803.906851 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6813.601039 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 15561 89.45% 89.45% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1740 10.00% 99.45% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 86 0.49% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::49152-65535 2 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17396 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 117727604724 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.629848 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489627 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 117677681224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 34838500 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7318000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4585500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 935500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 533500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1306000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 397000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 117727604724 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6471 81.85% 81.85% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1435 18.15% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7906 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72426 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 71256 # Table walker walks requested +system.cpu.dtb.walker.walksShort 71256 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29049 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23358 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 18849 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52407 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 389.146488 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2289.126746 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50564 96.48% 96.48% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 708 1.35% 97.83% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 582 1.11% 98.94% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 319 0.61% 99.55% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 67 0.13% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 32 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52407 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 16824 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9444.513790 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7664.409790 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6506.438101 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-8191 8278 49.20% 49.20% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::8192-16383 6918 41.12% 90.32% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-24575 1373 8.16% 98.48% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::24576-32767 165 0.98% 99.47% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-40959 22 0.13% 99.60% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::40960-49151 59 0.35% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::90112-98303 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-106495 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::114688-122879 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 16824 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 118987489224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.630928 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.488775 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 118941247224 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 32120500 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 6765500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 4407000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 968000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 470000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1161500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 338000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 11500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 118987489224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6321 82.34% 82.34% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1356 17.66% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7677 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71256 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72426 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7906 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71256 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7677 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7906 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 80332 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7677 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 78933 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25423365 # DTB read hits -system.cpu.dtb.read_misses 62664 # DTB read misses -system.cpu.dtb.write_hits 19868926 # DTB write hits -system.cpu.dtb.write_misses 9762 # DTB write misses +system.cpu.dtb.read_hits 25423703 # DTB read hits +system.cpu.dtb.read_misses 61573 # DTB read misses +system.cpu.dtb.write_hits 19869711 # DTB write hits +system.cpu.dtb.write_misses 9683 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4289 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2236 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 365 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2214 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1258 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25486029 # DTB read accesses -system.cpu.dtb.write_accesses 19878688 # DTB write accesses +system.cpu.dtb.perms_faults 1309 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25485276 # DTB read accesses +system.cpu.dtb.write_accesses 19879394 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45292291 # DTB hits -system.cpu.dtb.misses 72426 # DTB misses -system.cpu.dtb.accesses 45364717 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 45293414 # DTB hits +system.cpu.dtb.misses 71256 # DTB misses +system.cpu.dtb.accesses 45364670 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -489,58 +514,51 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 12855 # Table walker walks requested -system.cpu.itb.walker.walksShort 12855 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3590 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7693 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 1572 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11283 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 605.778605 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2805.757421 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 10907 96.67% 96.67% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 327 2.90% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 40 0.35% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 5 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11283 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 4887 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 8961.019030 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7007.167188 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7172.888707 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 3327 68.08% 68.08% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 829 16.96% 85.04% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 682 13.96% 99.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 38 0.78% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 1 0.02% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::40960-49151 7 0.14% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::49152-57343 1 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 4887 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23237381212 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.774797 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.417824 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 5234024500 22.52% 22.52% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 18002578212 77.47% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 696500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23237381212 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 12694 # Table walker walks requested +system.cpu.itb.walker.walksShort 12694 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3385 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7744 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 1565 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11129 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 587.519094 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2554.039533 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 10635 95.56% 95.56% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 121 1.09% 96.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 223 2.00% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 105 0.94% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 19 0.17% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 20 0.18% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-45055 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11129 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 4883 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 9054.884292 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7027.204830 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 11165.478993 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 4881 99.96% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 4883 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 24497265712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.701353 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.457724 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 7316690500 29.87% 29.87% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 17179912712 70.13% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 662500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 24497265712 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2983 89.90% 89.90% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 335 10.10% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3318 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12855 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 12855 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12694 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 12694 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 16170 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66060204 # ITB inst hits -system.cpu.itb.inst_misses 12855 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3318 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3318 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 16012 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 65985862 # ITB inst hits +system.cpu.itb.inst_misses 12694 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -549,21 +567,21 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3013 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3015 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2175 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2167 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66073059 # ITB inst accesses -system.cpu.itb.hits 66060204 # DTB hits -system.cpu.itb.misses 12855 # DTB misses -system.cpu.itb.accesses 66073059 # DTB accesses +system.cpu.itb.inst_accesses 65998556 # ITB inst accesses +system.cpu.itb.hits 65985862 # DTB hits +system.cpu.itb.misses 12694 # DTB misses +system.cpu.itb.accesses 65998556 # DTB accesses system.cpu.numPwrStateTransitions 6076 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887319797.866359 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17420812025.908409 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887100825.703094 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17420756349.556362 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state @@ -571,91 +589,91 @@ system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499973328096 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499972215488 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 132175550082 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 264351157 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 134100636014 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2695012308486 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 268201326 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 105007140 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184198118 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46859222 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33067367 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 149125653 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6062128 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 177509 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 342285 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 500656 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 149 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66059105 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1061874 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6140 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 258192520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.869926 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.232240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 105037035 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 183958233 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46887151 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33089572 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151917777 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6065436 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 178887 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8852 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338530 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 869885 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 153 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65984793 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 962400 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5953 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 261383837 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.858435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.227931 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 159207105 61.66% 61.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29153243 11.29% 72.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14041371 5.44% 78.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55790801 21.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 162469808 62.16% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29156945 11.15% 73.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14047249 5.37% 78.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55709835 21.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 258192520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.177261 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.696793 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78121728 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 109293057 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64347286 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3858820 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2571629 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3404933 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 467397 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157054266 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3508469 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2571629 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83876272 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10707182 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 75777880 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62454434 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22805123 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146493829 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 914752 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 447933 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 65579 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 19295 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 20059867 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150297562 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 677265731 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164029738 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11047 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141819290 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8478266 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2841903 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2646616 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13881588 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26350743 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21216202 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1694356 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2155521 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143287156 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2116266 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143106706 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 261772 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8147939 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14286308 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 122067 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 258192520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.554264 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.878016 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 261383837 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.174821 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.685896 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78154489 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112430645 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64386105 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3839531 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2573067 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3403885 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 467719 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157074107 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3510025 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2573067 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83905287 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11250556 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76371084 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62477293 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24806550 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146503885 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 915767 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 476463 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 65809 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19068 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22053632 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150297963 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 677315873 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164027698 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11061 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141834071 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8463886 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2844043 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2648878 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13862484 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26350148 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21217553 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1695311 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2061783 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143296271 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143117357 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 261040 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8140399 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14276109 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121662 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 261383837 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.547537 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.874444 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 169987358 65.84% 65.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45210540 17.51% 83.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31907168 12.36% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10268019 3.98% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 819402 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 173081384 66.22% 66.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45405843 17.37% 83.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31801280 12.17% 95.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10272399 3.93% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 822898 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -663,44 +681,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 258192520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 261383837 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7338606 32.76% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5623411 25.10% 57.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9440852 42.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7335509 32.77% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5621614 25.12% 57.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9424915 42.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95896760 67.01% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 115009 0.08% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95907816 67.01% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114378 0.08% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued @@ -724,99 +742,99 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8592 0.01% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8550 0.01% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26141404 18.27% 85.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20942604 14.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26140422 18.27% 85.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20943854 14.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143106706 # Type of FU issued -system.cpu.iq.rate 0.541351 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22402901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156547 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 567034934 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153556562 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140052264 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35671 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13288 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11499 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165483986 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23284 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324130 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143117357 # Type of FU issued +system.cpu.iq.rate 0.533619 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22382070 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156390 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 570225766 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153558624 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140063898 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35895 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13316 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11500 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165473596 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23494 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 325086 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1434023 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 698 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18538 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 619510 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1430934 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 704 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18603 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 620075 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88631 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6598 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88534 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6404 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2571629 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 994929 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 316385 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145584227 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2573067 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1155549 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 418674 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145593643 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26350743 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21216202 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1093451 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17658 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 280514 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18538 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 277676 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 470698 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 748374 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142207045 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25746206 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 827350 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26350148 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21217553 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1093742 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17678 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 382838 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18603 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 276771 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 470806 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 747577 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142219738 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25746846 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 826473 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 180805 # number of nop insts executed -system.cpu.iew.exec_refs 46576895 # number of memory reference insts executed -system.cpu.iew.exec_branches 26509940 # Number of branches executed -system.cpu.iew.exec_stores 20830689 # Number of stores executed -system.cpu.iew.exec_rate 0.537948 # Inst execution rate -system.cpu.iew.wb_sent 141837731 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140063763 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63261975 # num instructions producing a value -system.cpu.iew.wb_consumers 95760288 # num instructions consuming a value -system.cpu.iew.wb_rate 0.529840 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660628 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7362260 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1994199 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 714821 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255299551 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.538232 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.139550 # Number of insts commited each cycle +system.cpu.iew.exec_nop 180657 # number of nop insts executed +system.cpu.iew.exec_refs 46578356 # number of memory reference insts executed +system.cpu.iew.exec_branches 26518178 # Number of branches executed +system.cpu.iew.exec_stores 20831510 # Number of stores executed +system.cpu.iew.exec_rate 0.530272 # Inst execution rate +system.cpu.iew.wb_sent 141851208 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140075398 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63278837 # num instructions producing a value +system.cpu.iew.wb_consumers 95827539 # num instructions consuming a value +system.cpu.iew.wb_rate 0.522277 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660341 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 7356149 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995053 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 714141 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258490005 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.531655 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.132637 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 181839086 71.23% 71.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43295063 16.96% 88.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15470047 6.06% 94.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4367483 1.71% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6400805 2.51% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1643674 0.64% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 799411 0.31% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 417134 0.16% 99.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1066848 0.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 184915208 71.54% 71.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43409459 16.79% 88.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15465173 5.98% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4364887 1.69% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6512039 2.52% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1543037 0.60% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 797927 0.31% 99.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 416081 0.16% 99.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1066194 0.41% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255299551 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113310545 # Number of instructions committed -system.cpu.commit.committedOps 137410384 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 258490005 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113327954 # Number of instructions committed +system.cpu.commit.committedOps 137427488 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45513412 # Number of memory references committed -system.cpu.commit.loads 24916720 # Number of loads committed -system.cpu.commit.membars 814165 # Number of memory barriers committed -system.cpu.commit.branches 26044798 # Number of branches committed +system.cpu.commit.refs 45516692 # Number of memory references committed +system.cpu.commit.loads 24919214 # Number of loads committed +system.cpu.commit.membars 814556 # Number of memory barriers committed +system.cpu.commit.branches 26054279 # Number of branches committed system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120233477 # Number of committed integer instructions. -system.cpu.commit.function_calls 4891928 # Number of function calls committed. +system.cpu.commit.int_insts 120246700 # Number of committed integer instructions. +system.cpu.commit.function_calls 4895002 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91774855 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 113526 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91789332 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112915 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -840,689 +858,689 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8591 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8549 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24916720 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20596692 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24919214 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20597478 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137410384 # Class of committed instruction -system.cpu.commit.bw_lim_events 1066848 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 376774257 # The number of ROB reads -system.cpu.rob.rob_writes 292425270 # The number of ROB writes -system.cpu.timesIdled 893722 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6158637 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5391355036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113155640 # Number of Instructions Simulated -system.cpu.committedOps 137255479 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.336173 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.336173 # CPI: Total CPI of All Threads -system.cpu.ipc 0.428050 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.428050 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155596461 # number of integer regfile reads -system.cpu.int_regfile_writes 88540193 # number of integer regfile writes -system.cpu.fp_regfile_reads 9674 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137427488 # Class of committed instruction +system.cpu.commit.bw_lim_events 1066194 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 379949809 # The number of ROB reads +system.cpu.rob.rob_writes 292448043 # The number of ROB writes +system.cpu.timesIdled 895006 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6817489 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5390024564 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113173049 # Number of Instructions Simulated +system.cpu.committedOps 137272583 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.369834 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.369834 # CPI: Total CPI of All Threads +system.cpu.ipc 0.421971 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.421971 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155600043 # number of integer regfile reads +system.cpu.int_regfile_writes 88544133 # number of integer regfile writes +system.cpu.fp_regfile_reads 9688 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502394909 # number of cc regfile reads -system.cpu.cc_regfile_writes 53149715 # number of cc regfile writes -system.cpu.misc_regfile_reads 449419252 # number of misc regfile reads -system.cpu.misc_regfile_writes 1520020 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 839084 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954165 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40069527 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 839596 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.724771 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 270911500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954165 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502437138 # number of cc regfile reads +system.cpu.cc_regfile_writes 53153343 # number of cc regfile writes +system.cpu.misc_regfile_reads 452546223 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521066 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 835143 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.950856 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40081033 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 835655 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.963613 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 291735500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.950856 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999904 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999904 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179200286 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179200286 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23273566 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23273566 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15547100 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15547100 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 345314 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 345314 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441102 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441102 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 459566 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 459566 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38820666 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38820666 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39165980 # number of overall hits -system.cpu.dcache.overall_hits::total 39165980 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 709196 # number of ReadReq misses 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miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016566 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019101 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019101 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13595.100454 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13595.100454 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15563.335721 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15563.335721 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41600 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27029.175709 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27029.175709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25106.579632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25106.579632 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201738.105182 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201738.105182 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.141098 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.141098 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1887810 # number of replacements -system.cpu.icache.tags.tagsinuse 511.341026 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64075895 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1888322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.932716 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13715039500 # Cycle when the warmup percentage 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LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126955500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 192000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 192000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086794482 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21086794482 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22732868482 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22732868482 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281936500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281936500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281936500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281936500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017171 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017171 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227725 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227725 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27383.125645 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27383.125645 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201816.317024 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201816.317024 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106997.606922 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106997.606922 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1888653 # number of replacements +system.cpu.icache.tags.tagsinuse 511.315245 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64000443 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1889165 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.877635 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 14109307500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.315245 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998663 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998663 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 67944454 # Number of tag accesses -system.cpu.icache.tags.data_accesses 67944454 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 64075895 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64075895 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64075895 # number of demand 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demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26984355494 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26984355494 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26984355494 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66056101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66056101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66056101 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66056101 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66056101 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66056101 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029978 # miss rate for ReadReq accesses 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rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000697 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000336 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001788 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001788 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455508 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455508 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010493 # mshr miss rate for ReadCleanReq accesses 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# mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010493 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177553 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060353 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 257142.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84320.293127 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84320.293127 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97913.358220 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97913.358220 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106791.145912 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106791.145912 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97913.358220 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86331.776488 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87717.862217 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97913.358220 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86331.776488 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87717.862217 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189315.995759 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178756.605929 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100370.271329 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98866.420933 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5483646 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758798 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 45074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 178 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 178 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 129622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2559974 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2557224 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 791350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1887810 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 151157 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 542004 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 4368 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2641503 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130873 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8472029 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241718384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98487773 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 217428 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 340464457 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 139207 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6232532 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2995964 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025358 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.157210 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 784270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1888653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 148972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2801 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296581 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296581 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 539301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5673012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629673 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8459795 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241826896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98094045 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40180 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209708 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340170829 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135300 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5917976 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2986955 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025939 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.158953 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2919992 97.46% 97.46% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 75972 2.54% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2909477 97.41% 97.41% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 77478 2.59% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2995964 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5405204997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2986955 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5400390498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 383377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 295626 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2836467127 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2837677759 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1305988986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1300010143 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18982487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18878489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 76565899 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75816896 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30182 # Transaction distribution -system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 30169 # Transaction distribution +system.iobus.trans_dist::ReadResp 30169 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1545,9 +1563,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -1568,22 +1586,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43094500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480117 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43090000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 649500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 649000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1605,56 +1623,56 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6172500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6166500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33854000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33827500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187760330 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187658622 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 1.000676 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36410 # number of replacements +system.iocache.tags.tagsinuse 1.001835 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 252706881000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000676 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 253680812000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.001835 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062615 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062615 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328113 # Number of tag accesses -system.iocache.tags.data_accesses 328113 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses -system.iocache.ReadReq_misses::total 233 # number of ReadReq misses +system.iocache.tags.tag_accesses 327996 # Number of tag accesses +system.iocache.tags.data_accesses 327996 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses +system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36457 # number of demand (read+write) misses -system.iocache.demand_misses::total 36457 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36457 # number of overall misses -system.iocache.overall_misses::total 36457 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28964877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28964877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4277512453 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4277512453 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4306477330 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4306477330 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4306477330 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4306477330 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses +system.iocache.demand_misses::total 36444 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36444 # number of overall misses +system.iocache.overall_misses::total 36444 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 35726876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 35726876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4357072746 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4357072746 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4392799622 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4392799622 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4392799622 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4392799622 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36457 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36457 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36457 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36457 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36444 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36444 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36444 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36444 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1663,38 +1681,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124312.776824 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118124.841046 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118124.841046 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 162394.890909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162394.890909 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120281.381018 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120281.381018 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120535.605916 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120535.605916 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120535.605916 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120535.605916 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36457 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36457 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36457 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36457 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17314877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17314877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464212681 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2464212681 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2481527558 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2481527558 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2481527558 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2481527558 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36444 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 24726876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 24726876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2543825241 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2543825241 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2568552117 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2568552117 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2568552117 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2568552117 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1703,90 +1721,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 349590 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 144366 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112394.890909 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112394.890909 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70224.857581 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70224.857581 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70479.423691 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70479.423691 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70479.423691 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70479.423691 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 339259 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 139343 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 34130 # Transaction distribution -system.membus.trans_dist::ReadResp 68622 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 34136 # Transaction distribution +system.membus.trans_dist::ReadResp 67481 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131362 # Transaction distribution -system.membus.trans_dist::CleanEvict 8484 # Transaction distribution -system.membus.trans_dist::UpgradeReq 130 # Transaction distribution +system.membus.trans_dist::WritebackDirty 126432 # Transaction distribution +system.membus.trans_dist::CleanEvict 8077 # Transaction distribution +system.membus.trans_dist::UpgradeReq 126 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 138891 # Transaction distribution -system.membus.trans_dist::ReadExResp 138891 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34493 # Transaction distribution +system.membus.trans_dist::ReadExReq 134974 # Transaction distribution +system.membus.trans_dist::ReadExResp 134974 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33346 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 573007 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72895 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72895 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557589 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72869 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 630458 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17222620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17385997 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16583932 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16747309 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19703117 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 497 # Total snoops (count) -system.membus.snoopTraffic 31680 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 271454 # Request fanout histogram -system.membus.snoop_fanout::mean 0.017933 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.132708 # Request fanout histogram +system.membus.pkt_size::total 19064429 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 484 # Total snoops (count) +system.membus.snoopTraffic 30848 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 266392 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019141 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137021 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 266586 98.21% 98.21% # Request fanout histogram -system.membus.snoop_fanout::1 4868 1.79% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261293 98.09% 98.09% # Request fanout histogram +system.membus.snoop_fanout::1 5099 1.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 271454 # Request fanout histogram -system.membus.reqLayer0.occupancy 84464500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 266392 # Request fanout histogram +system.membus.reqLayer0.occupancy 84425500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1723499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1729999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 908168519 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 876952960 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1012308500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 984786250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1273123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1178374 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1818,29 +1836,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini index ce640090c..bcf1aa128 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -208,7 +208,7 @@ useIndirect=true [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -688,7 +688,7 @@ opClass=InstPrefetch [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -748,7 +748,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -820,7 +820,7 @@ port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -1024,7 +1024,7 @@ useIndirect=true [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1504,7 +1504,7 @@ opClass=InstPrefetch [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1564,7 +1564,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -1636,7 +1636,7 @@ port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -1783,7 +1783,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -1829,7 +1829,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1927,27 +1927,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1967,6 +1967,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1976,7 +1977,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1998,9 +1999,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -2353,7 +2354,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -2666,10 +2667,11 @@ pio=system.iobus.master[21] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain -conf_table_reported=true +conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2677,7 +2679,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2908,6 +2910,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2915,7 +2918,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout index 2aa1c9ae0..d0bf1da85 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:03:52 -gem5 executing on e108600-lin, pid 24173 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:43:00 +gem5 executing on e108600-lin, pid 17333 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor-dual Selected 64-bit ARM architecture, updating default disk image... @@ -15,4 +15,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47445489241000 because m5_exit instruction encountered +Exiting @ tick 47554910274000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 539176c94..202c4ef0d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.276773 # Number of seconds simulated -sim_ticks 47276772827000 # Number of ticks simulated -final_tick 47276772827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.554910 # Number of seconds simulated +sim_ticks 47554910274000 # Number of ticks simulated +final_tick 47554910274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146674 # Simulator instruction rate (inst/s) -host_op_rate 172507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7728246229 # Simulator tick rate (ticks/s) -host_mem_usage 772984 # Number of bytes of host memory used -host_seconds 6117.40 # Real time elapsed on the host -sim_insts 897262562 # Number of instructions simulated -sim_ops 1055295890 # Number of ops (including micro ops) simulated +host_inst_rate 172972 # Simulator instruction rate (inst/s) +host_op_rate 203472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9377554592 # Simulator tick rate (ticks/s) +host_mem_usage 769556 # Number of bytes of host memory used +host_seconds 5071.14 # Real time elapsed on the host +sim_insts 877166784 # Number of instructions simulated +sim_ops 1031833041 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 117376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 90560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7953664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13400200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 16005120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 165760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 157376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3942400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13075216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14708224 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 454784 # Number of bytes read from this memory -system.physmem.bytes_read::total 70070680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7953664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3942400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11896064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 81443392 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 127616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 113728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7300032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13854920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13786176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 105536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 93440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3887680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9545552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11958848 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory +system.physmem.bytes_read::total 61215640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7300032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3887680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11187712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74339904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 81463976 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1834 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1415 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 124276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 209391 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 250080 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2590 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 61600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 204313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 229816 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7106 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1094880 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1272553 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74360488 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 114063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 216496 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 215409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1460 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 60745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 149162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 186857 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory +system.physmem.num_reads::total 956520 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1161561 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1275127 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 168236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 283442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 338541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 83390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 276567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 311109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1482138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 168236 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 83390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 251626 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1722694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1164135 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 153507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 291346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 289900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 200727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 251475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1287262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 153507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 235259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1563243 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1723129 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1722694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 168236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 283877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 338541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 83390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 276568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 311109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3205266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1094880 # Number of read requests accepted -system.physmem.writeReqs 1275127 # Number of write requests accepted -system.physmem.readBursts 1094880 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1275127 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 70042240 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 30080 # Total number of bytes read from write queue -system.physmem.bytesWritten 81461504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 70070680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 81463976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 470 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1563676 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1563243 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 153507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 291778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 289900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 81751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 200727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 251475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2850939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 956520 # Number of read requests accepted +system.physmem.writeReqs 1164135 # Number of write requests accepted +system.physmem.readBursts 956520 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1164135 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61192448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24832 # Total number of bytes read from write queue +system.physmem.bytesWritten 74357824 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61215640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74360488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 388 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 60604 # Per bank write bursts -system.physmem.perBankRdBursts::1 71691 # Per bank write bursts -system.physmem.perBankRdBursts::2 59265 # Per bank write bursts -system.physmem.perBankRdBursts::3 66946 # Per bank write bursts -system.physmem.perBankRdBursts::4 67906 # Per bank write bursts -system.physmem.perBankRdBursts::5 80109 # Per bank write bursts -system.physmem.perBankRdBursts::6 61949 # Per bank write bursts -system.physmem.perBankRdBursts::7 69447 # Per bank write bursts -system.physmem.perBankRdBursts::8 60494 # Per bank write bursts -system.physmem.perBankRdBursts::9 115448 # Per bank write bursts -system.physmem.perBankRdBursts::10 56514 # Per bank write bursts -system.physmem.perBankRdBursts::11 69665 # Per bank write bursts -system.physmem.perBankRdBursts::12 63387 # Per bank write bursts -system.physmem.perBankRdBursts::13 66346 # Per bank write bursts -system.physmem.perBankRdBursts::14 64421 # Per bank write bursts -system.physmem.perBankRdBursts::15 60218 # Per bank write bursts -system.physmem.perBankWrBursts::0 77101 # Per bank write bursts -system.physmem.perBankWrBursts::1 84577 # Per bank write bursts -system.physmem.perBankWrBursts::2 74746 # Per bank write bursts -system.physmem.perBankWrBursts::3 81276 # Per bank write bursts -system.physmem.perBankWrBursts::4 79990 # Per bank write bursts -system.physmem.perBankWrBursts::5 87328 # Per bank write bursts -system.physmem.perBankWrBursts::6 77464 # Per bank write bursts -system.physmem.perBankWrBursts::7 81707 # Per bank write bursts -system.physmem.perBankWrBursts::8 78209 # Per bank write bursts -system.physmem.perBankWrBursts::9 81569 # Per bank write bursts -system.physmem.perBankWrBursts::10 73819 # Per bank write bursts -system.physmem.perBankWrBursts::11 80687 # Per bank write bursts -system.physmem.perBankWrBursts::12 78674 # Per bank write bursts -system.physmem.perBankWrBursts::13 80970 # Per bank write bursts -system.physmem.perBankWrBursts::14 77560 # Per bank write bursts -system.physmem.perBankWrBursts::15 77159 # Per bank write bursts +system.physmem.perBankRdBursts::0 50657 # Per bank write bursts +system.physmem.perBankRdBursts::1 60930 # Per bank write bursts +system.physmem.perBankRdBursts::2 49716 # Per bank write bursts +system.physmem.perBankRdBursts::3 55090 # Per bank write bursts +system.physmem.perBankRdBursts::4 56536 # Per bank write bursts +system.physmem.perBankRdBursts::5 68947 # Per bank write bursts +system.physmem.perBankRdBursts::6 58003 # Per bank write bursts +system.physmem.perBankRdBursts::7 60908 # Per bank write bursts +system.physmem.perBankRdBursts::8 53263 # Per bank write bursts +system.physmem.perBankRdBursts::9 106420 # Per bank write bursts +system.physmem.perBankRdBursts::10 50504 # Per bank write bursts +system.physmem.perBankRdBursts::11 59458 # Per bank write bursts +system.physmem.perBankRdBursts::12 56712 # Per bank write bursts +system.physmem.perBankRdBursts::13 60494 # Per bank write bursts +system.physmem.perBankRdBursts::14 55357 # Per bank write bursts +system.physmem.perBankRdBursts::15 53137 # Per bank write bursts +system.physmem.perBankWrBursts::0 68064 # Per bank write bursts +system.physmem.perBankWrBursts::1 74120 # Per bank write bursts +system.physmem.perBankWrBursts::2 68663 # Per bank write bursts +system.physmem.perBankWrBursts::3 72095 # Per bank write bursts +system.physmem.perBankWrBursts::4 73476 # Per bank write bursts +system.physmem.perBankWrBursts::5 80505 # Per bank write bursts +system.physmem.perBankWrBursts::6 71958 # Per bank write bursts +system.physmem.perBankWrBursts::7 74882 # Per bank write bursts +system.physmem.perBankWrBursts::8 69253 # Per bank write bursts +system.physmem.perBankWrBursts::9 72875 # Per bank write bursts +system.physmem.perBankWrBursts::10 68876 # Per bank write bursts +system.physmem.perBankWrBursts::11 75926 # Per bank write bursts +system.physmem.perBankWrBursts::12 72095 # Per bank write bursts +system.physmem.perBankWrBursts::13 75544 # Per bank write bursts +system.physmem.perBankWrBursts::14 71950 # Per bank write bursts +system.physmem.perBankWrBursts::15 71559 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 62 # Number of times write queue was full causing retry -system.physmem.totGap 47276770796500 # Total gap between requests +system.physmem.numWrRetry 408 # Number of times write queue was full causing retry +system.physmem.totGap 47554908178500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1094850 # Read request sizes (log2) +system.physmem.readPktSize::6 956490 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1272553 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 725931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 32959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 30077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 28140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 22148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1161561 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 589555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 157739 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 27945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 23391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 20914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1587 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -189,172 +189,188 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 67814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 70802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 73289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 75619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 78304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 78281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 81577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 85157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 81436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 87129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 77597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 71470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 67901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 212 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1013795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 149.441747 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 100.507639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.056675 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 662057 65.30% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 208347 20.55% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52181 5.15% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23884 2.36% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 17639 1.74% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11113 1.10% 96.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7357 0.73% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6249 0.62% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24968 2.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1013795 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 63452 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.247415 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 156.483425 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 63450 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 24143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 64206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 66032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 73352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 70410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 71450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 74135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 933 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 917155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 147.793592 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.753334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 195.501852 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 602356 65.68% 65.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 188931 20.60% 86.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45653 4.98% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20839 2.27% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15350 1.67% 95.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9574 1.04% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6849 0.75% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5486 0.60% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22117 2.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 917155 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 56545 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.908586 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 165.794592 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 56543 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 63452 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 63452 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.059825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.482738 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.878895 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 55385 87.29% 87.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2264 3.57% 90.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 727 1.15% 92.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 608 0.96% 92.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1019 1.61% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 457 0.72% 95.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 338 0.53% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 295 0.46% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 198 0.31% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 179 0.28% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 127 0.20% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 154 0.24% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 464 0.73% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 118 0.19% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 142 0.22% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 119 0.19% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 89 0.14% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 71 0.11% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 72 0.11% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 80 0.13% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 103 0.16% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 73 0.12% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 46 0.07% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 54 0.09% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 48 0.08% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 39 0.06% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 53 0.08% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 25 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 49 0.08% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 20 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 13 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 63452 # Writes before turning the bus around for reads -system.physmem.totQLat 38795138463 # Total ticks spent queuing -system.physmem.totMemAccLat 59315325963 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5472050000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35448.45 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 56545 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 56545 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.547193 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.712168 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.106429 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 48673 86.08% 86.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2227 3.94% 90.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 713 1.26% 91.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 569 1.01% 92.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 930 1.64% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 406 0.72% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 286 0.51% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 280 0.50% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 183 0.32% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 127 0.22% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 115 0.20% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 143 0.25% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 579 1.02% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 140 0.25% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 130 0.23% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 128 0.23% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 106 0.19% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 75 0.13% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 85 0.15% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 94 0.17% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 75 0.13% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 62 0.11% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 61 0.11% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 71 0.13% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 39 0.07% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 37 0.07% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 45 0.08% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 34 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 51 0.09% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 18 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 12 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 17 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 56545 # Writes before turning the bus around for reads +system.physmem.totQLat 49127716705 # Total ticks spent queuing +system.physmem.totMemAccLat 67055191705 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4780660000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51381.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54198.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70131.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing -system.physmem.readRowHits 817920 # Number of row buffer hits during reads -system.physmem.writeRowHits 535530 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.74 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 42.07 # Row buffer hit rate for writes -system.physmem.avgGap 19947945.64 # Average gap between requests -system.physmem.pageHitRate 57.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3880003680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2117065500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4195752600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4174344720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1190314271070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27321927289500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31614497574750 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.711016 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45452122728628 # Time in different power states -system.physmem_0.memoryStateTime::REF 1578675280000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 245973030122 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3784278960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2064834750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4340583000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4073632560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1186461286245 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27325307092500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31613920555695 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.698811 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45457733356018 # Time in different power states -system.physmem_1.memoryStateTime::REF 1578675280000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 240362584982 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing +system.physmem.readRowHits 713884 # Number of row buffer hits during reads +system.physmem.writeRowHits 486930 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.91 # Row buffer hit rate for writes +system.physmem.avgGap 22424632.10 # Average gap between requests +system.physmem.pageHitRate 56.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3312517320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1760633325 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3290019180 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3047242860 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 39654114240.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 43514746200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2086179840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 77547983010 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 55697482080 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11319929946090 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11549857795695 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.874137 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47454012976233 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3696049077 # Time in different power states +system.physmem_0.memoryStateTime::REF 16847240000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 47138905885000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 145045339612 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80353958440 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 170061801871 # Time in different power states +system.physmem_1.actEnergy 3235997940 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1719969900 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3536763300 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3017567160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 38496747120.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 44079949650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2012350560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 72751641060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 54144086400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11323086477345 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11546099446905 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.795105 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47452962329328 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3512995347 # Time in different power states +system.physmem_1.memoryStateTime::REF 16356664000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 47152420144750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 141000345458 # Time in different power states +system.physmem_1.memoryStateTime::ACT 82076677575 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 159543446870 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory @@ -370,41 +386,41 @@ system.realview.nvmem.num_reads::cpu1.data 1 # system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 132137665 # Number of BP lookups -system.cpu0.branchPred.condPredicted 93617551 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5999845 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98810350 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 69427031 # Number of BTB hits +system.cpu0.branchPred.lookups 137627857 # Number of BP lookups +system.cpu0.branchPred.condPredicted 96352530 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6353129 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 102612546 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 71378761 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.262914 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15260285 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1044115 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 3387017 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2259695 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1127322 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 409659 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 69.561436 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16463463 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1088270 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 3669510 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2436336 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1233174 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 447439 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -434,64 +450,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 271762 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 271762 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10351 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74846 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 271762 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 271762 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 271762 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85197 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23819.195512 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22123.263295 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14060.055266 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 84296 98.94% 98.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 776 0.91% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 35 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 35 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85197 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 74846 87.85% 87.85% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10351 12.15% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85197 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271762 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 282889 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 282889 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9418 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 82700 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 282889 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 282889 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 282889 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 92118 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24516.006644 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22528.646157 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 18042.498572 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 90947 98.73% 98.73% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 867 0.94% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 159 0.17% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 92118 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1049600704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1049600704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1049600704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 82700 89.78% 89.78% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9418 10.22% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 92118 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 282889 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271762 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85197 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 282889 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92118 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85197 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 356959 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92118 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 375007 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 82756248 # DTB read hits -system.cpu0.dtb.read_misses 224730 # DTB read misses -system.cpu0.dtb.write_hits 74117187 # DTB write hits -system.cpu0.dtb.write_misses 47032 # DTB write misses +system.cpu0.dtb.read_hits 87675894 # DTB read hits +system.cpu0.dtb.read_misses 234519 # DTB read misses +system.cpu0.dtb.write_hits 78239753 # DTB write hits +system.cpu0.dtb.write_misses 48370 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34573 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2108 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9506 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38151 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2038 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9397 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11030 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 82980978 # DTB read accesses -system.cpu0.dtb.write_accesses 74164219 # DTB write accesses +system.cpu0.dtb.perms_faults 11689 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 87910413 # DTB read accesses +system.cpu0.dtb.write_accesses 78288123 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 156873435 # DTB hits -system.cpu0.dtb.misses 271762 # DTB misses -system.cpu0.dtb.accesses 157145197 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 165915647 # DTB hits +system.cpu0.dtb.misses 282889 # DTB misses +system.cpu0.dtb.accesses 166198536 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -521,906 +539,899 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 60398 # Table walker walks requested -system.cpu0.itb.walker.walksLong 60398 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 589 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51882 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 60398 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 60398 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 60398 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52471 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25793.819443 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24019.609428 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 15089.787613 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 46836 89.26% 89.26% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 4750 9.05% 98.31% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 22 0.04% 98.36% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 772 1.47% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 15 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 26 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 9 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52471 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51882 98.88% 98.88% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 589 1.12% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52471 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 69273 # Table walker walks requested +system.cpu0.itb.walker.walksLong 69273 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 583 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61330 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 69273 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 69273 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 69273 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 61913 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26255.972090 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24021.087370 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 22669.077424 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 60695 98.03% 98.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 852 1.38% 99.41% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 248 0.40% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 49 0.08% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 11 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 39 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 61913 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 1048830204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1048830204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1048830204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 61330 99.06% 99.06% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 583 0.94% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 61913 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60398 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60398 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 69273 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 69273 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52471 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52471 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 112869 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 234456044 # ITB inst hits -system.cpu0.itb.inst_misses 60398 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61913 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61913 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 131186 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 244690597 # ITB inst hits +system.cpu0.itb.inst_misses 69273 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24118 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 27059 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 160109 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 167788 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 234516442 # ITB inst accesses -system.cpu0.itb.hits 234456044 # DTB hits -system.cpu0.itb.misses 60398 # DTB misses -system.cpu0.itb.accesses 234516442 # DTB accesses -system.cpu0.numPwrStateTransitions 8178 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 4089 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 11447226771.455124 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 162386644618.467285 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 2836 69.36% 69.36% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 1230 30.08% 99.44% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.46% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.51% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.56% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.58% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 14 0.34% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 244759870 # ITB inst accesses +system.cpu0.itb.hits 244690597 # DTB hits +system.cpu0.itb.misses 69273 # DTB misses +system.cpu0.itb.accesses 244759870 # DTB accesses +system.cpu0.numPwrStateTransitions 27904 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13952 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3372797482.084218 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 110921496988.059006 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3863 27.69% 27.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10067 72.15% 99.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.92% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 8 0.06% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7470355608744 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 4089 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 469062558520 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46807710268480 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 938130839 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7351146409252 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13952 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 497639803961 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47057270470039 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 995321471 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 430200528 # Number of instructions committed -system.cpu0.committedOps 505771410 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 45690974 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 3904 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93616054941 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.180683 # CPI: cycles per instruction -system.cpu0.ipc 0.458572 # IPC: instructions per cycle +system.cpu0.committedInsts 452001209 # Number of instructions committed +system.cpu0.committedOps 531851100 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 46239027 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 5092 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 94115325169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.202033 # CPI: cycles per instruction +system.cpu0.ipc 0.454126 # IPC: instructions per cycle system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 351125189 69.42% 69.42% # Class of committed instruction -system.cpu0.op_class_0::IntMult 1073769 0.21% 69.64% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 52983 0.01% 69.65% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 8 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 13 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 21 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 68782 0.01% 69.66% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction -system.cpu0.op_class_0::MemRead 79655364 15.75% 85.41% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 73795280 14.59% 100.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 368287155 69.25% 69.25% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1118982 0.21% 69.46% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 57276 0.01% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 8 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 13 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 21 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 85306 0.02% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::MemRead 84402084 15.87% 85.35% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 77900254 14.65% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 505771410 # Class of committed instruction +system.cpu0.op_class_0::total 531851100 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4089 # number of quiesce instructions executed -system.cpu0.tickCycles 697846091 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 240284748 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5497391 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.377946 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148839422 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5497903 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.072035 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.377946 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977301 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.977301 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 13952 # number of quiesce instructions executed +system.cpu0.tickCycles 729574114 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 265747357 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5787900 # number of replacements +system.cpu0.dcache.tags.tagsinuse 490.209920 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 157471988 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5788412 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.204696 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5354308000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.209920 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.957441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 316768421 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 316768421 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 75978032 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75978032 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68482955 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 68482955 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 264842 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 264842 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 244065 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 244065 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1687572 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1687572 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1654235 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1654235 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 144705052 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 144705052 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 144969894 # number of overall hits -system.cpu0.dcache.overall_hits::total 144969894 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3066734 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3066734 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2419958 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2419958 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670609 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 670609 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 786129 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 786129 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148878 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 148878 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 181031 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 181031 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6272821 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6272821 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6943430 # number of overall misses -system.cpu0.dcache.overall_misses::total 6943430 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47243422000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 47243422000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 49248110500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 49248110500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26231986000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 26231986000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2187373500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2187373500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4323764500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4323764500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2754000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2754000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 122723518500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 122723518500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 122723518500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 122723518500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79044766 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79044766 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 70902913 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 70902913 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935451 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 935451 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1030194 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1030194 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1836450 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1836450 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1835266 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1835266 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 150977873 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 150977873 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 151913324 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 151913324 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038797 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.038797 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.034131 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.034131 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716883 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.716883 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763088 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763088 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081068 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081068 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098640 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098640 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045707 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.045707 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15405.125453 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15405.125453 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20350.812080 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20350.812080 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33368.551472 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33368.551472 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14692.389070 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.389070 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23884.111009 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23884.111009 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 334937152 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 334937152 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 80549957 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80549957 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72496805 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72496805 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 269794 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 269794 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177007 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 177007 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1734640 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1734640 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1715473 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1715473 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 153223769 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153223769 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153493563 # number of overall hits +system.cpu0.dcache.overall_hits::total 153493563 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3263198 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3263198 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2445366 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2445366 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 673099 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 673099 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 844507 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 844507 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 169054 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 169054 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187078 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 187078 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6553071 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6553071 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7226170 # number of overall misses +system.cpu0.dcache.overall_misses::total 7226170 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52395902500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 52395902500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52490790500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 52490790500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27335813500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 27335813500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2555333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2555333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4463485500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4463485500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2023000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2023000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 132222506500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 132222506500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 132222506500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 132222506500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83813155 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83813155 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74942171 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74942171 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 942893 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 942893 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1021514 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1021514 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1903694 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1903694 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1902551 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1902551 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 159776840 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 159776840 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 160719733 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 160719733 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038934 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.038934 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032630 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.032630 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.713866 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.713866 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.826721 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.826721 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088803 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088803 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098330 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098330 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041014 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041014 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044961 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.044961 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16056.611490 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16056.611490 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21465.412744 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21465.412744 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32368.960234 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32368.960234 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15115.486768 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15115.486768 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23858.954554 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23858.954554 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19564.326561 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19564.326561 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17674.768594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17674.768594 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20177.182042 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20177.182042 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18297.729849 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18297.729849 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5497393 # number of writebacks -system.cpu0.dcache.writebacks::total 5497393 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200047 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 200047 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012976 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1012976 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 94 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 94 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39271 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39271 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 90 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 90 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1213117 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1213117 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1213117 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1213117 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2866687 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2866687 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1406982 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1406982 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 668415 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 668415 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 786035 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 786035 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 109607 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 109607 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180941 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 180941 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5059704 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5059704 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5728119 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5728119 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20634 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22275 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 42909 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39457015000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 39457015000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27671793000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27671793000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15966528000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15966528000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25439405000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25439405000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1452927000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1452927000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4140525000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4140525000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2476500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2476500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 92568213000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 92568213000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108534741000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 108534741000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4015086500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4015086500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4015086500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4015086500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036267 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036267 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019844 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019844 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714538 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714538 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.762997 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.762997 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059684 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059684 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098591 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098591 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033513 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033513 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037706 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.037706 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13763.977372 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13763.977372 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19667.481887 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19667.481887 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23887.147954 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23887.147954 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32364.214062 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32364.214062 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13255.786583 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13255.786583 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22883.287923 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22883.287923 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5787917 # number of writebacks +system.cpu0.dcache.writebacks::total 5787917 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 205447 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 205447 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1015907 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1015907 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 99 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 99 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45884 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45884 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 37 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 37 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1221453 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1221453 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1221453 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1221453 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3057751 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3057751 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1429459 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1429459 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 670780 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 670780 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 844408 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 844408 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123170 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123170 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187041 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 187041 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5331618 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5331618 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6002398 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6002398 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31212 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30755 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 61967 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44254087500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44254087500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29600010500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29600010500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15858321000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15858321000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26484603000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26484603000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1676878500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1676878500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4275603000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4275603000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1773000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1773000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 100338701000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 100338701000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116197022000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 116197022000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6038825000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6038825000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6038825000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6038825000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036483 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036483 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019074 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019074 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.711406 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.711406 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.826624 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.826624 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064701 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064701 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098311 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098311 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033369 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037347 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.037347 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14472.757102 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14472.757102 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20707.142003 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20707.142003 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23641.612749 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23641.612749 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31364.699292 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31364.699292 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13614.341966 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13614.341966 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22859.175261 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22859.175261 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18295.183473 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18295.183473 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.710584 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.710584 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194585.950373 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194585.950373 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93572.129390 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93572.129390 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 9280608 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932285 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 225009210 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9281120 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.243756 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 22204306000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932285 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18819.559278 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18819.559278 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19358.433413 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19358.433413 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193477.668845 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193477.668845 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97452.272984 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97452.272984 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 9773833 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.928996 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 234741496 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9774345 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.016085 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 22886662000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.928996 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999861 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 477861809 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 477861809 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 225009210 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 225009210 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 225009210 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 225009210 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 225009210 # number of overall hits -system.cpu0.icache.overall_hits::total 225009210 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9281130 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9281130 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9281130 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9281130 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9281130 # number of overall misses -system.cpu0.icache.overall_misses::total 9281130 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94226606500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 94226606500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 94226606500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 94226606500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 94226606500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 94226606500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290340 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 234290340 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 234290340 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 234290340 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 234290340 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 234290340 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039614 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039614 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039614 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039614 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039614 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039614 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10152.492908 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10152.492908 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10152.492908 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10152.492908 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 498806059 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 498806059 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 234741496 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 234741496 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 234741496 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 234741496 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 234741496 # number of overall hits +system.cpu0.icache.overall_hits::total 234741496 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9774356 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9774356 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9774356 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9774356 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9774356 # number of overall misses +system.cpu0.icache.overall_misses::total 9774356 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99441985000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 99441985000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 99441985000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 99441985000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 99441985000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 99441985000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 244515852 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 244515852 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 244515852 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 244515852 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 244515852 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 244515852 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039974 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039974 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039974 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039974 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039974 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.039974 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10173.763366 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10173.763366 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10173.763366 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10173.763366 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10173.763366 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10173.763366 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 9280608 # number of writebacks -system.cpu0.icache.writebacks::total 9280608 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9281130 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9281130 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9281130 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9281130 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9281130 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9281130 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 52300 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 52300 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89586042000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 89586042000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89586042000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 89586042000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89586042000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 89586042000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039614 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.039614 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.039614 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9652.492962 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197 # 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average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7608993 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7610336 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1188 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 942183 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.933609 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002426 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001343 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.951592 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 376 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15477 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 104 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 124 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 121 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 33 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1649 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4407 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5650 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3577 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022949 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.944641 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 507607175 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 507607175 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 496900 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 154788 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 651688 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3675506 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3675506 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 11099665 # 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number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33660637494 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33660637494 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 333947500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 333947500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 614702000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 331371000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23732034500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 47311513493 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 71989620993 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 614702000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 331371000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23732034500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 47311513493 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 71989620993 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 516703 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164407 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 681110 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3675506 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3675506 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 11099665 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 117 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1727 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6563 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4041 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2911 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021484 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.940552 # 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number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 30755 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 114251 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 342540500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 908484500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36299233693 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36299233693 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4539562995 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4539562995 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2868254998 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2868254998 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1441497 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1441497 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12630779498 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12630779498 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20869901000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20869901000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 31074032995 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 31074032995 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19885865000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19885865000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 342540500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20869901000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43704812493 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 65483197993 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 342540500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20869901000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43704812493 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36299233693 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 101782431686 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788958500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10532292500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788958500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10532292500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042803 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999996 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999996 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.230062 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.230062 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073593 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.261534 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261534 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.742235 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.742235 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.130924 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233793 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233793 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071429 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.253235 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253235 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.713501 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.713501 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248642 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.127511 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248642 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.183830 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26207.203520 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49101.672698 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18404.407019 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18404.407019 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15359.648034 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15359.648034 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 672666.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672666.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40319.771067 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40319.771067 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28744.946005 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29230.500946 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29230.500946 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33177.583784 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33177.583784 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30556.137615 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35893.492134 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186571.047785 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113364.020896 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89717.937962 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86841.490825 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 30377137 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 15497883 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2826 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 666100 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 666086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 826394 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13852976 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 22275 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 22275 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5277668 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 11102490 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1369040 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 998456 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 452524 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 496609 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1203701 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1179860 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9281130 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4723846 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 838465 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 784086 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 27947466 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17813968 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 344869 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1089699 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 47196002 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1191298304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 667170422 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1315256 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4133624 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1863917606 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5747559 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 110232304 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 21648150 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.044453 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.206103 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177834 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28692.306478 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46367.465055 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18431.480243 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18431.480243 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15335.309769 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.309769 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 288299.400000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 288299.400000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45350.934602 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45350.934602 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29892.205646 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31860.705679 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31860.705679 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33081.631635 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33081.631635 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34857.298205 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33011.367895 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34857.298205 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36790.834279 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185472.206203 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126141.282217 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93420.021947 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 92185.560739 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 31945858 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16286466 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2971 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 662323 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 662303 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 20 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 897088 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14618500 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 30756 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 30755 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5466694 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 11729628 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1381452 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1000780 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 445154 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 338634 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 499902 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1222912 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1199223 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9774356 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4899750 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 895142 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 842487 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29427111 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18719100 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 397503 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1155819 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 49699533 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1254430144 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699985190 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1523344 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4394512 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1960333190 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5744069 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 111836388 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 22520641 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.042476 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.201677 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 20685836 95.55% 95.55% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 962300 4.45% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 21564077 95.75% 95.75% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 956544 4.25% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 20 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21648150 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 30255355989 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 22520641 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 31868357980 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 202143120 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 188944290 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14002739292 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14742648604 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7861824025 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8252120363 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 180564794 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 207185798 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 573087816 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 606624760 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 142890193 # Number of BP lookups -system.cpu1.branchPred.condPredicted 101173603 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6378415 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 107083119 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 74895456 # Number of BTB hits +system.cpu1.branchPred.lookups 130393488 # Number of BP lookups +system.cpu1.branchPred.condPredicted 92735412 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5902942 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 97710710 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 68499677 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 69.941422 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16732142 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1061167 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3812146 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2601182 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1210964 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 435637 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 70.104574 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15029088 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 982146 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3431599 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2322480 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1109119 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 398100 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1450,63 +1461,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 301450 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 301450 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14052 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94528 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 301450 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 301450 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 301450 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 108580 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23842.945294 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21967.326975 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15932.247293 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 107036 98.58% 98.58% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1312 1.21% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 57 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.06% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 74 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 108580 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -588118056 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -588118056 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -588118056 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 94528 87.06% 87.06% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 14052 12.94% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 108580 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 301450 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 266586 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9178 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75276 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84454 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23652.319606 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21901.867132 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15135.594089 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 83574 98.96% 98.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 653 0.77% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 133 0.16% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 39 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 30 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84454 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 112342944 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 112342944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 112342944 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 75276 89.13% 89.13% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9178 10.87% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84454 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 301450 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108580 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84454 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108580 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 410030 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84454 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 351040 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 92214946 # DTB read hits -system.cpu1.dtb.read_misses 251350 # DTB read misses -system.cpu1.dtb.write_hits 79863458 # DTB write hits -system.cpu1.dtb.write_misses 50100 # DTB write misses +system.cpu1.dtb.read_hits 83602508 # DTB read hits +system.cpu1.dtb.read_misses 221634 # DTB read misses +system.cpu1.dtb.write_hits 72407946 # DTB write hits +system.cpu1.dtb.write_misses 44952 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 41485 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1017 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8355 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35586 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1113 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7045 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11459 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 92466296 # DTB read accesses -system.cpu1.dtb.write_accesses 79913558 # DTB write accesses +system.cpu1.dtb.perms_faults 10293 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83824142 # DTB read accesses +system.cpu1.dtb.write_accesses 72452898 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 172078404 # DTB hits -system.cpu1.dtb.misses 301450 # DTB misses -system.cpu1.dtb.accesses 172379854 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 156010454 # DTB hits +system.cpu1.dtb.misses 266586 # DTB misses +system.cpu1.dtb.accesses 156277040 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1536,892 +1548,893 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 68405 # Table walker walks requested -system.cpu1.itb.walker.walksLong 68405 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 536 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57692 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 68405 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 68405 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 68405 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 58228 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26184.473106 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23792.146832 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18243.083639 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 52664 90.44% 90.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 3935 6.76% 97.20% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 14 0.02% 97.23% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 1454 2.50% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 38 0.07% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 63 0.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 12 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 10 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 10 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 58228 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -588816556 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -588816556 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -588816556 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 57692 99.08% 99.08% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 536 0.92% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 58228 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 60007 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60007 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 568 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49765 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60007 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60007 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60007 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 50333 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25530.089603 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23478.456634 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19036.287161 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 49435 98.22% 98.22% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 638 1.27% 99.48% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 189 0.38% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 38 0.08% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 14 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 50333 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 111619444 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 111619444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 111619444 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 49765 98.87% 98.87% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 568 1.13% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 50333 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68405 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68405 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60007 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60007 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58228 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58228 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 126633 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 253981708 # ITB inst hits -system.cpu1.itb.inst_misses 68405 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 50333 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 50333 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 110340 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 231314016 # ITB inst hits +system.cpu1.itb.inst_misses 60007 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29878 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25531 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 186858 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 167507 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 254050113 # ITB inst accesses -system.cpu1.itb.hits 253981708 # DTB hits -system.cpu1.itb.misses 68405 # DTB misses -system.cpu1.itb.accesses 254050113 # DTB accesses -system.cpu1.numPwrStateTransitions 29008 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 14504 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3226000342.121070 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 122202778079.734619 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4515 31.13% 31.13% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 9966 68.71% 99.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.91% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 231374023 # ITB inst accesses +system.cpu1.itb.hits 231314016 # DTB hits +system.cpu1.itb.misses 60007 # DTB misses +system.cpu1.itb.accesses 231374023 # DTB accesses +system.cpu1.numPwrStateTransitions 9626 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 4813 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9788374174.243299 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 115006828751.685410 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3303 68.63% 68.63% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1483 30.81% 99.44% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.46% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.48% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 4 0.08% 99.56% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.58% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 18 0.37% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813587669000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 14504 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 486863864876 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46789908962124 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 973770006 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 1988779353616 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 4813 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 443465373367 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47111444900633 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 886937326 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 467062034 # Number of instructions committed -system.cpu1.committedOps 549524480 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 49354477 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5829 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93580668477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.084884 # CPI: cycles per instruction -system.cpu1.ipc 0.479643 # IPC: instructions per cycle +system.cpu1.committedInsts 425165575 # Number of instructions committed +system.cpu1.committedOps 499981941 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 45360018 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4813 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94223530921 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.086099 # CPI: cycles per instruction +system.cpu1.ipc 0.479364 # IPC: instructions per cycle system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 379758717 69.11% 69.11% # Class of committed instruction -system.cpu1.op_class_0::IntMult 1174710 0.21% 69.32% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 62873 0.01% 69.33% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 42788 0.01% 69.34% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction -system.cpu1.op_class_0::MemRead 88942339 16.19% 85.53% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 79543053 14.47% 100.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 346104827 69.22% 69.22% # Class of committed instruction +system.cpu1.op_class_0::IntMult 1095440 0.22% 69.44% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 59698 0.01% 69.45% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 26657 0.01% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::MemRead 80579122 16.12% 85.58% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 72116197 14.42% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 549524480 # Class of committed instruction +system.cpu1.op_class_0::total 499981941 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14504 # number of quiesce instructions executed -system.cpu1.tickCycles 754340504 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 219429502 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5584308 # number of replacements -system.cpu1.dcache.tags.tagsinuse 440.375822 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 163963779 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5584818 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.358840 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8377741807000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 440.375822 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.860109 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.860109 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 234 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 347150058 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 347150058 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 84821089 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 84821089 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 74565342 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 74565342 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 240493 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 240493 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 73857 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 73857 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1888770 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1888770 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1879546 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1879546 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 159460288 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 159460288 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 159700781 # number of overall hits -system.cpu1.dcache.overall_hits::total 159700781 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3413550 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3413550 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2348662 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2348662 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 664960 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 664960 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 462804 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 462804 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 186013 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 186013 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193851 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193851 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 6225016 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 6225016 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6889976 # number of overall misses -system.cpu1.dcache.overall_misses::total 6889976 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52244752500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 52244752500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 43500498500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 43500498500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11517052000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 11517052000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2853085500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2853085500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4630433000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4630433000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2585500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2585500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 107262303000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 107262303000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 107262303000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 107262303000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 88234639 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 88234639 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 76914004 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 76914004 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 905453 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 905453 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 536661 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 536661 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074783 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2074783 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2073397 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2073397 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 165685304 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 165685304 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 166590757 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 166590757 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038687 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038687 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030536 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030536 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.734395 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.734395 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.862377 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.862377 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089654 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089654 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.093494 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.093494 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037571 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.037571 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041359 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041359 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15305.108318 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15305.108318 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18521.395799 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18521.395799 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24885.376963 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24885.376963 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15338.097337 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15338.097337 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23886.557201 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23886.557201 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 4813 # number of quiesce instructions executed +system.cpu1.tickCycles 688160387 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 198776939 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 4915770 # number of replacements +system.cpu1.dcache.tags.tagsinuse 461.565771 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 148821179 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4916282 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.271083 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8378532705500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 461.565771 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.901496 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.901496 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 314637839 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 314637839 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 76998524 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76998524 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 67544283 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 67544283 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 228025 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 228025 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 143759 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 143759 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1733263 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1733263 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1698082 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1698082 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 144686566 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 144686566 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 144914591 # number of overall hits +system.cpu1.dcache.overall_hits::total 144914591 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2997503 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2997503 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2132920 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2132920 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 598160 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 598160 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 396373 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 396373 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156072 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 190006 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 190006 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5526796 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5526796 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6124956 # number of overall misses +system.cpu1.dcache.overall_misses::total 6124956 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46710580500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 46710580500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40169374000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 40169374000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10226397500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10226397500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2373794500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2373794500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4526922000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4526922000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1761500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1761500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 97106352000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 97106352000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 97106352000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 97106352000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 79996027 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 79996027 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69677203 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69677203 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 826185 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 826185 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 540132 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 540132 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1889335 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1889335 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1888088 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1888088 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 150213362 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 150213362 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 151039547 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 151039547 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037471 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037471 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030611 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030611 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.724002 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.724002 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.733845 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.733845 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082607 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082607 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100634 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100634 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036793 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.036793 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040552 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040552 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15583.163887 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15583.163887 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18833.042965 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18833.042965 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25799.934658 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25799.934658 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15209.611590 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15209.611590 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23825.152890 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23825.152890 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17230.847760 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17230.847760 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15567.877595 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15567.877595 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17570.098842 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17570.098842 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15854.212177 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15854.212177 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5584335 # number of writebacks -system.cpu1.dcache.writebacks::total 5584335 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169267 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 169267 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 957224 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 957224 # number of WriteReq MSHR hits +system.cpu1.dcache.writebacks::writebacks 4915771 # number of writebacks +system.cpu1.dcache.writebacks::total 4915771 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147995 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 147995 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 874601 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 874601 # number of WriteReq MSHR hits system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44866 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44866 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 87 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 87 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1126549 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1126549 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1126549 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1126549 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3244283 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3244283 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1391438 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1391438 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 664681 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 664681 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462746 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 462746 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193764 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 193764 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 5098467 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 5098467 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5763148 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5763148 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17608 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17608 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 15853 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 15853 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33461 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33461 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 45298654500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 45298654500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 25106196000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 25106196000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14639124500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14639124500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11050641000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11050641000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1898988000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1898988000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4434665000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4434665000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2119500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2119500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81455491500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 81455491500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 96094616000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 96094616000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2936127500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2936127500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2936127500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2936127500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036769 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036769 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.734087 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.734087 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.862269 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.862269 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068030 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068030 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.093452 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.093452 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030772 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034595 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034595 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13962.608841 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13962.608841 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18043.345086 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18043.345086 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22024.286086 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22024.286086 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23880.575953 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23880.575953 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13453.973517 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13453.973517 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22886.939782 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22886.939782 # average StoreCondReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 38344 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 38344 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 50 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 50 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1022654 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1022654 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1022654 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1022654 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2849508 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2849508 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1258319 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1258319 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 597912 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 597912 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 396315 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 396315 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117728 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117728 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 189956 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 189956 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4504142 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4504142 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5102054 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5102054 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7183 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7183 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7509 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14692 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14692 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40476665500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40476665500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23125073000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23125073000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13939684500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13939684500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9826633500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9826633500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1586206000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1586206000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4335749000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4335749000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1584500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1584500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73428372000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 73428372000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87368056500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 87368056500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 918087500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 918087500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 918087500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 918087500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035621 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035621 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018059 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018059 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.723702 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.723702 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.733737 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.733737 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062312 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062312 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100608 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100608 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029985 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029985 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033780 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033780 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14204.790967 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14204.790967 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18377.750793 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18377.750793 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23313.940011 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23313.940011 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24795.007759 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 24795.007759 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13473.481245 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13473.481245 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22825.017372 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22825.017372 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15976.467338 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15976.467338 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16673.980262 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16673.980262 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166749.630850 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166749.630850 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87747.751113 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 87747.751113 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 9521452 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.043038 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 244267020 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9521964 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.653008 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8368158607000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.043038 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990318 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990318 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16302.410537 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16302.410537 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17124.094825 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17124.094825 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127813.935681 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 127813.935681 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62488.939559 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62488.939559 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 8832346 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.234959 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 222308626 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8832858 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.168369 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8368864848000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.234959 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990693 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990693 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 517099934 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 517099934 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 244267020 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 244267020 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 244267020 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 244267020 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 244267020 # number of overall hits -system.cpu1.icache.overall_hits::total 244267020 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9521965 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9521965 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9521965 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9521965 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9521965 # number of overall misses -system.cpu1.icache.overall_misses::total 9521965 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 96688620500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 96688620500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 96688620500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 96688620500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 96688620500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 96688620500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 253788985 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 253788985 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 253788985 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 253788985 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 253788985 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 253788985 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037519 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.037519 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037519 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.037519 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037519 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.037519 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10154.271781 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10154.271781 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10154.271781 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10154.271781 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 471115826 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 471115826 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 222308626 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 222308626 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 222308626 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 222308626 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 222308626 # number of overall hits +system.cpu1.icache.overall_hits::total 222308626 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8832858 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8832858 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8832858 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8832858 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8832858 # number of overall misses +system.cpu1.icache.overall_misses::total 8832858 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 91672034000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 91672034000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 91672034000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 91672034000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 91672034000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 91672034000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 231141484 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 231141484 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 231141484 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 231141484 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 231141484 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 231141484 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038214 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.038214 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038214 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.038214 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038214 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.038214 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10378.524595 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10378.524595 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10378.524595 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10378.524595 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10378.524595 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10378.524595 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 9521452 # number of writebacks -system.cpu1.icache.writebacks::total 9521452 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9521965 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9521965 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9521965 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9521965 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9521965 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 9521965 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 8832346 # number of writebacks +system.cpu1.icache.writebacks::total 8832346 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8832858 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8832858 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8832858 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8832858 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8832858 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8832858 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91927638500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 91927638500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91927638500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 91927638500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91927638500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 91927638500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9070500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9070500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9070500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9070500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037519 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.037519 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.037519 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9654.271834 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95478.947368 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95478.947368 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7586302 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7586460 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 136 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 87255605000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 87255605000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 87255605000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 87255605000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 87255605000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 87255605000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9824500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9824500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9824500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9824500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038214 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.038214 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.038214 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9878.524595 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9878.524595 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9878.524595 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 103415.789474 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 103415.789474 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6928823 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6928917 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 84 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 987804 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2406613 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13125.467163 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 13856134 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2421819 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.721375 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 861587 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2157597 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13047.513497 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 12560684 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2173028 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.780268 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12849.276806 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.086630 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 14.305413 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 234.798314 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.784258 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001653 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000873 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014331 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.801115 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 271 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14856 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 106 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 108 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 47 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 65 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 743 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6180 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6756 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 775 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.906738 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 519862521 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 519862521 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 578094 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 171981 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 750075 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3464322 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3464322 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 11639503 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 11639503 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 901874 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 901874 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8781698 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 8781698 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3023137 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3023137 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191670 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 191670 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 578094 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 171981 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8781698 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3925011 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 13456784 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 578094 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 171981 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8781698 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3925011 # number of overall hits -system.cpu1.l2cache.overall_hits::total 13456784 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22586 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11050 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 33636 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 232349 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 232349 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193761 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 193761 # number of SCUpgradeReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 12721.719403 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 48.343114 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 32.192156 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 245.258823 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.776472 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002951 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001965 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014969 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.796357 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 270 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 73 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15088 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 102 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 832 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6150 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6722 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1111 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016479 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004456 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.920898 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 472979438 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 472979438 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 496781 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150336 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 647117 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3051311 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3051311 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 10695223 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 10695223 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2 # 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number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 12225407 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 496781 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 150336 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 8132856 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3445434 # number of overall hits +system.cpu1.l2cache.overall_hits::total 12225407 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 19778 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9507 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 29285 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 216104 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 216104 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 189953 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 189953 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 259533 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 259533 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 740267 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 740267 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1026659 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1026659 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 269262 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 269262 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22586 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11050 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 740267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1286192 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2060095 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22586 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11050 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 740267 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1286192 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2060095 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 726971000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 437240000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1164211000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 947721000 # 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number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24621036000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 47294328494 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 73079575494 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 600680 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 183031 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 783711 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3464322 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3464322 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 11639503 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 11639503 # 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mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250942 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182494 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28675.455088 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43700.698728 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18593.996531 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18593.996531 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15361.231063 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15361.231063 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 570833 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 570833 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35561.735393 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35561.735393 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27259.704295 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28885.430978 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28885.430978 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27367.029139 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27367.029139 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29115.472472 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33132.675950 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158745.996138 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158363.554200 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 83536.041959 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 83547.204673 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 31064178 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15870221 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 609547 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 609525 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 22 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 891069 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 14544906 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 15853 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 15853 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4703319 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 11641461 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1517999 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 982833 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 435735 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338791 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 485404 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1187635 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1166992 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9521965 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5021918 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 508584 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 460932 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28565571 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17994817 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 387517 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1269560 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 48217465 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1218784704 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 696648341 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1464248 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4805440 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1921702733 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5371031 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 85625912 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 21661443 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.043843 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.204751 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.184164 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26553.636893 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43252.561410 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18894.543812 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18894.543812 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15301.514043 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15301.514043 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 430666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 430666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37080.475970 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37080.475970 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29591.929286 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29610.705098 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29610.705098 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26632.007475 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26632.007475 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31062.482805 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30446.849170 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31062.482805 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33964.735128 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119800.083531 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119481.794449 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58570.922951 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58807.635085 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 28307892 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14471357 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1579 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 577788 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 577774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 765944 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13251577 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7509 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7509 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4119049 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 10696803 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1405207 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 907922 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 426575 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338167 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 466317 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1072889 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1050772 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8832858 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4591457 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 449471 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 394596 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26498252 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15919614 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339109 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1095958 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 43852933 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1130579136 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615678398 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1278736 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4132472 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1751668742 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5086460 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 75030592 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 19865784 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.045122 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.207576 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 20711756 95.62% 95.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 949665 4.38% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 22 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 18969410 95.49% 95.49% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 896360 4.51% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 21661443 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 30930175985 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 19865784 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 28134048478 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 161428122 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 171886209 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 14285968218 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13252138560 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8290126100 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7328947477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 204584802 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 179350830 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 668995768 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 579510776 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40347 # Transaction distribution -system.iobus.trans_dist::ReadResp 40347 # Transaction distribution -system.iobus.trans_dist::WriteReq 136610 # Transaction distribution -system.iobus.trans_dist::WriteResp 136610 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47638 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40272 # Transaction distribution +system.iobus.trans_dist::ReadResp 40272 # Transaction distribution +system.iobus.trans_dist::WriteReq 136595 # Transaction distribution +system.iobus.trans_dist::WriteResp 136595 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47628 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2432,15 +2445,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122572 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122510 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231144 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231144 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47658 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47648 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2451,105 +2464,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155679 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338592 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496829 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41998503 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496318 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42593000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 316000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25719009 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25879501 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34474500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34434000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569697884 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569469195 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92693000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92646000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147840000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115612 # number of replacements -system.iocache.tags.tagsinuse 11.289058 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115567 # number of replacements +system.iocache.tags.tagsinuse 11.304352 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115583 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9127814531000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.847615 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.441443 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240476 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465090 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705566 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9167343261000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.387949 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.916404 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.461747 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.244775 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706522 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041036 # Number of tag accesses -system.iocache.tags.data_accesses 1041036 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040505 # Number of tag accesses +system.iocache.tags.data_accesses 1040505 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8844 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8881 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115631 # number of demand (read+write) misses -system.iocache.demand_misses::total 115671 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115572 # number of demand (read+write) misses +system.iocache.demand_misses::total 115612 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115631 # number of overall misses -system.iocache.overall_misses::total 115671 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1683130463 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1688328963 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115572 # number of overall misses +system.iocache.overall_misses::total 115612 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1979797452 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1984993952 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12860878921 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12860878921 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14544009384 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14549576884 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14544009384 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14549576884 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13211000243 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13211000243 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15190797695 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15196363195 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15190797695 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15196363195 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8881 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115572 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115612 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115572 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115612 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2563,53 +2576,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 189052.056947 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 188851.114430 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 223857.694708 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 223510.184889 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120501.451550 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120501.451550 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125784.136767 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125784.136767 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33720 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123781.952655 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 123781.952655 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131440.121266 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131442.784443 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131440.121266 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131442.784443 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 49739 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3566 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3574 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.455973 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.916900 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8881 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115671 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115572 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115612 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115671 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237980463 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1241328963 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115572 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115612 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1537597452 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1540943952 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7515783412 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7515783412 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8753763875 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8757331375 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8753763875 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8757331375 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7865666947 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7865666947 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9403264399 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9406829899 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9403264399 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9406829899 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2623,661 +2636,661 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139052.056947 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 138851.114430 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173857.694708 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 173510.184889 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70419.978000 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70419.978000 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75704.299669 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75708.962272 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75704.299669 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75708.962272 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1555997 # number of replacements -system.l2c.tags.tagsinuse 65230.630092 # Cycle average of tags in use -system.l2c.tags.total_refs 7273929 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1617589 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.496772 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7807986500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 8906.310468 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.466536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 9.611192 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3875.011018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9658.633081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3787.473530 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 432.466953 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 495.764320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3981.420883 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 15318.580710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18749.891401 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.135900 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000236 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000147 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059128 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.147379 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.057792 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.006599 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.007565 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.060752 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.233743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.286101 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995340 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10605 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 254 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50733 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 57 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 363 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 10181 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1499 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4720 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 44382 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.161819 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003876 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.774124 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 80901066 # Number of tag accesses -system.l2c.tags.data_accesses 80901066 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2828973 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2828973 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 204859 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 171268 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 376127 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 49678 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 57164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 106842 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57243 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53868 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 111111 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12667 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5625 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 610867 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 589040 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 292600 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12537 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4791 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 678625 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 607071 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 308630 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3122453 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 131047 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 131317 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 262364 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 12667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 610867 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 646283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 292600 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12537 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4791 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 678625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 660939 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 308630 # number of demand (read+write) hits -system.l2c.demand_hits::total 3233564 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 12667 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5625 # number of overall hits -system.l2c.overall_hits::cpu0.inst 610867 # number of overall hits -system.l2c.overall_hits::cpu0.data 646283 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 292600 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12537 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4791 # number of overall hits -system.l2c.overall_hits::cpu1.inst 678625 # number of overall hits -system.l2c.overall_hits::cpu1.data 660939 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 308630 # number of overall hits -system.l2c.overall_hits::total 3233564 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 21060 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 26656 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 47716 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 518 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 636 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1154 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76722 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 60050 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136772 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1834 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1415 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 72156 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 133347 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 250233 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2590 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2459 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 61640 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 144790 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 229898 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 900362 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 438466 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 125863 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 564329 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1834 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1415 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 72156 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 210069 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 250233 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2590 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2459 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 61640 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 204840 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 229898 # number of demand (read+write) misses -system.l2c.demand_misses::total 1037134 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1834 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1415 # number of overall misses -system.l2c.overall_misses::cpu0.inst 72156 # number of overall misses -system.l2c.overall_misses::cpu0.data 210069 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 250233 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2590 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2459 # number of overall misses -system.l2c.overall_misses::cpu1.inst 61640 # number of overall misses -system.l2c.overall_misses::cpu1.data 204840 # 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number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 128340500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6167992000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 12302035500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 231186000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 216219500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5316209000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 13039902500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 99287989218 # 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number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 683023 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 856352 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 542833 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 15127 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7250 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 740265 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 865779 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 538528 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4270698 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.093219 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.134678 # 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average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16735.521236 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13841.194969 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 15140.381282 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91313.417273 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 87267.876736 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 89537.215205 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 92351.145038 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90700 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85481.345973 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 92255.810029 # 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average overall miss latency -system.l2c.blocked_cycles::no_mshrs 751 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73698.251134 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73698.251134 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81362.824897 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81365.514817 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81362.824897 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81365.514817 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1396284 # number of replacements +system.l2c.tags.tagsinuse 65138.751942 # Cycle average of tags in use +system.l2c.tags.total_refs 7016729 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1457215 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.815164 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8133240500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10857.852094 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 193.720367 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 194.423316 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4494.530949 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 16342.707209 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9582.831884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 263.988799 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 269.731759 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4576.542600 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 8162.860696 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10199.562268 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.165678 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002956 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002967 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.068581 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.249370 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146222 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004028 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004116 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.069832 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.124555 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.155633 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993938 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9763 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 241 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50927 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 80 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 414 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9269 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1371 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4645 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 44789 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.148972 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003677 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.777084 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 77350226 # Number of tag accesses +system.l2c.tags.data_accesses 77350226 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2692321 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2692321 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 204225 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 155483 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 359708 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 52320 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 51074 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 103394 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55531 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 51791 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107322 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13410 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5332 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 636242 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 595342 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 315678 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10946 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4404 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 639193 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 560416 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 301207 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 3082170 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 138800 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 132737 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 271537 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 13410 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5332 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 636242 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 650873 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 315678 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10946 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4404 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 639193 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 612207 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 301207 # number of demand (read+write) hits +system.l2c.demand_hits::total 3189492 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 13410 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5332 # number of overall hits +system.l2c.overall_hits::cpu0.inst 636242 # number of overall hits +system.l2c.overall_hits::cpu0.data 650873 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 315678 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79242.515396 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 97550.886770 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168555.103615 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140758.775417 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102416.958217 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186999 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.157518 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.200612 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.764068 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.445341 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.671905 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.250126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.196747 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.219853 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.250126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.196747 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.219853 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20419.179415 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20581.771963 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20509.301409 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23773.547094 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24042.089985 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23929.292929 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97862.363573 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98561.918668 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 98114.477773 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100726.295967 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105857.183007 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116471.987302 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20898.979764 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20368.736864 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20797.355596 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99668.757351 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103659.545193 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113912.230624 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99668.757351 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103659.545193 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113912.230624 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167466.118897 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101816.320986 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105875.506808 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84350.581810 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49771.477263 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74479.459252 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3616665 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2148581 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2925 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 90635 # Transaction distribution -system.membus.trans_dist::ReadResp 999620 # Transaction distribution -system.membus.trans_dist::WriteReq 38128 # Transaction distribution -system.membus.trans_dist::WriteResp 38128 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1272553 # Transaction distribution -system.membus.trans_dist::CleanEvict 289712 # Transaction distribution -system.membus.trans_dist::UpgradeReq 348270 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 267748 # Transaction distribution -system.membus.trans_dist::UpgradeResp 23 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 90772 # Transaction distribution +system.membus.trans_dist::ReadResp 873224 # Transaction distribution +system.membus.trans_dist::WriteReq 38264 # Transaction distribution +system.membus.trans_dist::WriteResp 38264 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1161561 # Transaction distribution +system.membus.trans_dist::CleanEvict 250705 # Transaction distribution +system.membus.trans_dist::UpgradeReq 347946 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 273520 # Transaction distribution +system.membus.trans_dist::UpgradeResp 24 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 152656 # Transaction distribution -system.membus.trans_dist::ReadExResp 136047 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 908985 # Transaction distribution -system.membus.trans_dist::InvalidateReq 669058 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122572 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 139972 # Transaction distribution +system.membus.trans_dist::ReadExResp 124377 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 782452 # Transaction distribution +system.membus.trans_dist::InvalidateReq 660097 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122510 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24944 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4823028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4970598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5208987 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155679 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25584 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4392225 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4540373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238087 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238087 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4778460 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155640 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144251456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 144458411 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7283200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7283200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 151741611 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 583612 # Total snoops (count) -system.membus.snoopTraffic 163584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2475487 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012229 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.109905 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128305664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 128513860 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7270464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7270464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 135784324 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 584171 # Total snoops (count) +system.membus.snoopTraffic 172608 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2333030 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013166 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.113984 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2445215 98.78% 98.78% # Request fanout histogram -system.membus.snoop_fanout::1 30272 1.22% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2302314 98.68% 98.68% # Request fanout histogram +system.membus.snoop_fanout::1 30716 1.32% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2475487 # Request fanout histogram -system.membus.reqLayer0.occupancy 102607988 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2333030 # Request fanout histogram +system.membus.reqLayer0.occupancy 103320999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20962995 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21353996 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8793410200 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8035790677 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5849158337 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5121349382 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45598905 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45284261 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3320,78 +3333,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12529275 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6783970 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2045593 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 207524 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 190768 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 16756 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 90637 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4878287 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38128 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38128 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3994832 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 3079472 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 721673 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 374590 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1096263 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301835 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301835 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4787847 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 854297 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 826693 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9608901 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8808719 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18417620 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 240252134 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 217815813 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 458067947 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2968837 # Total snoops (count) -system.toL2Bus.snoopTraffic 127024720 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8725155 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.358566 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.483567 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12127091 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6563266 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2068389 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 180040 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 163507 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 16533 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 90774 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4717359 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38264 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3747189 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2956256 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 703976 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 376914 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1080890 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 83 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 286236 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 286236 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4627139 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 855379 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 827617 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9817286 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8000729 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17818015 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243574806 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194096942 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 437671748 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2816292 # Total snoops (count) +system.toL2Bus.snoopTraffic 120259472 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8375094 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.374182 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.487973 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5613365 64.34% 64.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3095034 35.47% 99.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 16756 0.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5257818 62.78% 62.78% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3100743 37.02% 99.80% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 16533 0.20% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8725155 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9593262018 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8375094 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9230074402 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2632911 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2547405 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4411209152 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4495965489 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4336941336 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3978820805 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal index 74f9afa7a..451380e54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000023] Console: colour dummy device 80x25
-[ 0.000025] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000027] pid_max: default: 32768 minimum: 301
-[ 0.000038] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000039] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000155] hw perfevents: no hardware support available
-[ 0.060041] CPU1: Booted secondary processor
+[ 0.000024] Console: colour dummy device 80x25
+[ 0.000027] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000028] pid_max: default: 32768 minimum: 301
+[ 0.000039] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000040] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000160] hw perfevents: no hardware support available
+[ 0.060042] CPU1: Booted secondary processor
[ 1.080079] CPU2: failed to come online
-[ 2.100151] CPU3: failed to come online
-[ 2.100154] Brought up 2 CPUs
-[ 2.100155] SMP: Total of 2 processors activated.
+[ 2.100148] CPU3: failed to come online
+[ 2.100151] Brought up 2 CPUs
+[ 2.100152] SMP: Total of 2 processors activated.
[ 2.100226] devtmpfs: initialized
-[ 2.100722] atomic64_test: passed
-[ 2.100767] regulator-dummy: no parameters
-[ 2.101110] NET: Registered protocol family 16
-[ 2.101240] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.101248] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.101651] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.101655] Serial: AMBA PL011 UART driver
-[ 2.101841] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.101878] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.102452] console [ttyAMA0] enabled
-[ 2.102605] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.102668] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.102733] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.102790] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.140329] 3V3: 3300 mV
-[ 2.140389] vgaarb: loaded
-[ 2.140455] SCSI subsystem initialized
-[ 2.140504] libata version 3.00 loaded.
-[ 2.140588] usbcore: registered new interface driver usbfs
-[ 2.140613] usbcore: registered new interface driver hub
-[ 2.140641] usbcore: registered new device driver usb
-[ 2.140687] pps_core: LinuxPPS API ver. 1 registered
-[ 2.140698] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.140722] PTP clock support registered
-[ 2.140900] Switched to clocksource arch_sys_counter
-[ 2.142431] NET: Registered protocol family 2
-[ 2.142518] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.142535] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.142552] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.142574] TCP: reno registered
-[ 2.142581] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.142593] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.142627] NET: Registered protocol family 1
-[ 2.142670] RPC: Registered named UNIX socket transport module.
-[ 2.142681] RPC: Registered udp transport module.
-[ 2.142689] RPC: Registered tcp transport module.
-[ 2.142698] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.142710] PCI: CLS 0 bytes, default 64
-[ 2.142942] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.143052] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.145204] fuse init (API version 7.23)
-[ 2.145320] msgmni has been set to 469
-[ 2.145427] io scheduler noop registered
-[ 2.145479] io scheduler cfq registered (default)
-[ 2.145859] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.145872] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.145883] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.145896] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.145906] pci_bus 0000:00: scanning bus
-[ 2.145917] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.145930] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.145945] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.145979] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.145991] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.146002] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.146013] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.146024] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.146035] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.146046] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.146081] pci_bus 0000:00: fixups for bus
-[ 2.146089] pci_bus 0000:00: bus scan returning with max=00
-[ 2.146101] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.146121] pci 0000:00:00.0: fixup irq: got 33
-[ 2.146129] pci 0000:00:00.0: assigning IRQ 33
-[ 2.146140] pci 0000:00:01.0: fixup irq: got 34
-[ 2.146149] pci 0000:00:01.0: assigning IRQ 34
-[ 2.146160] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.146173] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.146186] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.146199] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.146211] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.146222] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.146234] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.146245] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.146902] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.147174] ata_piix 0000:00:01.0: version 2.13
-[ 2.147184] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.147208] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.147469] scsi0 : ata_piix
-[ 2.147563] scsi1 : ata_piix
-[ 2.147592] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.147605] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.147706] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.147719] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.147733] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.147745] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290935] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290946] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.290974] ata1.00: configured for UDMA/33
-[ 2.291028] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.291135] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.291142] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.291184] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.291194] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.291214] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.291351] sda: sda1
-[ 2.291468] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.411201] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.411215] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.411238] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.411249] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.411270] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.411282] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.411355] usbcore: registered new interface driver usb-storage
-[ 2.411408] mousedev: PS/2 mouse device common for all mice
-[ 2.411558] usbcore: registered new interface driver usbhid
-[ 2.411568] usbhid: USB HID core driver
-[ 2.411600] TCP: cubic registered
-[ 2.411608] NET: Registered protocol family 17
- -[ 2.411985] devtmpfs: mounted
-[ 2.412018] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 2.100728] atomic64_test: passed
+[ 2.100773] regulator-dummy: no parameters
+[ 2.101119] NET: Registered protocol family 16
+[ 2.101251] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101259] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.101662] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.101665] Serial: AMBA PL011 UART driver
+[ 2.101855] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.101892] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.102468] console [ttyAMA0] enabled
+[ 2.102623] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.102687] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.102745] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.102803] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.140306] 3V3: 3300 mV
+[ 2.140354] vgaarb: loaded
+[ 2.140400] SCSI subsystem initialized
+[ 2.140435] libata version 3.00 loaded.
+[ 2.140482] usbcore: registered new interface driver usbfs
+[ 2.140500] usbcore: registered new interface driver hub
+[ 2.140526] usbcore: registered new device driver usb
+[ 2.140554] pps_core: LinuxPPS API ver. 1 registered
+[ 2.140564] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.140583] PTP clock support registered
+[ 2.140715] Switched to clocksource arch_sys_counter
+[ 2.142179] NET: Registered protocol family 2
+[ 2.142255] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.142273] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.142290] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.142312] TCP: reno registered
+[ 2.142319] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.142331] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.142367] NET: Registered protocol family 1
+[ 2.142431] RPC: Registered named UNIX socket transport module.
+[ 2.142441] RPC: Registered udp transport module.
+[ 2.142450] RPC: Registered tcp transport module.
+[ 2.142458] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.142471] PCI: CLS 0 bytes, default 64
+[ 2.142634] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.142729] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.144357] fuse init (API version 7.23)
+[ 2.144445] msgmni has been set to 469
+[ 2.144792] io scheduler noop registered
+[ 2.144847] io scheduler cfq registered (default)
+[ 2.145229] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.145243] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.145255] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.145268] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.145278] pci_bus 0000:00: scanning bus
+[ 2.145289] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.145303] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.145317] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.145353] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.145366] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.145377] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.145388] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.145399] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.145410] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.145421] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.145456] pci_bus 0000:00: fixups for bus
+[ 2.145464] pci_bus 0000:00: bus scan returning with max=00
+[ 2.145476] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.145496] pci 0000:00:00.0: fixup irq: got 33
+[ 2.145505] pci 0000:00:00.0: assigning IRQ 33
+[ 2.145516] pci 0000:00:01.0: fixup irq: got 34
+[ 2.145525] pci 0000:00:01.0: assigning IRQ 34
+[ 2.145537] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.145551] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.145564] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.145577] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.145589] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.145601] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.145612] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.145624] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.146092] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.146340] ata_piix 0000:00:01.0: version 2.13
+[ 2.146352] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.146375] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.146628] scsi0 : ata_piix
+[ 2.146701] scsi1 : ata_piix
+[ 2.146733] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.146746] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.146850] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.146863] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.146877] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.146889] e1000 0000:00:00.0: enabling bus mastering
+[ 2.300748] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.300759] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.300788] ata1.00: configured for UDMA/33
+[ 2.300844] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.300954] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.300958] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.300986] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.300996] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.301021] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.301150] sda: sda1
+[ 2.301268] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.421014] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.421028] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.421050] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.421060] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.421081] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.421093] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.421166] usbcore: registered new interface driver usb-storage
+[ 2.421232] mousedev: PS/2 mouse device common for all mice
+[ 2.421395] usbcore: registered new interface driver usbhid
+[ 2.421405] usbhid: USB HID core driver
+[ 2.421435] TCP: cubic registered
+[ 2.421443] NET: Registered protocol family 17
+ +[ 2.421896] devtmpfs: mounted
+[ 2.421929] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.450547] udevd[609]: starting version 182
+[ 2.460465] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.513635] random: dd urandom read with 17 bits of entropy available
+[ 2.543480] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.641130] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.670941] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
@@ -181,4 +181,3 @@ done. rpcbind: cannot get uid of '': Success
creating NFS state directory: done
starting statd: done
-Starting auto-serial-console: done
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini index 72828743e..b088465c0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -208,7 +208,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -688,7 +688,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -748,7 +748,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -820,7 +820,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -937,7 +937,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -982,7 +982,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -994,7 +994,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1026,29 +1026,36 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1068,6 +1075,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1077,7 +1085,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1099,9 +1107,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1454,7 +1462,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1767,10 +1775,11 @@ pio=system.iobus.master[21] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain -conf_table_reported=true +conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1778,7 +1787,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2009,6 +2018,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2016,7 +2026,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout index 0ddf66a62..3120c88a0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:41:22 -gem5 executing on e108600-lin, pid 23124 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:01:48 +gem5 executing on e108600-lin, pid 17560 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor Selected 64-bit ARM architecture, updating default disk image... @@ -15,4 +15,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51660717372000 because m5_exit instruction encountered +Exiting @ tick 51688774990000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index c77078f22..1319d3c2e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.687765 # Number of seconds simulated -sim_ticks 51687764518000 # Number of ticks simulated -final_tick 51687764518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.688775 # Number of seconds simulated +sim_ticks 51688774990000 # Number of ticks simulated +final_tick 51688774990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151884 # Simulator instruction rate (inst/s) -host_op_rate 178474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8204277049 # Simulator tick rate (ticks/s) -host_mem_usage 687220 # Number of bytes of host memory used -host_seconds 6300.10 # Real time elapsed on the host -sim_insts 956884636 # Number of instructions simulated -sim_ops 1124405089 # Number of ops (including micro ops) simulated +host_inst_rate 210815 # Simulator instruction rate (inst/s) +host_op_rate 247704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11507504763 # Simulator tick rate (ticks/s) +host_mem_usage 684036 # Number of bytes of host memory used +host_seconds 4491.74 # Real time elapsed on the host +sim_insts 946928269 # Number of instructions simulated +sim_ops 1112623169 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 423488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 359680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10197440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 68348040 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 416768 # Number of bytes read from this memory -system.physmem.bytes_read::total 79745416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10197440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10197440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 96812416 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 401472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 331520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10196544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65400968 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 425152 # Number of bytes read from this memory +system.physmem.bytes_read::total 76755656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10196544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10196544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 93615936 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 96832996 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5620 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1067951 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6512 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1246035 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1512694 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 93636516 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 159321 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1021903 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6643 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1199320 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1462749 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1515267 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1322325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1542830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1873024 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1465322 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 197268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1265284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1484958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197268 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197268 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1811146 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1873422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1873024 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1322723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3416252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1246035 # Number of read requests accepted -system.physmem.writeReqs 1515267 # Number of write requests accepted -system.physmem.readBursts 1246035 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1515267 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 79703040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43200 # Total number of bytes read from write queue -system.physmem.bytesWritten 96830656 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 79745416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 96832996 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 675 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1811544 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1811146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1265682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3296502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1199320 # Number of read requests accepted +system.physmem.writeReqs 1465322 # Number of write requests accepted +system.physmem.readBursts 1199320 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1465322 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 76712512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43968 # Total number of bytes read from write queue +system.physmem.bytesWritten 93634496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 76755656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 93636516 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 687 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74796 # Per bank write bursts -system.physmem.perBankRdBursts::1 76131 # Per bank write bursts -system.physmem.perBankRdBursts::2 70862 # Per bank write bursts -system.physmem.perBankRdBursts::3 68837 # Per bank write bursts -system.physmem.perBankRdBursts::4 72123 # Per bank write bursts -system.physmem.perBankRdBursts::5 84628 # Per bank write bursts -system.physmem.perBankRdBursts::6 78694 # Per bank write bursts -system.physmem.perBankRdBursts::7 74893 # Per bank write bursts -system.physmem.perBankRdBursts::8 72007 # Per bank write bursts -system.physmem.perBankRdBursts::9 129561 # Per bank write bursts -system.physmem.perBankRdBursts::10 74825 # Per bank write bursts -system.physmem.perBankRdBursts::11 74032 # Per bank write bursts -system.physmem.perBankRdBursts::12 72055 # Per bank write bursts -system.physmem.perBankRdBursts::13 77727 # Per bank write bursts -system.physmem.perBankRdBursts::14 71057 # Per bank write bursts -system.physmem.perBankRdBursts::15 73132 # Per bank write bursts -system.physmem.perBankWrBursts::0 93267 # Per bank write bursts -system.physmem.perBankWrBursts::1 94026 # Per bank write bursts -system.physmem.perBankWrBursts::2 93600 # Per bank write bursts -system.physmem.perBankWrBursts::3 92665 # Per bank write bursts -system.physmem.perBankWrBursts::4 94539 # Per bank write bursts -system.physmem.perBankWrBursts::5 102396 # Per bank write bursts -system.physmem.perBankWrBursts::6 95600 # Per bank write bursts -system.physmem.perBankWrBursts::7 94740 # Per bank write bursts -system.physmem.perBankWrBursts::8 92115 # Per bank write bursts -system.physmem.perBankWrBursts::9 99710 # Per bank write bursts -system.physmem.perBankWrBursts::10 92671 # Per bank write bursts -system.physmem.perBankWrBursts::11 94633 # Per bank write bursts -system.physmem.perBankWrBursts::12 92127 # Per bank write bursts -system.physmem.perBankWrBursts::13 95527 # Per bank write bursts -system.physmem.perBankWrBursts::14 92160 # Per bank write bursts -system.physmem.perBankWrBursts::15 93203 # Per bank write bursts +system.physmem.perBankRdBursts::0 70144 # Per bank write bursts +system.physmem.perBankRdBursts::1 74650 # Per bank write bursts +system.physmem.perBankRdBursts::2 68418 # Per bank write bursts +system.physmem.perBankRdBursts::3 68145 # Per bank write bursts +system.physmem.perBankRdBursts::4 72367 # Per bank write bursts +system.physmem.perBankRdBursts::5 76479 # Per bank write bursts +system.physmem.perBankRdBursts::6 68140 # Per bank write bursts +system.physmem.perBankRdBursts::7 71247 # Per bank write bursts +system.physmem.perBankRdBursts::8 66581 # Per bank write bursts +system.physmem.perBankRdBursts::9 125666 # Per bank write bursts +system.physmem.perBankRdBursts::10 74635 # Per bank write bursts +system.physmem.perBankRdBursts::11 76739 # Per bank write bursts +system.physmem.perBankRdBursts::12 72169 # Per bank write bursts +system.physmem.perBankRdBursts::13 75530 # Per bank write bursts +system.physmem.perBankRdBursts::14 66172 # Per bank write bursts +system.physmem.perBankRdBursts::15 71551 # Per bank write bursts +system.physmem.perBankWrBursts::0 89120 # Per bank write bursts +system.physmem.perBankWrBursts::1 91694 # Per bank write bursts +system.physmem.perBankWrBursts::2 88427 # Per bank write bursts +system.physmem.perBankWrBursts::3 87889 # Per bank write bursts +system.physmem.perBankWrBursts::4 92386 # Per bank write bursts +system.physmem.perBankWrBursts::5 94711 # Per bank write bursts +system.physmem.perBankWrBursts::6 88472 # Per bank write bursts +system.physmem.perBankWrBursts::7 91239 # Per bank write bursts +system.physmem.perBankWrBursts::8 88274 # Per bank write bursts +system.physmem.perBankWrBursts::9 94990 # Per bank write bursts +system.physmem.perBankWrBursts::10 92874 # Per bank write bursts +system.physmem.perBankWrBursts::11 94799 # Per bank write bursts +system.physmem.perBankWrBursts::12 93039 # Per bank write bursts +system.physmem.perBankWrBursts::13 95949 # Per bank write bursts +system.physmem.perBankWrBursts::14 87664 # Per bank write bursts +system.physmem.perBankWrBursts::15 91512 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 51687762664000 # Total gap between requests +system.physmem.numWrRetry 468 # Number of times write queue was full causing retry +system.physmem.totGap 51688773130000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1246020 # Read request sizes (log2) +system.physmem.readPktSize::6 1199305 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1512694 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1180646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 58552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1462749 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1127245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,173 +160,184 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 83104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 89526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 91633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 87574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 93055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 92225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 93220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 90182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 94606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 92258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 89036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 87252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 83915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 83414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 82380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 686907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 256.997398 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.492038 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 292.459663 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 294027 42.80% 42.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 175466 25.54% 68.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 64376 9.37% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35669 5.19% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24767 3.61% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16380 2.38% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12324 1.79% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10264 1.49% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 53634 7.81% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 686907 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 80666 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.437595 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 138.740748 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 80664 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 29655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 78822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 84952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 87044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 83743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 88388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 87662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 88784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 85626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 88571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 89853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 87229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 84323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 82904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 81964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 79861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 79771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1066 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 662940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 256.956322 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.084684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 293.850288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 284383 42.90% 42.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 170705 25.75% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61081 9.21% 77.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 33561 5.06% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23575 3.56% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15515 2.34% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11286 1.70% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9362 1.41% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 53472 8.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 662940 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 77129 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.540445 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 141.912078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 77126 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 80666 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 80666 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.756093 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.057108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.363487 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 67894 84.17% 84.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 3915 4.85% 89.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3350 4.15% 93.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 2485 3.08% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1103 1.37% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 521 0.65% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 244 0.30% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 153 0.19% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 79 0.10% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 83 0.10% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 83 0.10% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 89 0.11% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 450 0.56% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 43 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 41 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 30 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 23 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 18 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 80666 # Writes before turning the bus around for reads -system.physmem.totQLat 17151209707 # Total ticks spent queuing -system.physmem.totMemAccLat 40501709707 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6226800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13772.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 77129 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 77129 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.968728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.139558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.416384 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 64621 83.78% 83.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 3761 4.88% 88.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3195 4.14% 92.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 2420 3.14% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1145 1.48% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 346 0.45% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 199 0.26% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 173 0.22% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 112 0.15% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 62 0.08% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 79 0.10% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 69 0.09% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 561 0.73% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 77 0.10% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 111 0.14% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 54 0.07% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 32 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.00% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 13 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 7 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 12 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 12 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 77129 # Writes before turning the bus around for reads +system.physmem.totQLat 38956691672 # Total ticks spent queuing +system.physmem.totMemAccLat 61431060422 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5993165000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32500.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32522.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.54 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51250.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.30 # Average write queue length when enqueuing -system.physmem.readRowHits 964137 # Number of row buffer hits during reads -system.physmem.writeRowHits 1107294 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes -system.physmem.avgGap 18718619.94 # Average gap between requests -system.physmem.pageHitRate 75.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2629783800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1434901875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4687519200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4930197840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1305935149860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29867098550250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34562709276105 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.682675 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49685845654409 # Time in different power states -system.physmem_0.memoryStateTime::REF 1725967880000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 275945978091 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2563233120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1398589500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5026242000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4873906080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1305717731910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29867289276000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34562862151890 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.685632 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49686132095770 # Time in different power states -system.physmem_1.memoryStateTime::REF 1725967880000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 275664064230 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing +system.physmem.readRowHits 929087 # Number of row buffer hits during reads +system.physmem.writeRowHits 1069644 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes +system.physmem.avgGap 19398017.87 # Average gap between requests +system.physmem.pageHitRate 75.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2341677240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1244627175 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4066872600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3778956360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50725624560.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 43528474080 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3238135680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 96319832910 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 74142648000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12293580495315 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12572988857670 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.244086 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51584838283234 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 6009063000 # Time in different power states +system.physmem_0.memoryStateTime::REF 21570724000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51180529926500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 193079953190 # Time in different power states +system.physmem_0.memoryStateTime::ACT 76356875016 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 211228448294 # Time in different power states +system.physmem_1.actEnergy 2391721500 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1271230125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4491367020 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3858107220 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 51763751520.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 44789626440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3183541920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 99591324540 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 75005755680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12290774240265 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12577142748300 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.324450 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51582206485554 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5783812250 # Time in different power states +system.physmem_1.memoryStateTime::REF 22010710000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51168482999000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 195327455894 # Time in different power states +system.physmem_1.memoryStateTime::ACT 78768252696 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 218401760160 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory @@ -343,30 +354,30 @@ system.realview.nvmem.bw_inst_read::total 14 # I system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 264432116 # Number of BP lookups -system.cpu.branchPred.condPredicted 184777930 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12360480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 195121872 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131792442 # Number of BTB hits +system.cpu.branchPred.lookups 261505306 # Number of BP lookups +system.cpu.branchPred.condPredicted 182498706 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12291836 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 192874347 # Number of BTB lookups +system.cpu.branchPred.BTBHits 130159045 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.543654 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 32005520 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2166164 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7202634 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5156312 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2046322 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 848562 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 67.483855 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31722667 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2144910 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7175659 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5109497 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2066162 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 844099 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -396,70 +407,65 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 584775 # Table walker walks requested -system.cpu.dtb.walker.walksLong 584775 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 23234 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 194431 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 584775 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 584775 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 584775 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 217665 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25428.727632 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21638.505013 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 16299.176879 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 136227 62.59% 62.59% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 78767 36.19% 98.77% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1401 0.64% 99.42% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 854 0.39% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 27 0.01% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 133 0.06% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-229375 57 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::229376-262143 75 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 47 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 26 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 217665 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -10206296 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -10206296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -10206296 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 194432 89.33% 89.33% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 23234 10.67% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 217666 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 584775 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 574319 # Table walker walks requested +system.cpu.dtb.walker.walksLong 574319 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21733 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 190269 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 574319 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 574319 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 574319 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 212002 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25745.962302 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21834.815515 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18121.324193 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 209468 98.80% 98.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2131 1.01% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 103 0.05% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 132 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 12 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 29 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 212002 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 316311704 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 316311704 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 316311704 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 190270 89.75% 89.75% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 21733 10.25% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 212003 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 574319 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 584775 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 217666 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 574319 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 212003 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 217666 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 802441 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 212003 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 786322 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184602893 # DTB read hits -system.cpu.dtb.read_misses 481054 # DTB read misses -system.cpu.dtb.write_hits 163948315 # DTB write hits -system.cpu.dtb.write_misses 103721 # DTB write misses +system.cpu.dtb.read_hits 182769858 # DTB read hits +system.cpu.dtb.read_misses 473161 # DTB read misses +system.cpu.dtb.write_hits 162201881 # DTB write hits +system.cpu.dtb.write_misses 101158 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80755 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1436 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15519 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 79796 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1477 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15505 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23435 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 185083947 # DTB read accesses -system.cpu.dtb.write_accesses 164052036 # DTB write accesses +system.cpu.dtb.perms_faults 23270 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 183243019 # DTB read accesses +system.cpu.dtb.write_accesses 162303039 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 348551208 # DTB hits -system.cpu.dtb.misses 584775 # DTB misses -system.cpu.dtb.accesses 349135983 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 344971739 # DTB hits +system.cpu.dtb.misses 574319 # DTB misses +system.cpu.dtb.accesses 345546058 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -489,72 +495,70 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 136740 # Table walker walks requested -system.cpu.itb.walker.walksLong 136740 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1077 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118526 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136740 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136740 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136740 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 119603 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27883.393393 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23898.853743 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 18564.311346 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 67731 56.63% 56.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 48774 40.78% 97.41% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 1154 0.96% 98.37% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 1639 1.37% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 37 0.03% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 137 0.11% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 18 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 21 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 18 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 119603 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -10844796 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -10844796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -10844796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118526 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1077 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 119603 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 135751 # Table walker walks requested +system.cpu.itb.walker.walksLong 135751 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1056 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 117755 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 135751 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 135751 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 135751 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 118811 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28810.606762 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24143.293111 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 28291.561253 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 115975 97.61% 97.61% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2399 2.02% 99.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 123 0.10% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 44 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 141 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 118811 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 315425204 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 315425204 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 315425204 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 117755 99.11% 99.11% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1056 0.89% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 118811 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136740 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136740 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135751 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 135751 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119603 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 119603 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 256343 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 457894474 # ITB inst hits -system.cpu.itb.inst_misses 136740 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118811 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 118811 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 254562 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 452655900 # ITB inst hits +system.cpu.itb.inst_misses 135751 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57885 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57242 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 331252 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 322846 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 458031214 # ITB inst accesses -system.cpu.itb.hits 457894474 # DTB hits -system.cpu.itb.misses 136740 # DTB misses -system.cpu.itb.accesses 458031214 # DTB accesses -system.cpu.numPwrStateTransitions 33262 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16631 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3032078673.597498 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59558384510.943253 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7336 44.11% 44.11% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9260 55.68% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 452791651 # ITB inst accesses +system.cpu.itb.hits 452655900 # DTB hits +system.cpu.itb.misses 135751 # DTB misses +system.cpu.itb.accesses 452791651 # DTB accesses +system.cpu.numPwrStateTransitions 33180 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16590 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3039388324.246233 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59640903157.908096 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7293 43.96% 43.96% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9262 55.83% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state @@ -567,23 +571,23 @@ system.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988777698120 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16631 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1261264097400 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50426500420600 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2522582223 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 16590 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1265322690755 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50423452299245 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2530699433 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 956884636 # Number of instructions committed -system.cpu.committedOps 1124405089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 99545013 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100854059486 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.636245 # CPI: cycles per instruction -system.cpu.ipc 0.379327 # IPC: instructions per cycle +system.cpu.committedInsts 946928269 # Number of instructions committed +system.cpu.committedOps 1112623169 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97851669 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7730 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100847957157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.672536 # CPI: cycles per instruction +system.cpu.ipc 0.374177 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 779381648 69.32% 69.32% # Class of committed instruction -system.cpu.op_class_0::IntMult 2317785 0.21% 69.52% # Class of committed instruction -system.cpu.op_class_0::IntDiv 99593 0.01% 69.53% # Class of committed instruction +system.cpu.op_class_0::IntAlu 771151081 69.31% 69.31% # Class of committed instruction +system.cpu.op_class_0::IntMult 2302642 0.21% 69.52% # Class of committed instruction +system.cpu.op_class_0::IntDiv 99189 0.01% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction @@ -606,522 +610,520 @@ system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Cl system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 108729 0.01% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::MemRead 179105650 15.93% 85.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 163391641 14.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 108989 0.01% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::MemRead 177312606 15.94% 85.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 161648619 14.53% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1124405089 # Class of committed instruction +system.cpu.op_class_0::total 1112623169 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed -system.cpu.tickCycles 1810679239 # Number of cycles that the object actually ticked -system.cpu.idleCycles 711902984 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11237287 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.957340 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 332608189 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11237799 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.597272 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4326295500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.957340 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16590 # number of quiesce instructions executed +system.cpu.tickCycles 1791525295 # Number of cycles that the object actually ticked +system.cpu.idleCycles 739174138 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11091024 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954083 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 329234475 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11091536 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.683398 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4655908500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954083 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1395920077 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1395920077 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 170244902 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 170244902 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 153016106 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 153016106 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 525044 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 525044 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336678 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336678 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4066137 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4066137 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4385244 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4385244 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 323597686 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 323597686 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 324122730 # number of overall hits -system.cpu.dcache.overall_hits::total 324122730 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6163054 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6163054 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4362358 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4362358 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1504058 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1504058 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246141 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246141 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 320841 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 320841 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1381544711 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1381544711 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 168600534 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 168600534 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 151416750 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 151416750 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 521238 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 521238 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 337307 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 337307 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4005998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4005998 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4318996 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4318996 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 320354591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320354591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320875829 # number of overall hits +system.cpu.dcache.overall_hits::total 320875829 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6093036 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6093036 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4287792 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4287792 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1473735 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1473735 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1243168 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1243168 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 314729 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 314729 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 11771553 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11771553 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13275611 # number of overall misses -system.cpu.dcache.overall_misses::total 13275611 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 101076172500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 101076172500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157713428000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157713428000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27433825500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 27433825500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4889648000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4889648000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 11623996 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11623996 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13097731 # number of overall misses +system.cpu.dcache.overall_misses::total 13097731 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 107249746000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 107249746000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 169106972500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 169106972500 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27289591000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 27289591000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5063641000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5063641000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 286223426000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 286223426000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 286223426000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 286223426000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 176407956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 176407956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 157378464 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 157378464 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2029102 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2029102 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1582819 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1582819 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4386978 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4386978 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4385245 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4385245 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335369239 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335369239 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 337398341 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 337398341 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034936 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.034936 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027719 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027719 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.741243 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.741243 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787292 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787292 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073135 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073135 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 303646309500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 303646309500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 303646309500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 303646309500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 174693570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 174693570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 155704542 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 155704542 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1994973 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1994973 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1580475 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1580475 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4320727 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4320727 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4318997 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4318997 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 331978587 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 331978587 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 333973560 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 333973560 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034878 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.034878 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027538 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738724 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.738724 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786579 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786579 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072842 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072842 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035100 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035100 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039347 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039347 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16400.338615 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16400.338615 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36153.251980 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36153.251980 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22015.025186 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22015.025186 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15240.097120 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15240.097120 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.035014 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035014 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039218 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039218 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17602.020733 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17602.020733 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39439.173472 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39439.173472 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21951.651748 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21951.651748 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16088.892349 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16088.892349 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24314.839852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24314.839852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21560.094372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21560.094372 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.368719 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26122.368719 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23183.123054 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23183.123054 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8619796 # number of writebacks -system.cpu.dcache.writebacks::total 8619796 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 315342 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 315342 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1930607 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1930607 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 154 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 154 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70929 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70929 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2246103 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2246103 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2246103 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2246103 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5847712 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5847712 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2431751 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2431751 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1496531 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1496531 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1245987 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1245987 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 249912 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 249912 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 8512101 # number of writebacks +system.cpu.dcache.writebacks::total 8512101 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 311042 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 311042 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1897692 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1897692 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70889 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70889 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2208886 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2208886 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2208886 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2208886 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5781994 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5781994 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2390100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2390100 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466271 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1466271 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1243016 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1243016 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 243840 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 243840 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9525450 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9525450 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 11021981 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 11021981 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33698 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33698 # number of ReadReq MSHR uncacheable +system.cpu.dcache.demand_mshr_misses::cpu.data 9415110 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9415110 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 10881381 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 10881381 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67405 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67405 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 89040002500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 89040002500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82314078000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 82314078000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 24215113000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 24215113000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26183606500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26183606500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3424677000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3424677000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94763834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 94763834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88482137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88482137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25605238500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25605238500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26041674000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26041674000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3459340500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3459340500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 197537687000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 197537687000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221752800000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 221752800000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231251500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231251500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231251500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231251500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.737534 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.737534 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787195 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787195 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056967 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056967 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 209287645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 209287645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 234892883500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 234892883500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231136500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231136500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231136500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231136500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033098 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033098 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734983 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734983 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786483 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786483 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056435 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056435 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028403 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028403 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032668 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032668 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15226.468489 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15226.468489 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33849.714876 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33849.714876 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.829532 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.829532 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21014.349668 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21014.349668 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13703.531643 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13703.531643 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032582 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032582 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16389.472905 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16389.472905 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37020.265679 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37020.265679 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17462.828154 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17462.828154 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20950.393237 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20950.393237 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14186.927904 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14186.927904 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20737.885034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20737.885034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20119.141922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20119.141922 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184914.579500 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184914.579500 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92444.944737 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92444.944737 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24740790 # number of replacements -system.cpu.icache.tags.tagsinuse 511.930482 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 432810859 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24741302 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.493455 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20587192500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.930482 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999864 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22228.911293 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22228.911293 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21586.679439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21586.679439 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184922.142094 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184922.142094 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92445.981633 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92445.981633 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 24547500 # number of replacements +system.cpu.icache.tags.tagsinuse 511.926335 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 427774095 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24548012 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.426018 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 21430762500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.926335 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999856 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 482293482 # Number of tag accesses -system.cpu.icache.tags.data_accesses 482293482 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 432810859 # 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average overall miss latency +system.cpu.icache.tags.tag_accesses 476870138 # Number of tag accesses +system.cpu.icache.tags.data_accesses 476870138 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 427774095 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 427774095 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 427774095 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 427774095 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 427774095 # number of overall hits +system.cpu.icache.overall_hits::total 427774095 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24548022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24548022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24548022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24548022 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13432.860619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13432.860619 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24740790 # number of writebacks -system.cpu.icache.writebacks::total 24740790 # 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Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 41.006765 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5897369000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9082.397486 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 468.031396 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 465.228429 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8079.882193 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47320.450462 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.138586 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007142 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007099 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123289 # 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number of writebacks +system.cpu.icache.writebacks::total 24547500 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24548022 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 24548022 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24548022 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24548022 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24548022 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24548022 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 52291 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52291 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 52291 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305202137000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 305202137000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305202137000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 305202137000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305202137000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 305202137000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4421533000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4421533000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4421533000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 4421533000 # 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number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9420792000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009588 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.118132 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.118132 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.121055 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.121055 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.305219 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.305219 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004327 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044412 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044412 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.439635 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.439635 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.033073 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.033073 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78218.231593 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19083.602484 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19083.602484 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.295400 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.295400 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004361 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043639 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043639 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.436316 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.436316 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032075 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131719.549463 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19091.946968 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19091.946968 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72944.879406 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72944.879406 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72690.640537 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72690.640537 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75552.119164 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75552.119164 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20639.713938 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20639.713938 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172411.745504 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105668.064100 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.362436 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 75911.899113 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 72719983 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 36740859 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1912 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1912 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86242.262534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86242.262534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97644.531871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97644.531871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103535.606613 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103535.606613 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20650.125014 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20650.125014 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172417.586657 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109560.654518 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.724270 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78707.303624 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 72021080 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 36381496 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4425 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1940 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1940 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1798088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 34134170 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1770978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33811680 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 10025859 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24740790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2858806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 34075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9868219 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24547500 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2814706 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 33649 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 34076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2397848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2397848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24741312 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7596551 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1271756 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1245987 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74327998 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33916673 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 673778 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2238495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 111156944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3170201152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1191384986 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2119720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7481688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4371187546 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2188425 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 94133704 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 39520716 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018595 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.135091 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 33650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2356666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2356666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24548022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7494335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1271849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1243016 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73748124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33477065 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672528 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2206986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 110104703 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3145459904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1175323090 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2133296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7422888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4330339178 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2114439 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 90765792 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 39101108 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018304 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134047 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 38785811 98.14% 98.14% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 734905 1.86% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 38385418 98.17% 98.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 715690 1.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 39520716 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 70288980496 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 39101108 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 69634684493 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1482392 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1487890 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 37194713363 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36904751913 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15679329987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15462672587 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 408839447 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 405908415 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1303303960 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1279140469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40309 # Transaction distribution -system.iobus.trans_dist::ReadResp 40309 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40325 # Transaction distribution +system.iobus.trans_dist::ReadResp 40325 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1333,11 +1335,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1352,102 +1354,102 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37793000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37691500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 335000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25128500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25239000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36456000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36441500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569339894 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569511366 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147736000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115470 # number of replacements -system.iocache.tags.tagsinuse 10.448409 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115486 # number of replacements +system.iocache.tags.tagsinuse 10.448155 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13140724969000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519445 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928964 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219965 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433060 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653026 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13141696144000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519387 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928768 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219962 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433048 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653010 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039749 # Number of tag accesses -system.iocache.tags.data_accesses 1039749 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039893 # Number of tag accesses +system.iocache.tags.data_accesses 1039893 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses -system.iocache.demand_misses::total 115528 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115504 # number of demand (read+write) misses +system.iocache.demand_misses::total 115544 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115488 # number of overall misses -system.iocache.overall_misses::total 115528 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1631024611 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1636110611 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115504 # number of overall misses +system.iocache.overall_misses::total 115544 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2067712004 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2072797504 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12739251283 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12739251283 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14370275894 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14375712894 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14370275894 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14375712894 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13276938862 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13276938862 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15344650866 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15350087366 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15344650866 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15350087366 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115504 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115544 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115504 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115544 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1461,53 +1463,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184839.597801 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184641.757251 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 233904.072851 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 233502.028163 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119433.466615 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119433.466615 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124434.880670 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124434.880670 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31942 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124474.413692 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 124474.413692 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 132850.579571 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 132850.579571 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 54006 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3389 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3503 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.425199 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.417071 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115488 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115528 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115504 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115544 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115488 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115528 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1189824611 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1193060611 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115504 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115544 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1625712004 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1628947504 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7399114026 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7399114026 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8588938637 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8592375637 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8588938637 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8592375637 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7936726922 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7936726922 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9562438926 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9565875426 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9562438926 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9565875426 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1521,95 +1523,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134839.597801 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 134641.757251 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 183904.072851 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 183502.028163 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69368.428204 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69368.428204 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 3617552 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1792214 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74408.675111 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74408.675111 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 3510315 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1740308 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 85991 # Transaction distribution -system.membus.trans_dist::ReadResp 551423 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 85987 # Transaction distribution +system.membus.trans_dist::ReadResp 540308 # Transaction distribution system.membus.trans_dist::WriteReq 33707 # Transaction distribution system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1512694 # Transaction distribution -system.membus.trans_dist::CleanEvict 249055 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4641 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1462749 # Transaction distribution +system.membus.trans_dist::CleanEvict 243530 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4703 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 731311 # Transaction distribution -system.membus.trans_dist::ReadExResp 731311 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 465432 # Transaction distribution -system.membus.trans_dist::InvalidateReq 654388 # Transaction distribution +system.membus.trans_dist::ReadExReq 695596 # Transaction distribution +system.membus.trans_dist::ReadExResp 695596 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 454321 # Transaction distribution +system.membus.trans_dist::InvalidateReq 648947 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4683490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4813146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5050656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4528935 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4658587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4896260 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 169337260 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 169507674 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7241152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7241152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 176748826 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3012 # Total snoops (count) -system.membus.snoopTraffic 192320 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1975472 # Request fanout histogram -system.membus.snoop_fanout::mean 0.014689 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.120303 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163142636 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163313042 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7249536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 170562578 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2899 # Total snoops (count) +system.membus.snoopTraffic 185088 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1923263 # Request fanout histogram +system.membus.snoop_fanout::mean 0.016618 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.127834 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1946455 98.53% 98.53% # Request fanout histogram -system.membus.snoop_fanout::1 29017 1.47% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1891303 98.34% 98.34% # Request fanout histogram +system.membus.snoop_fanout::1 31960 1.66% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1975472 # Request fanout histogram -system.membus.reqLayer0.occupancy 99807500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1923263 # Request fanout histogram +system.membus.reqLayer0.occupancy 99811000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5588000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5612500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9976212567 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9664854495 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6680987810 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6432615655 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44817130 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44921497 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1652,28 +1654,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal index 5bd114d12..3c88ced61 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000031] Console: colour dummy device 80x25
-[ 0.000034] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000036] pid_max: default: 32768 minimum: 301
-[ 0.000052] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000053] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000228] hw perfevents: no hardware support available
+[ 0.000027] Console: colour dummy device 80x25
+[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000032] pid_max: default: 32768 minimum: 301
+[ 0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000181] hw perfevents: no hardware support available
[ 1.060097] CPU1: failed to come online
[ 2.080187] CPU2: failed to come online
[ 3.100278] CPU3: failed to come online
-[ 3.100282] Brought up 1 CPUs
+[ 3.100281] Brought up 1 CPUs
[ 3.100283] SMP: Total of 1 processors activated.
-[ 3.100367] devtmpfs: initialized
-[ 3.101019] atomic64_test: passed
-[ 3.101081] regulator-dummy: no parameters
-[ 3.101652] NET: Registered protocol family 16
-[ 3.101829] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101840] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.102554] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.102561] Serial: AMBA PL011 UART driver
-[ 3.102830] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.102879] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.103440] console [ttyAMA0] enabled
-[ 3.103555] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.103592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.103630] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.103665] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130723] 3V3: 3300 mV
-[ 3.130781] vgaarb: loaded
-[ 3.130844] SCSI subsystem initialized
-[ 3.130897] libata version 3.00 loaded.
-[ 3.130956] usbcore: registered new interface driver usbfs
-[ 3.130977] usbcore: registered new interface driver hub
-[ 3.131019] usbcore: registered new device driver usb
-[ 3.131051] pps_core: LinuxPPS API ver. 1 registered
-[ 3.131061] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131081] PTP clock support registered
-[ 3.131243] Switched to clocksource arch_sys_counter
-[ 3.132709] NET: Registered protocol family 2
-[ 3.132818] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.132843] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.132874] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.132892] TCP: reno registered
-[ 3.132900] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132916] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132971] NET: Registered protocol family 1
-[ 3.133024] RPC: Registered named UNIX socket transport module.
-[ 3.133035] RPC: Registered udp transport module.
-[ 3.133043] RPC: Registered tcp transport module.
-[ 3.133051] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.133064] PCI: CLS 0 bytes, default 64
-[ 3.133270] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.133439] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.135679] fuse init (API version 7.23)
-[ 3.135790] msgmni has been set to 469
-[ 3.138999] io scheduler noop registered
-[ 3.139069] io scheduler cfq registered (default)
-[ 3.139634] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.139648] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.139659] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.139672] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.139682] pci_bus 0000:00: scanning bus
-[ 3.139694] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.139709] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.139724] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.139771] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.139784] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.139795] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.139806] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.139818] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.139829] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.139841] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.139883] pci_bus 0000:00: fixups for bus
-[ 3.139892] pci_bus 0000:00: bus scan returning with max=00
-[ 3.139905] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.139929] pci 0000:00:00.0: fixup irq: got 33
-[ 3.139938] pci 0000:00:00.0: assigning IRQ 33
-[ 3.139949] pci 0000:00:01.0: fixup irq: got 34
-[ 3.139958] pci 0000:00:01.0: assigning IRQ 34
-[ 3.139971] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.139985] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.139998] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.140011] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.140023] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.140035] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.140047] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.140059] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.140718] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.141064] ata_piix 0000:00:01.0: version 2.13
-[ 3.141076] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.141104] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.141758] scsi0 : ata_piix
-[ 3.141889] scsi1 : ata_piix
-[ 3.141926] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.141938] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.142070] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.142082] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.142099] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.142111] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301279] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301289] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301320] ata1.00: configured for UDMA/33
-[ 3.301387] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.301528] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.301559] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.301607] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.301617] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.301642] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.301803] sda: sda1
-[ 3.301959] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.421568] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.421582] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.421605] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.421616] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.421640] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.421652] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.421739] usbcore: registered new interface driver usb-storage
-[ 3.421808] mousedev: PS/2 mouse device common for all mice
-[ 3.422005] usbcore: registered new interface driver usbhid
-[ 3.422015] usbhid: USB HID core driver
-[ 3.422054] TCP: cubic registered
-[ 3.422062] NET: Registered protocol family 17
- -[ 3.422556] devtmpfs: mounted
-[ 3.422604] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 3.100354] devtmpfs: initialized
+[ 3.100991] atomic64_test: passed
+[ 3.101046] regulator-dummy: no parameters
+[ 3.101555] NET: Registered protocol family 16
+[ 3.101721] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.101732] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.102038] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.102043] Serial: AMBA PL011 UART driver
+[ 3.102290] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.102335] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.102901] console [ttyAMA0] enabled
+[ 3.103000] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.103038] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.103076] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.103112] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130703] 3V3: 3300 mV
+[ 3.130755] vgaarb: loaded
+[ 3.130815] SCSI subsystem initialized
+[ 3.130867] libata version 3.00 loaded.
+[ 3.130924] usbcore: registered new interface driver usbfs
+[ 3.130945] usbcore: registered new interface driver hub
+[ 3.130986] usbcore: registered new device driver usb
+[ 3.131018] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131027] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131047] PTP clock support registered
+[ 3.131197] Switched to clocksource arch_sys_counter
+[ 3.132637] NET: Registered protocol family 2
+[ 3.132735] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.132757] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.132784] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.132801] TCP: reno registered
+[ 3.132809] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132824] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132871] NET: Registered protocol family 1
+[ 3.132921] RPC: Registered named UNIX socket transport module.
+[ 3.132932] RPC: Registered udp transport module.
+[ 3.132940] RPC: Registered tcp transport module.
+[ 3.132948] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.132961] PCI: CLS 0 bytes, default 64
+[ 3.133158] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.133307] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.135503] fuse init (API version 7.23)
+[ 3.135611] msgmni has been set to 469
+[ 3.138767] io scheduler noop registered
+[ 3.138836] io scheduler cfq registered (default)
+[ 3.139309] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.139322] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.139334] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.139347] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.139357] pci_bus 0000:00: scanning bus
+[ 3.139369] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.139383] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.139398] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.139443] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.139455] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.139467] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.139478] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.139489] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.139501] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.139513] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.139555] pci_bus 0000:00: fixups for bus
+[ 3.139564] pci_bus 0000:00: bus scan returning with max=00
+[ 3.139576] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.139598] pci 0000:00:00.0: fixup irq: got 33
+[ 3.139607] pci 0000:00:00.0: assigning IRQ 33
+[ 3.139619] pci 0000:00:01.0: fixup irq: got 34
+[ 3.139628] pci 0000:00:01.0: assigning IRQ 34
+[ 3.139641] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.139654] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.139668] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.139681] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.139693] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.139705] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.139717] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.139729] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.140375] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.140706] ata_piix 0000:00:01.0: version 2.13
+[ 3.140717] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.140741] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.141104] scsi0 : ata_piix
+[ 3.141497] scsi1 : ata_piix
+[ 3.141534] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.141547] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.141673] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.141686] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.141703] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.141715] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301229] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301240] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301271] ata1.00: configured for UDMA/33
+[ 3.301328] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.301469] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.301499] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.301548] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.301558] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.301583] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.301736] sda: sda1
+[ 3.301887] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.421517] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.421531] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.421555] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.421565] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.421589] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.421601] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.421690] usbcore: registered new interface driver usb-storage
+[ 3.421758] mousedev: PS/2 mouse device common for all mice
+[ 3.421951] usbcore: registered new interface driver usbhid
+[ 3.421962] usbhid: USB HID core driver
+[ 3.421997] TCP: cubic registered
+[ 3.422006] NET: Registered protocol family 17
+ +[ 3.422472] devtmpfs: mounted
+[ 3.422501] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.464675] udevd[607]: starting version 182
+[ 3.464513] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.594846] random: dd urandom read with 20 bits of entropy available
+[ 3.604760] random: dd urandom read with 21 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.761479] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.771432] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini index 72dca03c3..d65c44016 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -229,7 +229,7 @@ useIndirect=true [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ pipelined=true [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -723,7 +723,7 @@ port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -948,7 +948,7 @@ useIndirect=true [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1310,7 +1310,7 @@ pipelined=true [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1442,7 +1442,7 @@ port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -1589,7 +1589,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -1635,7 +1635,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1733,27 +1733,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1773,6 +1773,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1782,7 +1783,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1804,9 +1805,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -2159,7 +2160,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -2472,10 +2473,11 @@ pio=system.iobus.master[21] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain -conf_table_reported=true +conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2483,7 +2485,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2714,6 +2716,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2721,7 +2724,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr index ab526e302..d6ed411d1 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr @@ -11,6 +11,6 @@ warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: allocating bonus target for snoop warn: allocating bonus target for snoop +warn: allocating bonus target for snoop warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: allocating bonus target for snoop diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout index 336574573..0d7fb0d1c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12199 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:43:00 +gem5 executing on e108600-lin, pid 17330 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-dual Selected 64-bit ARM architecture, updating default disk image... @@ -15,4 +15,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47384351300000 because m5_exit instruction encountered +Exiting @ tick 47384942719000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 7c01d248f..79f2acec9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.383918 # Number of seconds simulated -sim_ticks 47383917710000 # Number of ticks simulated -final_tick 47383917710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.384943 # Number of seconds simulated +sim_ticks 47384942719000 # Number of ticks simulated +final_tick 47384942719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126839 # Simulator instruction rate (inst/s) -host_op_rate 149150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6559041658 # Simulator tick rate (ticks/s) -host_mem_usage 782584 # Number of bytes of host memory used -host_seconds 7224.21 # Real time elapsed on the host -sim_insts 916315151 # Number of instructions simulated -sim_ops 1077489368 # Number of ops (including micro ops) simulated +host_inst_rate 146603 # Simulator instruction rate (inst/s) +host_op_rate 172405 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7419029838 # Simulator tick rate (ticks/s) +host_mem_usage 776468 # Number of bytes of host memory used +host_seconds 6386.95 # Real time elapsed on the host +sim_insts 936348150 # Number of instructions simulated +sim_ops 1101141201 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 217728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 211200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4242016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 16335944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 21100544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 95616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 61568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3171760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9979472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12170752 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 426688 # Number of bytes read from this memory -system.physmem.bytes_read::total 68013288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4242016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3171760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7413776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 84160640 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 225984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 211072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4210272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 17875336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 22288384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 132032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 98944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3431264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10538960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 15414592 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory +system.physmem.bytes_read::total 74864536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4210272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3431264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7641536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 90448704 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 84181224 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 82234 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 255262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 329696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 49603 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 155942 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 190168 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6667 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1078730 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1315010 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 90469288 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3531 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3298 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 81738 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 279315 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 348256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 53657 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 164684 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 240853 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1185780 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1413261 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1317584 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 89524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 344757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 445310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 66937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 210609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 256854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1435366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 89524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 66937 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1776144 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1415835 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 88853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 377237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 470368 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 72413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 325306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1579922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 88853 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 72413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 161265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1908807 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1776578 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1776144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 89524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 345191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 445310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 66937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 210609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 256854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3211944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1078730 # Number of read requests accepted -system.physmem.writeReqs 1317584 # Number of write requests accepted -system.physmem.readBursts 1078730 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1317584 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 69010688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 28032 # Total number of bytes read from write queue -system.physmem.bytesWritten 84179968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 68013288 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 84181224 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 438 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1909241 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1908807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 88853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 377671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 470368 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 72413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 325306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3489164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1185780 # Number of read requests accepted +system.physmem.writeReqs 1415835 # Number of write requests accepted +system.physmem.readBursts 1185780 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1415835 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 75867200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue +system.physmem.bytesWritten 90467840 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 74864536 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 90469288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 67696 # Per bank write bursts -system.physmem.perBankRdBursts::1 73149 # Per bank write bursts -system.physmem.perBankRdBursts::2 67549 # Per bank write bursts -system.physmem.perBankRdBursts::3 71981 # Per bank write bursts -system.physmem.perBankRdBursts::4 66956 # Per bank write bursts -system.physmem.perBankRdBursts::5 73789 # Per bank write bursts -system.physmem.perBankRdBursts::6 64889 # Per bank write bursts -system.physmem.perBankRdBursts::7 66635 # Per bank write bursts -system.physmem.perBankRdBursts::8 57075 # Per bank write bursts -system.physmem.perBankRdBursts::9 82656 # Per bank write bursts -system.physmem.perBankRdBursts::10 58467 # Per bank write bursts -system.physmem.perBankRdBursts::11 69413 # Per bank write bursts -system.physmem.perBankRdBursts::12 60741 # Per bank write bursts -system.physmem.perBankRdBursts::13 63810 # Per bank write bursts -system.physmem.perBankRdBursts::14 67156 # Per bank write bursts -system.physmem.perBankRdBursts::15 66330 # Per bank write bursts -system.physmem.perBankWrBursts::0 82175 # Per bank write bursts -system.physmem.perBankWrBursts::1 87404 # Per bank write bursts -system.physmem.perBankWrBursts::2 82364 # Per bank write bursts -system.physmem.perBankWrBursts::3 86039 # Per bank write bursts -system.physmem.perBankWrBursts::4 82832 # Per bank write bursts -system.physmem.perBankWrBursts::5 88693 # Per bank write bursts -system.physmem.perBankWrBursts::6 80795 # Per bank write bursts -system.physmem.perBankWrBursts::7 83065 # Per bank write bursts -system.physmem.perBankWrBursts::8 76149 # Per bank write bursts -system.physmem.perBankWrBursts::9 79916 # Per bank write bursts -system.physmem.perBankWrBursts::10 77037 # Per bank write bursts -system.physmem.perBankWrBursts::11 82986 # Per bank write bursts -system.physmem.perBankWrBursts::12 77147 # Per bank write bursts -system.physmem.perBankWrBursts::13 80171 # Per bank write bursts -system.physmem.perBankWrBursts::14 84038 # Per bank write bursts -system.physmem.perBankWrBursts::15 84501 # Per bank write bursts +system.physmem.perBankRdBursts::0 74918 # Per bank write bursts +system.physmem.perBankRdBursts::1 82946 # Per bank write bursts +system.physmem.perBankRdBursts::2 75146 # Per bank write bursts +system.physmem.perBankRdBursts::3 74319 # Per bank write bursts +system.physmem.perBankRdBursts::4 73960 # Per bank write bursts +system.physmem.perBankRdBursts::5 83356 # Per bank write bursts +system.physmem.perBankRdBursts::6 71088 # Per bank write bursts +system.physmem.perBankRdBursts::7 75076 # Per bank write bursts +system.physmem.perBankRdBursts::8 69225 # Per bank write bursts +system.physmem.perBankRdBursts::9 91582 # Per bank write bursts +system.physmem.perBankRdBursts::10 63014 # Per bank write bursts +system.physmem.perBankRdBursts::11 68676 # Per bank write bursts +system.physmem.perBankRdBursts::12 68042 # Per bank write bursts +system.physmem.perBankRdBursts::13 71091 # Per bank write bursts +system.physmem.perBankRdBursts::14 73017 # Per bank write bursts +system.physmem.perBankRdBursts::15 69969 # Per bank write bursts +system.physmem.perBankWrBursts::0 88621 # Per bank write bursts +system.physmem.perBankWrBursts::1 92960 # Per bank write bursts +system.physmem.perBankWrBursts::2 88280 # Per bank write bursts +system.physmem.perBankWrBursts::3 90026 # Per bank write bursts +system.physmem.perBankWrBursts::4 89701 # Per bank write bursts +system.physmem.perBankWrBursts::5 97248 # Per bank write bursts +system.physmem.perBankWrBursts::6 87218 # Per bank write bursts +system.physmem.perBankWrBursts::7 89230 # Per bank write bursts +system.physmem.perBankWrBursts::8 86326 # Per bank write bursts +system.physmem.perBankWrBursts::9 88636 # Per bank write bursts +system.physmem.perBankWrBursts::10 82100 # Per bank write bursts +system.physmem.perBankWrBursts::11 87622 # Per bank write bursts +system.physmem.perBankWrBursts::12 86001 # Per bank write bursts +system.physmem.perBankWrBursts::13 87485 # Per bank write bursts +system.physmem.perBankWrBursts::14 85741 # Per bank write bursts +system.physmem.perBankWrBursts::15 86365 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50212 # Number of times write queue was full causing retry -system.physmem.totGap 47383916196500 # Total gap between requests +system.physmem.numWrRetry 51113 # Number of times write queue was full causing retry +system.physmem.totGap 47384941205500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) -system.physmem.readPktSize::4 21334 # Read request sizes (log2) +system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1057371 # Read request sizes (log2) +system.physmem.readPktSize::6 1164422 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1315010 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 477824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 264556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 63109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 41587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 35911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1413261 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 492558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 272193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 123866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 77106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 49827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 31591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 5210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,136 +189,147 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 42274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 46464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 50322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 56496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 66561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 68608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 74012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 78194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 76215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 79218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 90231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 80845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 75138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 70175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 2035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 118579 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1002120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 152.866515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.517170 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.697434 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 641919 64.06% 64.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 209293 20.89% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56817 5.67% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24891 2.48% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19538 1.95% 95.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11144 1.11% 96.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7510 0.75% 96.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6154 0.61% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24854 2.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1002120 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61846 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.434870 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 71.484606 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 61843 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 22656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 37414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 43560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 48703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 53588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 65839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 73927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 78606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 82389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 81499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 83906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 89741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 97285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 86545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 80600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 5197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 25051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 120445 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1083045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 153.580618 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.695829 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 199.684011 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 694535 64.13% 64.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 223527 20.64% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61545 5.68% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27125 2.50% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21919 2.02% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12312 1.14% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8465 0.78% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6818 0.63% 97.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 26799 2.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1083045 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 67614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.532168 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 68.484066 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 67610 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61846 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.267535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.561626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 606.950117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 61844 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61846 # Writes before turning the bus around for reads -system.physmem.totQLat 51075620081 # Total ticks spent queuing -system.physmem.totMemAccLat 71293595081 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5391460000 # Total ticks spent in databus transfers -system.physmem.avgQLat 47367.15 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 67614 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 67614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.906321 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.453992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 533.973047 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-2047 67611 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12288-14335 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43008-45055 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::129024-131071 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 67614 # Writes before turning the bus around for reads +system.physmem.totQLat 72498378118 # Total ticks spent queuing +system.physmem.totMemAccLat 94725096868 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5927125000 # Total ticks spent in databus transfers +system.physmem.avgQLat 61158.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 66117.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 79908.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.91 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing -system.physmem.readRowHits 810741 # Number of row buffer hits during reads -system.physmem.writeRowHits 580742 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 44.15 # Row buffer hit rate for writes -system.physmem.avgGap 19773667.47 # Average gap between requests -system.physmem.pageHitRate 58.13 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3929423400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2144030625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4310615400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4363418160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1164748800645 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27408641092500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31683024522570 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.645104 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45596671664426 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582253140000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 204992820574 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3646603800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1989714375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4100054400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4159803600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1159320938310 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27413402375250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31681506631575 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.613070 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45604605403923 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582253140000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 197059081077 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 894792 # Number of row buffer hits during reads +system.physmem.writeRowHits 621147 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.94 # Row buffer hit rate for writes +system.physmem.avgGap 18213663.90 # Average gap between requests +system.physmem.pageHitRate 58.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4041154320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2147920665 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4361176260 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3775542480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 33222521280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 42262106220 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1577144160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 67404809070 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 44351104800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11290594038405 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11493753562350 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.561305 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47288119152834 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 2641670410 # Time in different power states +system.physmem_0.memoryStateTime::REF 14105156000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 47024804557250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 115497548988 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80076687506 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 147817098846 # Time in different power states +system.physmem_1.actEnergy 3691794120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1962235110 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4102758240 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3603240720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 31839581280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 42875044890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1564584000 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 59886050220 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 43118785440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11295073117425 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11487733544595 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.434260 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47286801320918 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2657158504 # Time in different power states +system.physmem_1.memoryStateTime::REF 13520630000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 47043190241000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 112288389331 # Time in different power states +system.physmem_1.memoryStateTime::ACT 81956603828 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 131329696337 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -345,30 +356,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 139955722 # Number of BP lookups -system.cpu0.branchPred.condPredicted 92576910 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6767718 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98409045 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61922323 # Number of BTB hits +system.cpu0.branchPred.lookups 139745078 # Number of BP lookups +system.cpu0.branchPred.condPredicted 92256746 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6767345 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 98774130 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61692324 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 62.923406 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 19026711 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 185987 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4326684 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2749366 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1577318 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 397214 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 62.457978 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 19130272 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 187780 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4236971 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2716946 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1520025 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 386103 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -398,86 +409,87 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 611788 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 611788 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13108 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 98298 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 292807 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 318981 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2428.828049 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 13543.109769 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 316274 99.15% 99.15% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 2036 0.64% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 442 0.14% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 53 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 29 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 318981 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 326187 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22022.583671 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18838.451550 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 17664.426007 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 321608 98.60% 98.60% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3320 1.02% 99.61% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 429 0.13% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 611 0.19% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 146 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 45 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 642249 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 642249 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14371 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105891 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 311173 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 331076 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2394.451727 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14284.464178 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 328283 99.16% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 2041 0.62% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 492 0.15% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 140 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 331076 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 352054 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21918.096372 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18874.221671 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 17893.290078 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 347548 98.72% 98.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2975 0.85% 99.57% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 632 0.18% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 594 0.17% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 153 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 118 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 25 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 326187 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 530119453936 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.586335 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.554664 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 528635854936 99.72% 99.72% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 807711000 0.15% 99.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 321496500 0.06% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 138249500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 109943500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 58618500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 20610000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 26013000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 940000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 17000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 530119453936 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 98298 88.23% 88.23% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13108 11.77% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 111406 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 611788 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 352054 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 539733877528 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.599244 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.552867 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 538149503028 99.71% 99.71% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 904434000 0.17% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 320975500 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 139201000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 110066000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 60836000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 22060500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 25840500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 959500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 539733877528 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 105891 88.05% 88.05% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 14371 11.95% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 120262 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 642249 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 611788 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111406 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 642249 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120262 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111406 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 723194 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120262 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 762511 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 102674478 # DTB read hits -system.cpu0.dtb.read_misses 445170 # DTB read misses -system.cpu0.dtb.write_hits 82832935 # DTB write hits -system.cpu0.dtb.write_misses 166618 # DTB write misses -system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 102850435 # DTB read hits +system.cpu0.dtb.read_misses 467880 # DTB read misses +system.cpu0.dtb.write_hits 83320332 # DTB write hits +system.cpu0.dtb.write_misses 174369 # DTB write misses +system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 42795 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 479 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7037 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 42516 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 599 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7036 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 40072 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 103119648 # DTB read accesses -system.cpu0.dtb.write_accesses 82999553 # DTB write accesses +system.cpu0.dtb.perms_faults 38961 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 103318315 # DTB read accesses +system.cpu0.dtb.write_accesses 83494701 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 185507413 # DTB hits -system.cpu0.dtb.misses 611788 # DTB misses -system.cpu0.dtb.accesses 186119201 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 186170767 # DTB hits +system.cpu0.dtb.misses 642249 # DTB misses +system.cpu0.dtb.accesses 186813016 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,1182 +519,1177 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 85546 # Table walker walks requested -system.cpu0.itb.walker.walksLong 85546 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1054 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59782 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10366 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 75180 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1322.160149 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 9414.531253 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 74314 98.85% 98.85% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.60% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 228 0.30% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 153 0.20% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 75180 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 71202 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26797.709334 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23346.070270 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 22372.473032 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 68772 96.59% 96.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 2000 2.81% 99.40% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 197 0.28% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 144 0.20% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 71202 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 422744199036 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.876427 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.329334 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 52271860780 12.36% 12.36% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 370441299256 87.63% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 29828500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1210500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 422744199036 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 59782 98.27% 98.27% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1054 1.73% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 60836 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 84160 # Table walker walks requested +system.cpu0.itb.walker.walksLong 84160 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1044 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58792 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10193 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 73967 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1726.006192 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 15527.215020 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-65535 73402 99.24% 99.24% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-131071 457 0.62% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-196607 56 0.08% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-327679 7 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-393215 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::589824-655359 22 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 73967 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 70029 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27234.188693 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23423.171681 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 26401.977199 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 67612 96.55% 96.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1634 2.33% 98.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 479 0.68% 99.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 184 0.26% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 16 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 70029 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 423766533036 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.875739 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.330248 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 52705402108 12.44% 12.44% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 371016436928 87.55% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 42131000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1939000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 624000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 423766533036 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 58792 98.26% 98.26% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1044 1.74% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 59836 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85546 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85546 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84160 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84160 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60836 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60836 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 146382 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 220474674 # ITB inst hits -system.cpu0.itb.inst_misses 85546 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59836 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59836 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 143996 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 220066677 # ITB inst hits +system.cpu0.itb.inst_misses 84160 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 31037 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 30584 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 205838 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 203568 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 220560220 # ITB inst accesses -system.cpu0.itb.hits 220474674 # DTB hits -system.cpu0.itb.misses 85546 # DTB misses -system.cpu0.itb.accesses 220560220 # DTB accesses -system.cpu0.numPwrStateTransitions 10840 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 5420 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 8671662092.472324 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 149203914828.202179 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3833 70.72% 70.72% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 1557 28.73% 99.45% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.20% 99.65% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.06% 99.70% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 13 0.24% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 6993554617000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 5420 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 383509168800 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 47000408541200 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 767019929 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 220150837 # ITB inst accesses +system.cpu0.itb.hits 220066677 # DTB hits +system.cpu0.itb.misses 84160 # DTB misses +system.cpu0.itb.accesses 220150837 # DTB accesses +system.cpu0.numPwrStateTransitions 10070 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 5035 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 9333517887.918768 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 154504325024.809692 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3827 76.01% 76.01% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1181 23.46% 99.46% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.60% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 13 0.26% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 6914082505000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 5035 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 390680153329 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46994262565671 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 781361530 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 88196996 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 619911097 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 139955722 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83698400 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 636708825 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14589342 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2007819 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 289070 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6017581 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 759490 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 830550 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 220269194 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1684756 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 27864 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 742105002 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.977120 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.219124 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 89977379 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 618690334 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 139745078 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83539542 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 647313928 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14578052 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1993554 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 302966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 5990682 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 771527 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 852599 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 219863904 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1701332 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 27447 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 754491661 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.959990 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.215112 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 394679215 53.18% 53.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 135211877 18.22% 71.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 46727804 6.30% 77.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 165486106 22.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 407421945 54.00% 54.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 135112889 17.91% 71.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 46679176 6.19% 78.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 165277651 21.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 742105002 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.182467 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.808207 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 106471358 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 362106065 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 229306920 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 38969186 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5251473 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19951761 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2082457 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 641630797 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23347252 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5251473 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 142650653 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 53065481 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 241402745 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 231558396 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 68176254 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 624076980 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6229632 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10704846 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 385160 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 931811 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 31501280 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 596222700 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 963956032 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 736577059 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 695179 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 537389975 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 58832686 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16140854 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14103711 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78118251 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 102816112 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86124751 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9533509 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8142362 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 600960924 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16329392 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 605893488 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2751703 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 55206879 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35882934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 285911 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 742105002 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.816453 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.065729 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 754491661 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.178848 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.791811 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 107863691 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 373653702 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 228590583 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39162463 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5221222 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 20030707 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2107727 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 640747867 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23352656 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5221222 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 144093047 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 59069591 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 244366962 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 230957488 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 70783351 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 623359263 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6158447 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 11021555 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 440656 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 940490 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 33921586 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11494 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 594689945 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 962815337 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 736259751 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 682623 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 536299590 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 58390349 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16178274 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14135285 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78489785 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 102915286 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86617273 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9593817 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8133429 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 600294247 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16347683 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 605471525 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2720884 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 54918264 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 35662191 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 285806 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 754491661 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.802489 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.061507 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 411055814 55.39% 55.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 139198751 18.76% 74.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 116841261 15.74% 89.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 67029634 9.03% 98.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7974397 1.07% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5145 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 423297632 56.10% 56.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 139867580 18.54% 74.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 116427415 15.43% 90.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 66852551 8.86% 98.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8040953 1.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5530 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 742105002 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 754491661 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62807824 45.43% 45.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 65216 0.05% 45.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 15839 0.01% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 32 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 36880846 26.68% 72.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 38467267 27.83% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62202700 45.10% 45.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 65869 0.05% 45.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 12866 0.01% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 27 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 36951420 26.79% 71.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 38701650 28.06% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 414236377 68.37% 68.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1540158 0.25% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 80647 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 9 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 1 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 41778 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 105913797 17.48% 86.12% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 84080696 13.88% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 413123878 68.23% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1535668 0.25% 68.49% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 80204 0.01% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 6 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 45354 0.01% 68.51% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 106103331 17.52% 86.03% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 84583031 13.97% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 605893488 # Type of FU issued -system.cpu0.iq.rate 0.789932 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 138237024 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228154 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2093764115 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 672208466 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 588253598 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1116590 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 439713 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 411739 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 743434871 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 695616 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2774549 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 605471525 # Type of FU issued +system.cpu0.iq.rate 0.774893 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 137934532 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227813 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2104985611 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 671273361 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 587796479 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1104514 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 436534 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 408765 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 742719141 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 686865 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2818576 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12838296 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17783 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 152412 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5562268 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12827708 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17934 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 150945 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5597965 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2788433 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4754457 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2832815 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4794177 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5251473 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7932610 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1687524 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 617423509 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5221222 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8523162 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2018525 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 616773219 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 102816112 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86124751 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13854081 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 62183 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1552208 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 152412 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1974984 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3105212 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5080196 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 597824194 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 102668745 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7465093 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 102915286 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86617273 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13889545 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 69101 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1866975 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 150945 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1955799 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3092868 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5048667 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 597424685 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 102845914 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7413191 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 133193 # number of nop insts executed -system.cpu0.iew.exec_refs 185500111 # number of memory reference insts executed -system.cpu0.iew.exec_branches 112433305 # Number of branches executed -system.cpu0.iew.exec_stores 82831366 # Number of stores executed -system.cpu0.iew.exec_rate 0.779412 # Inst execution rate -system.cpu0.iew.wb_sent 589443856 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 588665337 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 287005457 # num instructions producing a value -system.cpu0.iew.wb_consumers 470602155 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.767471 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609869 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 48230515 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16043481 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4724520 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 732949405 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.766879 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.569816 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 131289 # number of nop insts executed +system.cpu0.iew.exec_refs 186166471 # number of memory reference insts executed +system.cpu0.iew.exec_branches 112308682 # Number of branches executed +system.cpu0.iew.exec_stores 83320557 # Number of stores executed +system.cpu0.iew.exec_rate 0.764594 # Inst execution rate +system.cpu0.iew.wb_sent 588977240 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 588205244 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 286222957 # num instructions producing a value +system.cpu0.iew.wb_consumers 469478170 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.752795 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609662 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 48006701 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16061877 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4699541 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 745382545 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.753605 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560188 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 487135616 66.46% 66.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 127506386 17.40% 83.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 54345658 7.41% 91.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18167389 2.48% 93.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13030534 1.78% 95.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9013680 1.23% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6080548 0.83% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3647046 0.50% 98.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14022548 1.91% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 499589625 67.02% 67.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 127846284 17.15% 84.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 54154407 7.27% 91.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18022208 2.42% 93.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 12958039 1.74% 95.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8991225 1.21% 96.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6101110 0.82% 97.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3650180 0.49% 98.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14069467 1.89% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 732949405 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 479057822 # Number of instructions committed -system.cpu0.commit.committedOps 562083399 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 745382545 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 478330111 # Number of instructions committed +system.cpu0.commit.committedOps 561723659 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 170540284 # Number of memory references committed -system.cpu0.commit.loads 89977801 # Number of loads committed -system.cpu0.commit.membars 3918882 # Number of memory barriers committed -system.cpu0.commit.branches 106864519 # Number of branches committed -system.cpu0.commit.fp_insts 404083 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 515735338 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14196925 # Number of function calls committed. +system.cpu0.commit.refs 171106885 # Number of memory references committed +system.cpu0.commit.loads 90087577 # Number of loads committed +system.cpu0.commit.membars 3940521 # Number of memory barriers committed +system.cpu0.commit.branches 106744395 # Number of branches committed +system.cpu0.commit.fp_insts 400838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 515553500 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14275050 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 390151246 69.41% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1292004 0.23% 69.64% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 63609 0.01% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 36256 0.01% 69.66% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 89977801 16.01% 85.67% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 80562483 14.33% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 389225467 69.29% 69.29% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1288146 0.23% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 63590 0.01% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 39571 0.01% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 90087577 16.04% 85.58% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 81019308 14.42% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 562083399 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14022548 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1325013729 # The number of ROB reads -system.cpu0.rob.rob_writes 1229746140 # The number of ROB writes -system.cpu0.timesIdled 998783 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24914927 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 94000815527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 479057822 # Number of Instructions Simulated -system.cpu0.committedOps 562083399 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.601101 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.601101 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.624570 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.624570 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 705670279 # number of integer regfile reads -system.cpu0.int_regfile_writes 419695299 # number of integer regfile writes -system.cpu0.fp_regfile_reads 680997 # number of floating regfile reads -system.cpu0.fp_regfile_writes 310212 # number of floating regfile writes -system.cpu0.cc_regfile_reads 130338984 # number of cc regfile reads -system.cpu0.cc_regfile_writes 131056521 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1328403158 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16107336 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6279329 # number of replacements -system.cpu0.dcache.tags.tagsinuse 481.718631 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 157880144 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6279840 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.140791 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.718631 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940857 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.940857 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 354237308 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 354237308 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 83229187 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83229187 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69700757 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69700757 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201759 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 201759 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 148045 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 148045 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1863463 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1863463 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1922512 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1922512 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153077989 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153077989 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153279748 # number of overall hits -system.cpu0.dcache.overall_hits::total 153279748 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7047364 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7047364 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7798246 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7798246 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 750513 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 750513 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796040 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 796040 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 285990 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 285990 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189707 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 189707 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15641650 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15641650 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 16392163 # number of overall misses -system.cpu0.dcache.overall_misses::total 16392163 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 106587069500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 106587069500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 149276619912 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 149276619912 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 30060531759 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 30060531759 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4170219500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4170219500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536657500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4536657500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2221500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2221500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 285924221171 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 285924221171 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 285924221171 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 285924221171 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90276551 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90276551 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77499003 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77499003 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 952272 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 952272 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 944085 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 944085 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2149453 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2149453 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2112219 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2112219 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 168719639 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 168719639 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 169671911 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 169671911 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078064 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.078064 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.100624 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.100624 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.788129 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788129 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843187 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843187 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.133052 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.133052 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089814 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089814 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092708 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092708 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096611 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.096611 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15124.388282 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15124.388282 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19142.332765 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19142.332765 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37762.589517 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37762.589517 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14581.696912 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14581.696912 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23914.022677 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23914.022677 # average StoreCondReq miss latency +system.cpu0.commit.op_class_0::total 561723659 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14069467 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1336864700 # The number of ROB reads +system.cpu0.rob.rob_writes 1228532736 # The number of ROB writes +system.cpu0.timesIdled 1001309 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26869869 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93988523944 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 478330111 # Number of Instructions Simulated +system.cpu0.committedOps 561723659 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.633519 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.633519 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.612175 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.612175 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 705719528 # number of integer regfile reads +system.cpu0.int_regfile_writes 419138035 # number of integer regfile writes +system.cpu0.fp_regfile_reads 669802 # number of floating regfile reads +system.cpu0.fp_regfile_writes 321532 # number of floating regfile writes +system.cpu0.cc_regfile_reads 129631161 # number of cc regfile reads +system.cpu0.cc_regfile_writes 130314957 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1341639409 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16172326 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6359267 # number of replacements +system.cpu0.dcache.tags.tagsinuse 478.495579 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 158196405 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6359779 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 24.874513 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.495579 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934562 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.934562 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 355337560 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 355337560 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 83119639 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83119639 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 70042361 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 70042361 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205739 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 205739 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 143941 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 143941 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1893040 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1893040 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1948071 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1948071 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 153305941 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153305941 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153511680 # number of overall hits +system.cpu0.dcache.overall_hits::total 153511680 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7167523 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7167523 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7883078 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7883078 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 755741 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 755741 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796292 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 796292 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 289192 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 289192 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197314 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 197314 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15846893 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 15846893 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 16602634 # number of overall misses +system.cpu0.dcache.overall_misses::total 16602634 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 116616484000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 116616484000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 160918615442 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 160918615442 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 30600076090 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 30600076090 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4458676000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4458676000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4713253000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4713253000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2519000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2519000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 308135175532 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 308135175532 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 308135175532 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 308135175532 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90287162 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90287162 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77925439 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77925439 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961480 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 961480 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 940233 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 940233 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2182232 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2182232 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2145385 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2145385 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169152834 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 169152834 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170114314 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 170114314 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079386 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.079386 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101162 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.101162 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786018 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786018 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.846909 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.846909 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132521 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132521 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091971 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091971 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093684 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.093684 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097597 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097597 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16270.123444 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16270.123444 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20413.170521 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20413.170521 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 38428.209865 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 38428.209865 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.701734 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.701734 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23887.068328 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23887.068328 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18279.671337 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18279.671337 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17442.739019 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17442.739019 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9136124 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 22955799 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 744485 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 773832 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.271737 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 29.665094 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6279393 # number of writebacks -system.cpu0.dcache.writebacks::total 6279393 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3627313 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3627313 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6268862 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6268862 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4039 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4039 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 145852 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 145852 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9900214 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9900214 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9900214 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9900214 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3420051 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3420051 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1529384 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1529384 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 743716 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 743716 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792001 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 792001 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140138 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140138 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189707 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 189707 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5741436 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5741436 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6485152 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6485152 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17085 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17085 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18834 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18834 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35919 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35919 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49260241500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49260241500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32250000948 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32250000948 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16897998500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16897998500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29124405259 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29124405259 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1866604500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1866604500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4347004500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4347004500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2167500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2167500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110634647707 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 110634647707 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 127532646207 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 127532646207 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3215151000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3215151000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3215151000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3215151000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037884 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037884 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019734 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019734 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.780991 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.780991 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.838909 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.838909 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065197 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065197 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089814 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089814 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034029 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034029 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038222 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.038222 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14403.364599 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14403.364599 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21086.921890 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21086.921890 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22721.036659 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22721.036659 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36773.192533 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36773.192533 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13319.759808 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13319.759808 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22914.307327 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22914.307327 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19444.516697 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19444.516697 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18559.415062 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18559.415062 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9297521 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 24817691 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 744023 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 779199 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.496282 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 31.850260 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 6359403 # number of writebacks +system.cpu0.dcache.writebacks::total 6359403 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3686639 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3686639 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6327255 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6327255 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4271 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4271 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 148971 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 148971 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10018165 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10018165 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10018165 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10018165 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3480884 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3480884 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1555823 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1555823 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 748893 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 748893 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792021 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 792021 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140221 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140221 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197311 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 197311 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5828728 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5828728 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6577621 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6577621 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16980 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18801 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35781 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 53164892500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 53164892500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34944889021 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34944889021 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18458336500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18458336500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29638184090 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29638184090 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1982757000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1982757000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4516003000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4516003000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2458000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2458000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 117747965611 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 117747965611 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136206302111 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 136206302111 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3133590500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3133590500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3133590500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3133590500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038553 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038553 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019966 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019966 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.778896 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.778896 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842367 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842367 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091970 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091970 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034458 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034458 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038666 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.038666 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15273.388168 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15273.388168 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22460.709876 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22460.709876 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24647.495036 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24647.495036 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 37420.957386 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 37420.957386 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14140.228639 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14140.228639 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22887.740673 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22887.740673 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19269.508135 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19269.508135 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19665.328771 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19665.328771 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188185.601405 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188185.601405 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89511.150088 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89511.150088 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5960489 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.962298 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 213927686 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5961001 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.887880 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13033031000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962298 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999926 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999926 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20201.314182 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20201.314182 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20707.532725 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20707.532725 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184545.965842 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184545.965842 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87576.940276 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87576.940276 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 6086800 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.960315 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 213393241 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6087312 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.055414 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13476237000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960315 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 446443685 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 446443685 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 213927686 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 213927686 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 213927686 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 213927686 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 213927686 # number of overall hits -system.cpu0.icache.overall_hits::total 213927686 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6313628 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6313628 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6313628 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6313628 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6313628 # number of overall misses -system.cpu0.icache.overall_misses::total 6313628 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 68941695345 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 68941695345 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 68941695345 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 68941695345 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 68941695345 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 68941695345 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 220241314 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 220241314 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 220241314 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 220241314 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 220241314 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 220241314 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028667 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028667 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028667 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028667 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028667 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028667 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10919.505448 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10919.505448 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10919.505448 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10919.505448 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10919.505448 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10919.505448 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10186888 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 465 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 736848 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.824952 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 51.666667 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5960489 # number of writebacks -system.cpu0.icache.writebacks::total 5960489 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 352571 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 352571 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 352571 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 352571 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 352571 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 352571 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5961057 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5961057 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5961057 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5961057 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5961057 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5961057 # number of overall MSHR misses +system.cpu0.icache.tags.tag_accesses 445759262 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 445759262 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 213393241 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 213393241 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 213393241 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 213393241 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 213393241 # number of overall hits +system.cpu0.icache.overall_hits::total 213393241 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6442715 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6442715 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6442715 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6442715 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6442715 # number of overall misses +system.cpu0.icache.overall_misses::total 6442715 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71477790896 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 71477790896 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 71477790896 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 71477790896 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 71477790896 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 71477790896 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 219835956 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 219835956 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 219835956 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 219835956 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 219835956 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 219835956 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029307 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029307 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029307 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029307 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029307 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029307 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11094.358651 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11094.358651 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11094.358651 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11094.358651 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10557387 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 2753 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 752829 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.023619 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 196.642857 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 6086800 # number of writebacks +system.cpu0.icache.writebacks::total 6086800 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355365 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 355365 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 355365 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 355365 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 355365 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 355365 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6087350 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6087350 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6087350 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6087350 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6087350 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6087350 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62354110053 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 62354110053 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62354110053 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 62354110053 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62354110053 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 62354110053 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027066 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027066 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027066 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10460.243888 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8592940 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8600926 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7220 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64448796094 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 64448796094 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64448796094 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 64448796094 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64448796094 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 64448796094 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027690 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027690 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027690 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10587.332106 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8595677 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8603285 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 6909 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1116114 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2719287 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15847.951353 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 10783985 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2734787 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.943263 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2212469000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15472.818870 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.262850 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 18.351912 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 323.517722 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.944386 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002030 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001120 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019746 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.967282 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 300 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15089 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 82 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 118 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 1123339 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2781248 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15839.093178 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 10966307 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2797118 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.920574 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2357977000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.164563 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.011471 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 18.049668 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000001 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.867475 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.947215 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002015 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001102 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016410 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.966742 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 337 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15450 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 116 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2056 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7291 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3067 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2287 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018311 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920959 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 426577615 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 426577615 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 609078 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 186922 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 796000 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4110828 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4110828 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8127250 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8127250 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 41 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 991441 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 991441 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5365262 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5365262 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3250561 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3250561 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 179546 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 179546 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 609078 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 186922 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5365262 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4242002 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10403264 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 609078 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 186922 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5365262 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4242002 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10403264 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 23667 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12082 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 35749 # number of ReadReq misses -system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses -system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 259915 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 259915 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 189699 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 189699 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 286982 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 286982 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 595762 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 595762 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1051075 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1051075 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 610539 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 610539 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 23667 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12082 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 595762 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1338057 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1969568 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 23667 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12082 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 595762 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1338057 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1969568 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 824553000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 534370500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1358923500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 956036000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 956036000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 288541500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 288541500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2086500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2086500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16444485496 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 16444485496 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20913606500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20913606500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 39888753486 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 39888753486 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 293901000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 293901000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 824553000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 534370500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20913606500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 56333238982 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 78605768982 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 824553000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 534370500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20913606500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 56333238982 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 78605768982 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 632745 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 199004 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 831749 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4110828 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4110828 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 8127252 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 8127252 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 259956 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 259956 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189704 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 189704 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1708 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7197 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4776 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020569 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.942993 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 434183760 # 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mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999842 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999842 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999974 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999974 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999915 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999915 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999990 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999990 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.209906 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.209906 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099943 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.243132 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243132 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772747 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772747 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037192 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058923 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235520 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157218 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037192 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058923 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235520 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216069 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216069 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097477 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249205 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249205 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.789118 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.789118 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.241617 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.158301 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.241617 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228959 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32290.152869 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59475.138338 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18533.216598 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18533.216598 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15397.474383 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15397.474383 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 587500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 587500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45129.381880 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45129.381880 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29103.997241 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31830.259628 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31830.259628 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36425.359014 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36425.359014 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32838.272405 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41184.535280 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180158.267486 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125175.439054 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85692.920182 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83968.101098 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 25397703 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13066663 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1795 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 671473 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 671468 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 963728 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11315166 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 18834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 18834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5872564 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8129050 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1348327 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1122615 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 22 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 466810 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 338240 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 510310 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1307620 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1285212 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5961057 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5219350 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 843100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 790085 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17925156 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20147173 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419117 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1337980 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 39829426 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 763317520 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 765224037 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1592032 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5061960 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1535195549 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5838031 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 119621704 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 19351504 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.054273 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.226556 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229330 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34997.108322 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65391.691488 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18519.906505 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18519.906505 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15371.196205 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15371.196205 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400100 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400100 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50363.819503 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50363.819503 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31122.206006 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35189.856297 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35189.856297 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36508.154280 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36508.154280 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36107.230903 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45177.276679 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176515.871614 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127105.256970 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83766.230681 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85234.949364 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 25828303 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13287358 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1712 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 676521 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 676518 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 990165 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11537181 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 18801 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 18801 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5966642 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8286555 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1378403 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1136481 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 480580 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352407 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 530357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1327096 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1303956 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6087350 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5339261 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 842479 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 790170 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18304055 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20435509 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 413815 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1398403 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 40551782 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 779484304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 775974521 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1575256 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5307368 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1562341449 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5999180 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 122789024 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 19760108 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.053277 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.224586 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 18301249 94.57% 94.57% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 1050250 5.43% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 18707349 94.67% 94.67% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1052756 5.33% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19351504 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 25250991712 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 19760108 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 25687014453 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 173970437 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 182391125 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 8969219750 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9158694684 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9025116687 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9158841551 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 220608496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 217386526 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 706093257 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 735766915 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 128968222 # Number of BP lookups -system.cpu1.branchPred.condPredicted 85282466 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6518355 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 89675287 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 55364340 # Number of BTB hits +system.cpu1.branchPred.lookups 134369829 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89463085 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6609561 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 94230263 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 58109960 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.738682 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17439644 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 182879 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4134289 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2557852 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1576437 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 401535 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 61.668044 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17839939 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 183627 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4347444 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2695405 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1652039 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 417102 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1712,96 +1719,86 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 531460 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 531460 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10155 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82594 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 244261 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 287199 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2189.199823 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 12408.912934 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 282304 98.30% 98.30% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 2996 1.04% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 743 0.26% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 602 0.21% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 197 0.07% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 152 0.05% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 103 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 33 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 287199 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 267684 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20635.114538 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18133.747768 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 11911.787641 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 239914 89.63% 89.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26330 9.84% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 756 0.28% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 476 0.18% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 73 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 55 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 22 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 8 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 267684 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 465694213496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.593113 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.550788 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 464589649996 99.76% 99.76% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 559093500 0.12% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 239052500 0.05% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 120378000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 87009500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 57335500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 14978500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 26310000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 396500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 465694213496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 82595 89.05% 89.05% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10155 10.95% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 92750 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 531460 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 561952 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 561952 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11814 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88087 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 261651 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 300301 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2363.057399 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13317.227915 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 298048 99.25% 99.25% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1567 0.52% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 436 0.15% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 167 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 40 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 300301 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 287935 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21029.369476 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18280.568505 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15111.837725 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 285795 99.26% 99.26% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1436 0.50% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 377 0.13% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 181 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 86 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 287935 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 466714959496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.597643 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.555516 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 465490623496 99.74% 99.74% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 621983000 0.13% 99.87% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 266845500 0.06% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 131382500 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 96036000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 60845000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 18797500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 27878000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 546500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 22000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 466714959496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 88088 88.17% 88.17% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11814 11.83% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 99902 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 561952 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 531460 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92750 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 561952 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 99902 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92750 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 624210 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 99902 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 661854 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 93944307 # DTB read hits -system.cpu1.dtb.read_misses 364370 # DTB read misses -system.cpu1.dtb.write_hits 78170381 # DTB write hits -system.cpu1.dtb.write_misses 167090 # DTB write misses -system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 97791245 # DTB read hits +system.cpu1.dtb.read_misses 385118 # DTB read misses +system.cpu1.dtb.write_hits 81245431 # DTB write hits +system.cpu1.dtb.write_misses 176834 # DTB write misses +system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 34720 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 381 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5735 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36850 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 268 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6109 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 39000 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 94308677 # DTB read accesses -system.cpu1.dtb.write_accesses 78337471 # DTB write accesses +system.cpu1.dtb.perms_faults 40755 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 98176363 # DTB read accesses +system.cpu1.dtb.write_accesses 81422265 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 172114688 # DTB hits -system.cpu1.dtb.misses 531460 # DTB misses -system.cpu1.dtb.accesses 172646148 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 179036676 # DTB hits +system.cpu1.dtb.misses 561952 # DTB misses +system.cpu1.dtb.accesses 179598628 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1831,1180 +1828,1166 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 82381 # Table walker walks requested -system.cpu1.itb.walker.walksLong 82381 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1018 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59631 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9853 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 72528 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 882.590172 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 6870.472006 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 72114 99.43% 99.43% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 279 0.38% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 39 0.05% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 75 0.10% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 72528 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 70502 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24022.878784 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22243.496704 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 12757.621468 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 63844 90.56% 90.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 6070 8.61% 99.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 93 0.13% 99.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 382 0.54% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 44 0.06% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 19 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 18 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 70502 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 379792000076 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.874646 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.331269 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 47625596788 12.54% 12.54% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 332150851288 87.46% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 14331500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 990000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 230500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 379792000076 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 59631 98.32% 98.32% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1018 1.68% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 60649 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 84407 # Table walker walks requested +system.cpu1.itb.walker.walksLong 84407 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1027 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60740 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 10156 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 74251 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1057.238286 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8622.114888 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 74015 99.68% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 199 0.27% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 74251 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71923 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24988.821378 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22597.090075 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18666.984039 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 70820 98.47% 98.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 715 0.99% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 265 0.37% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 63 0.09% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 24 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71923 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 410850107648 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.878728 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.326631 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 49848543788 12.13% 12.13% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 360979116860 87.86% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 21177000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1227500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 42500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 410850107648 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 60740 98.34% 98.34% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1027 1.66% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 61767 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82381 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82381 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 84407 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 84407 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60649 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60649 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 143030 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 201934152 # ITB inst hits -system.cpu1.itb.inst_misses 82381 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61767 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61767 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 146174 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 210802915 # ITB inst hits +system.cpu1.itb.inst_misses 84407 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24569 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26222 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202631 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 208943 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 202016533 # ITB inst accesses -system.cpu1.itb.hits 201934152 # DTB hits -system.cpu1.itb.misses 82381 # DTB misses -system.cpu1.itb.accesses 202016533 # DTB accesses -system.cpu1.numPwrStateTransitions 26784 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 13392 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3512583180.059961 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 88770415671.353104 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3351 25.02% 25.02% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 10014 74.78% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 210887322 # ITB inst accesses +system.cpu1.itb.hits 210802915 # DTB hits +system.cpu1.itb.misses 84407 # DTB misses +system.cpu1.itb.accesses 210887322 # DTB accesses +system.cpu1.numPwrStateTransitions 27667 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 13834 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3399006591.183533 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 87524078188.715500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3453 24.96% 24.96% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10352 74.83% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.04% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7430623145540 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 13392 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 343403762637 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47040513947363 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 686817572 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7390880477084 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 13834 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 363085536567 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47021857182433 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 726181462 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 87491536 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 569150585 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 128968222 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 75361836 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 564504137 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14030828 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1743458 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 273069 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5670150 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 713565 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 783781 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 201710843 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1678338 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 26867 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 668195110 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.000138 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.225435 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 86390303 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 594062843 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 134369829 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 78645304 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 601498232 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14253482 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1820697 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 287238 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5988786 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 713679 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 819715 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 210572695 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1658938 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27666 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 704645391 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.988963 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.222689 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 348421230 52.14% 52.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 124504424 18.63% 70.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 42025261 6.29% 77.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 153244195 22.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 370929364 52.64% 52.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 130277469 18.49% 71.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 43725033 6.21% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 159713525 22.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 668195110 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.187777 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.828678 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 102161242 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 311763510 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 215198558 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 34078749 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4993051 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18208977 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2060516 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 590405276 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22672761 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4993051 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 135354794 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 41008219 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 216515907 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 215714387 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 54608752 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 573925738 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5865325 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9111156 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 235226 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 246551 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 22706071 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 10845 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 544713354 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 881414288 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 677140554 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 799785 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 489645115 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 55068233 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14685141 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12835902 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 68922736 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 94552173 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 81340147 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8760661 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7542596 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 552653279 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14818656 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 556478216 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2578197 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 52065959 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 33349277 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 259122 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 668195110 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.832808 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.070079 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 704645391 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.185036 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.818064 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 103020673 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 337373962 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 222407115 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 36734416 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5109225 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18739170 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2055775 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 616426802 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23026844 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5109225 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 137867421 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 45074504 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 232811775 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 223900939 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 59881527 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 599411621 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 6042296 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9969882 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 242190 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 299313 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 25537080 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 11262 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 571214843 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 926423560 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 707359605 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 805393 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 514629531 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 56585312 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15957043 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 14048251 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 73992297 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 98060208 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 84478655 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8950565 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7675207 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 576680308 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 16104006 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 581772484 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2680133 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 53366771 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 34273904 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 266458 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 704645391 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.825624 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.067009 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 364178661 54.50% 54.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 127786531 19.12% 73.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 107346035 16.07% 89.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 61539810 9.21% 98.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7340180 1.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3893 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 385934490 54.77% 54.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 135280434 19.20% 73.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 111501247 15.82% 89.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 64231431 9.12% 98.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7693682 1.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4107 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 668195110 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 704645391 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 55774345 44.07% 44.07% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 53478 0.04% 44.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 18362 0.01% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 33579431 26.53% 70.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 37124892 29.34% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 58591735 44.23% 44.23% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 49305 0.04% 44.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 21310 0.02% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 60 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 35005485 26.43% 70.71% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 38791699 29.29% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 35 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 378772554 68.07% 68.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1203453 0.22% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 69506 0.01% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 82169 0.01% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 96967073 17.43% 85.73% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 79383378 14.27% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 36 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 397008075 68.24% 68.24% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1247296 0.21% 68.46% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 70487 0.01% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 78078 0.01% 68.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.48% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 100884939 17.34% 85.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82483526 14.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 556478216 # Type of FU issued -system.cpu1.iq.rate 0.810227 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 126550523 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227413 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1908944024 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 619142753 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 540109020 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1336236 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 533681 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 496559 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 682200972 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 827732 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2535076 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 581772484 # Type of FU issued +system.cpu1.iq.rate 0.801139 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 132459594 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227683 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 2001993843 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 645760406 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 564750025 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1336243 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 531893 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 495883 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 713403384 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 828658 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2572358 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12050927 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 15964 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 139670 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5367770 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12226985 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16460 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 142391 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5497757 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2479862 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3811174 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2564544 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4190277 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4993051 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6066595 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1484920 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 567600146 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 5109225 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6111838 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1648605 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 592918318 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 94552173 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 81340147 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12593166 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 61012 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1366008 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 139670 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1864288 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2962654 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4826942 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 548760252 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 93936954 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 7198002 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 98060208 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 84478655 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13792326 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 62841 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1527139 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 142391 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1885740 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 3046567 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4932307 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 573876367 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 97784309 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 7346483 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 128211 # number of nop insts executed -system.cpu1.iew.exec_refs 172107181 # number of memory reference insts executed -system.cpu1.iew.exec_branches 103045741 # Number of branches executed -system.cpu1.iew.exec_stores 78170227 # Number of stores executed -system.cpu1.iew.exec_rate 0.798990 # Inst execution rate -system.cpu1.iew.wb_sent 541337937 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 540605579 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 260784878 # num instructions producing a value -system.cpu1.iew.wb_consumers 427489689 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.787117 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610038 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 45375845 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14559534 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4495992 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 659550921 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.781450 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.574730 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 134004 # number of nop insts executed +system.cpu1.iew.exec_refs 179029158 # number of memory reference insts executed +system.cpu1.iew.exec_branches 107707763 # Number of branches executed +system.cpu1.iew.exec_stores 81244849 # Number of stores executed +system.cpu1.iew.exec_rate 0.790266 # Inst execution rate +system.cpu1.iew.wb_sent 565995055 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 565245908 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 273023556 # num instructions producing a value +system.cpu1.iew.wb_consumers 448078183 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.778381 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.609321 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 46535716 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15837548 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4592045 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 695790390 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.775259 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.568649 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 433210493 65.68% 65.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 117319741 17.79% 83.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 50366969 7.64% 91.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16989740 2.58% 93.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12025543 1.82% 95.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8091474 1.23% 96.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5593324 0.85% 97.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3365512 0.51% 98.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12588125 1.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 457970279 65.82% 65.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 124243355 17.86% 83.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 52434114 7.54% 91.21% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 17645088 2.54% 93.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12549968 1.80% 95.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8433891 1.21% 96.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5802471 0.83% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3503250 0.50% 98.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 13207974 1.90% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 659550921 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 437257329 # Number of instructions committed -system.cpu1.commit.committedOps 515405969 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 695790390 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 458018039 # Number of instructions committed +system.cpu1.commit.committedOps 539417542 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 158473622 # Number of memory references committed -system.cpu1.commit.loads 82501245 # Number of loads committed -system.cpu1.commit.membars 3568741 # Number of memory barriers committed -system.cpu1.commit.branches 97797753 # Number of branches committed -system.cpu1.commit.fp_insts 487077 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 473223690 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12865392 # Number of function calls committed. +system.cpu1.commit.refs 164814121 # Number of memory references committed +system.cpu1.commit.loads 85833223 # Number of loads committed +system.cpu1.commit.membars 3719425 # Number of memory barriers committed +system.cpu1.commit.branches 102343051 # Number of branches committed +system.cpu1.commit.fp_insts 486729 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 494686776 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13237013 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 355828768 69.04% 69.04% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 973462 0.19% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 55201 0.01% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 74874 0.01% 69.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.25% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 82501245 16.01% 85.26% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 75972377 14.74% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 373462182 69.23% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1014464 0.19% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 55738 0.01% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 70995 0.01% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 85833223 15.91% 85.36% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78980898 14.64% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 515405969 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12588125 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1203797977 # The number of ROB reads -system.cpu1.rob.rob_writes 1130170940 # The number of ROB writes -system.cpu1.timesIdled 922689 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18622462 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94081017888 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 437257329 # Number of Instructions Simulated -system.cpu1.committedOps 515405969 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.570740 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.570740 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.636643 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.636643 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 647634757 # number of integer regfile reads -system.cpu1.int_regfile_writes 384292228 # number of integer regfile writes -system.cpu1.fp_regfile_reads 785728 # number of floating regfile reads -system.cpu1.fp_regfile_writes 454696 # number of floating regfile writes -system.cpu1.cc_regfile_reads 117471222 # number of cc regfile reads -system.cpu1.cc_regfile_writes 118161265 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1199366647 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14671382 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5153619 # number of replacements -system.cpu1.dcache.tags.tagsinuse 456.044406 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 148207895 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5154131 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.755166 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8517415326000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.044406 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890712 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.890712 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 328622817 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 328622817 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 76967758 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76967758 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 66682281 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 66682281 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 189501 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 189501 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 166829 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 166829 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1726427 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1726427 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1743769 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1743769 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 143816868 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 143816868 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 144006369 # number of overall hits -system.cpu1.dcache.overall_hits::total 144006369 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 5978399 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 5978399 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6727643 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6727643 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 625948 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 625948 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 458256 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 458256 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 242959 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 242959 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183921 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 183921 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13164298 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13164298 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13790246 # number of overall misses -system.cpu1.dcache.overall_misses::total 13790246 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87383841500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 87383841500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119886339095 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 119886339095 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11324190656 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 11324190656 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3328957500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3328957500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379371000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4379371000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2907500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2907500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 218594371251 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 218594371251 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 218594371251 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 218594371251 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82946157 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82946157 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 73409924 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 73409924 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 815449 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 815449 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625085 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 625085 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1969386 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1969386 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1927690 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1927690 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 156981166 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 156981166 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 157796615 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 157796615 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072076 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.072076 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.091645 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.091645 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.767611 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.767611 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.733110 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.733110 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.123368 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.123368 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095410 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095410 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083859 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.083859 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087393 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.087393 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14616.595764 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14616.595764 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17819.961478 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17819.961478 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24711.494571 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24711.494571 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13701.725394 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13701.725394 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23811.152614 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23811.152614 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 539417542 # Class of committed instruction +system.cpu1.commit.bw_lim_events 13207974 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1264391907 # The number of ROB reads +system.cpu1.rob.rob_writes 1180722952 # The number of ROB writes +system.cpu1.timesIdled 944459 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 21536071 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94043695657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 458018039 # Number of Instructions Simulated +system.cpu1.committedOps 539417542 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.585487 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.585487 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.630721 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.630721 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 677403787 # number of integer regfile reads +system.cpu1.int_regfile_writes 401367044 # number of integer regfile writes +system.cpu1.fp_regfile_reads 791707 # number of floating regfile reads +system.cpu1.fp_regfile_writes 438600 # number of floating regfile writes +system.cpu1.cc_regfile_reads 124889457 # number of cc regfile reads +system.cpu1.cc_regfile_writes 125620500 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1260290191 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15974322 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5362331 # number of replacements +system.cpu1.dcache.tags.tagsinuse 456.510727 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 153804268 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5362842 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.679620 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8517840775000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.510727 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.891623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 341608540 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 341608540 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 79940930 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 79940930 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 69078558 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 69078558 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191831 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 191831 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 170764 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 170764 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1820637 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1820637 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1828950 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1828950 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 149190252 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 149190252 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 149382083 # number of overall hits +system.cpu1.dcache.overall_hits::total 149382083 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6220385 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6220385 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7237581 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7237581 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 689658 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 689658 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 463987 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 463987 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 244543 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 244543 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192296 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 192296 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13921953 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13921953 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14611611 # number of overall misses +system.cpu1.dcache.overall_misses::total 14611611 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96362388500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 96362388500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 134833660621 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 134833660621 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11613680644 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 11613680644 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3499456000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3499456000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4567503000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4567503000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3019500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3019500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 242809729765 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 242809729765 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 242809729765 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 242809729765 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 86161315 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 86161315 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 76316139 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 76316139 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 881489 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 881489 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 634751 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 634751 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2065180 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2065180 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2021246 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2021246 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 163112205 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 163112205 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 163993694 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 163993694 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072195 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.072195 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094837 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.094837 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.782378 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.782378 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.730975 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.730975 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118412 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118412 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095137 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095137 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085352 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.085352 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089099 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.089099 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15491.386546 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15491.386546 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18629.658255 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18629.658255 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25030.185423 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25030.185423 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14310.186757 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14310.186757 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23752.459750 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23752.459750 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16605.091381 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16605.091381 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15851.375766 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15851.375766 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 2917967 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18895353 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 374678 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 668758 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.787933 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 28.254395 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5153631 # number of writebacks -system.cpu1.dcache.writebacks::total 5153631 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3023211 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3023211 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5427179 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5427179 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3743 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3743 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 127495 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 127495 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8454133 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8454133 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8454133 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8454133 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2955188 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2955188 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1300464 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1300464 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 625861 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 625861 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454513 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 454513 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115464 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115464 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183920 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 183920 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4710165 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4710165 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5336026 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5336026 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21232 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21232 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17440.780741 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17440.780741 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16617.587873 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16617.587873 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 3018250 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 21738633 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 378529 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 731712 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.973629 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 29.709275 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 5362354 # number of writebacks +system.cpu1.dcache.writebacks::total 5362354 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3187456 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3187456 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5861363 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5861363 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3594 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3594 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 128092 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 128092 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9052413 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9052413 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9052413 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9052413 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3032929 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3032929 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1376218 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1376218 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 689576 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 689576 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460393 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 460393 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116451 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116451 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192288 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 192288 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4869540 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4869540 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5559116 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5559116 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21291 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21291 # number of ReadReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40642 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40642 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40128990000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40128990000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24368462066 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24368462066 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13718666000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13718666000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10741056156 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10741056156 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1514532000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1514532000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4195522000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4195522000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2836500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2836500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75238508222 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 75238508222 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88957174222 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 88957174222 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3718611500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3718611500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3718611500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3718611500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035628 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035628 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017715 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017715 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.767505 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.767505 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.727122 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.727122 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058629 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058629 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095410 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095410 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030005 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030005 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033816 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033816 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13579.166537 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13579.166537 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18738.282694 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18738.282694 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21919.669064 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21919.669064 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23632.010869 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23632.010869 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13116.919559 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13116.919559 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22811.668117 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22811.668117 # average StoreCondReq mshr miss latency +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40701 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40701 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42726170500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42726170500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26732145261 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26732145261 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16635879000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16635879000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11021618644 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11021618644 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587191500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587191500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4375287000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4375287000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2947500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2947500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 80479934405 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 80479934405 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 97115813405 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 97115813405 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3797634000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3797634000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3797634000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3797634000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035201 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035201 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018033 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018033 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.782285 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.782285 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725313 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.725313 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056388 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056388 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095133 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095133 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029854 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029854 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033898 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033898 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14087.428522 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14087.428522 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19424.353744 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19424.353744 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24124.794076 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.794076 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23939.587796 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23939.587796 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13629.694034 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13629.694034 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22753.822391 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22753.822391 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15973.645981 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15973.645981 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16671.053369 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16671.053369 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175141.837792 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175141.837792 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91496.764431 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91496.764431 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 6014648 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.532915 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 195349774 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 6015160 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 32.476239 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8517720712000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.532915 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979556 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979556 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16527.214974 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16527.214974 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17469.650463 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17469.650463 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178368.042835 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178368.042835 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93305.668165 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 93305.668165 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5902862 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.529159 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 204324856 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5903374 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.611538 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8518180301500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.529159 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979549 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.979549 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 409423979 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 409423979 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 195349774 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 195349774 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 195349774 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 195349774 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 195349774 # number of overall hits -system.cpu1.icache.overall_hits::total 195349774 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6354622 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6354622 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6354622 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6354622 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6354622 # number of overall misses -system.cpu1.icache.overall_misses::total 6354622 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 66668444908 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 66668444908 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 66668444908 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 66668444908 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 66668444908 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 66668444908 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 201704396 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 201704396 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 201704396 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 201704396 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 201704396 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 201704396 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031505 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.031505 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031505 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.031505 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031505 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.031505 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10491.331335 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10491.331335 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10491.331335 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10491.331335 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9555681 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 472 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 727552 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.134018 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 118 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 6014648 # number of writebacks -system.cpu1.icache.writebacks::total 6014648 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339435 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 339435 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 339435 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 339435 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 339435 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 339435 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6015187 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 6015187 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 6015187 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 6015187 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 6015187 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 6015187 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 68 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 68 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 68 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 68 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 60428904539 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 60428904539 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 60428904539 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 60428904539 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 60428904539 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 60428904539 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6183499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6183499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6183499 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6183499 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029822 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.029822 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.029822 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10046.055848 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90933.808824 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90933.808824 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6826847 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6833838 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 6347 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.tags.tag_accesses 427035149 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 427035149 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 204324856 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 204324856 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 204324856 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 204324856 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 204324856 # number of overall hits +system.cpu1.icache.overall_hits::total 204324856 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6241016 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6241016 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6241016 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6241016 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6241016 # number of overall misses +system.cpu1.icache.overall_misses::total 6241016 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 68483006769 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 68483006769 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 68483006769 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 68483006769 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 68483006769 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 68483006769 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 210565872 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 210565872 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 210565872 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 210565872 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 210565872 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 210565872 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029639 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029639 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029639 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029639 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029639 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029639 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10973.054190 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10973.054190 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10973.054190 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10973.054190 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 10089385 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 780 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 729550 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.829600 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 390 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 5902862 # number of writebacks +system.cpu1.icache.writebacks::total 5902862 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 337611 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 337611 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 337611 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 337611 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 337611 # 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number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 61792345334 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 61792345334 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 61792345334 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 61792345334 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 61792345334 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 61792345334 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7079498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7079498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7079498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 7079498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028036 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028036 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028036 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10467.238032 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 105664.149254 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 105664.149254 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7372835 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7380898 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 7290 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 835722 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1955228 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 12896.405710 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10261646 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1970971 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.206391 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 895622 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2111480 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12950.875249 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10279593 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2126904 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.833125 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.365224 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 35.187602 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 26.957161 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 235.895723 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.768943 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002148 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001645 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014398 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.787134 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 398 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15279 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 92 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2171 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6847 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4119 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1911 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.024292 # 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number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7886275 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 44 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 841994 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 841994 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5485264 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 5485264 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2792582 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2792582 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 201829 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 201829 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 536780 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 184573 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5485264 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3634576 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9841193 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 536780 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 184573 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5485264 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3634576 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9841193 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18586 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8726 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 27312 # number of ReadReq misses -system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses -system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 218938 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 218938 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 183916 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 183916 # number of SCUpgradeReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 12615.195694 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 33.253837 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 24.384299 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 278.041418 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.769970 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002030 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001488 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.016970 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.790459 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 414 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14899 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 65 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 114 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 107 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 89 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 279 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1377 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5586 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5487 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2170 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.025269 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909363 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 393006433 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 393006433 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 563217 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 188120 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 751337 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3404083 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3404083 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 7859423 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 7859423 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 897837 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 897837 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5343474 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 5343474 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2865962 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2865962 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 200218 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 200218 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 563217 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 188120 # 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number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6576000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3627092000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3633668000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.038550 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999799 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999799 # 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mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088092 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242452 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242452 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.553648 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.553648 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.033331 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044154 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.236871 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.146352 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.033331 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044154 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.236871 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.210915 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.210915 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094846 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251455 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251455 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.563140 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.563140 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242071 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154001 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242071 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206422 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24907.731273 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47104.456602 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18790.618769 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18790.618769 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15296.842015 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15296.842015 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33451.032223 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33451.032223 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28270.219367 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28485.685373 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28485.685373 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26859.329809 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26859.329809 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29059.233508 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34310.488986 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167132.912585 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166865.680751 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87312.779883 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87306.288381 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 23161545 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11911126 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 559932 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 559928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.219384 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28455.103531 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55438.584063 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18715.799153 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18715.799153 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15240.681672 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15240.681672 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 601875 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 601875 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36897.157204 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36897.157204 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30741.251735 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31043.545359 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31043.545359 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26979.327768 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26979.327768 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32224.041226 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31699.107813 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32224.041226 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38774.214418 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170357.991640 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170131.472984 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 89115.549986 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 89130.396389 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 23401917 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12050394 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1685 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 583324 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 583320 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 858463 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10650090 # Transaction distribution +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 895492 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10720388 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 19410 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 19410 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4372034 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7887876 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1202832 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 877539 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 29 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 412195 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 333118 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 458356 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1116808 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1095312 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6015187 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4685876 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 509592 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 452179 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18045125 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16655613 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 406321 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179507 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36286566 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 769908416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 641765745 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1546392 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4442928 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1417663481 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4824103 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 76247568 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 17122714 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.052642 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.223318 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4582624 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7861129 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1298468 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 967756 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 436519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348532 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 480708 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1183332 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1160512 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5903405 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4845353 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 522418 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 458323 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17709789 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17335665 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416038 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1239832 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 36701324 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 755601072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 668583302 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1583448 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4670440 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1430438262 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5153113 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 82064432 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 17599300 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.053842 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.225707 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 16221347 94.74% 94.74% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 901363 5.26% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 16651717 94.62% 94.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 947579 5.38% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 17122714 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23027796506 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 17599300 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 23252082447 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 160947650 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 167523282 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 9028759604 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8861086123 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7641863842 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7965231666 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 213393747 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 218506693 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 624968323 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 656902733 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40315 # Transaction distribution -system.iobus.trans_dist::ReadResp 40315 # Transaction distribution -system.iobus.trans_dist::WriteReq 136630 # Transaction distribution -system.iobus.trans_dist::WriteResp 136630 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47698 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40332 # Transaction distribution +system.iobus.trans_dist::ReadResp 40332 # Transaction distribution +system.iobus.trans_dist::WriteReq 136631 # Transaction distribution +system.iobus.trans_dist::WriteResp 136631 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3015,15 +2998,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353890 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47718 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353926 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3034,27 +3017,27 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155710 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496732 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36996503 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496841 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36933004 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -3062,77 +3045,77 @@ system.iobus.reqLayer15.occupancy 10500 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24232502 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24511500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36410001 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36406001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568919799 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569333352 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92681000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147926000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115610 # number of replacements -system.iocache.tags.tagsinuse 11.211324 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115627 # number of replacements +system.iocache.tags.tagsinuse 11.209625 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115626 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115643 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9155814843000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.413268 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.798056 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463329 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.237379 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.700708 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9156281985000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.417323 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.792302 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463583 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.237019 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.700602 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040892 # Number of tag accesses -system.iocache.tags.data_accesses 1040892 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1041036 # Number of tag accesses +system.iocache.tags.data_accesses 1041036 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses -system.iocache.demand_misses::total 115655 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115631 # number of demand (read+write) misses +system.iocache.demand_misses::total 115671 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115615 # number of overall misses -system.iocache.overall_misses::total 115655 # number of overall misses +system.iocache.overall_misses::realview.ide 115631 # number of overall misses +system.iocache.overall_misses::total 115671 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1677259553 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1682459553 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1786499757 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1791699757 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12947566246 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12947566246 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13185420595 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13185420595 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14624825799 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14630394799 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14971920352 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14977489352 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14624825799 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14630394799 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14971920352 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14977489352 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3147,52 +3130,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 188731.805221 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 188531.998319 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 200662.670673 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 200413.843065 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121313.678191 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 121313.678191 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123542.281266 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 123542.281266 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126500.322502 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129483.529597 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126500.322502 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33395 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129483.529597 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 39692 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3537 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.557813 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.221939 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3614 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 44004 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.166931 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_blocks::1024 50513 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1395 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 577 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9525 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 271 # 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average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162146.824876 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149138.789590 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 122053.187311 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 77125.713494 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77908.870645 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74383.639767 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3980803 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2353726 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3243 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.107586 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125299 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.115771 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.011449 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016031 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.013612 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.638758 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.459123 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.564225 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.224199 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166057 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260318 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781516 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.457585 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.688886 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.278758 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.278758 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20295.679445 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20793.680153 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20544.742838 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24188.080495 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24720.642769 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24484.192440 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98536.210915 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99453.454152 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 98845.895687 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101990.786172 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108368.427426 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126261.676330 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24695.536494 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20746.752089 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23945.493776 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158502.709069 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152366.950068 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124514.405742 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75218.020737 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 79700.729748 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 75885.828904 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 4262418 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2509154 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3063 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 59676 # Transaction distribution -system.membus.trans_dist::ReadResp 985495 # Transaction distribution -system.membus.trans_dist::WriteReq 38244 # Transaction distribution -system.membus.trans_dist::WriteResp 38244 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1315010 # Transaction distribution -system.membus.trans_dist::CleanEvict 256715 # Transaction distribution -system.membus.trans_dist::UpgradeReq 339680 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 271581 # Transaction distribution -system.membus.trans_dist::UpgradeResp 24 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 147332 # Transaction distribution -system.membus.trans_dist::ReadExResp 134542 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 925819 # Transaction distribution -system.membus.trans_dist::InvalidateReq 674453 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122580 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 59629 # Transaction distribution +system.membus.trans_dist::ReadResp 1085265 # Transaction distribution +system.membus.trans_dist::WriteReq 38211 # Transaction distribution +system.membus.trans_dist::WriteResp 38211 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1413261 # Transaction distribution +system.membus.trans_dist::CleanEvict 284296 # Transaction distribution +system.membus.trans_dist::UpgradeReq 353595 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 284030 # Transaction distribution +system.membus.trans_dist::UpgradeResp 23 # Transaction distribution +system.membus.trans_dist::ReadExReq 155418 # Transaction distribution +system.membus.trans_dist::ReadExResp 141619 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1025636 # Transaction distribution +system.membus.trans_dist::InvalidateReq 695069 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4797896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4945870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237932 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237932 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5183802 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155710 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5185454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5333270 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238137 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238137 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5571407 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144939472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 145146374 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7255040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 152401414 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 572055 # Total snoops (count) -system.membus.snoopTraffic 191360 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2456788 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015156 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.122173 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 158067712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 158274271 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7266112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 165540383 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 598647 # Total snoops (count) +system.membus.snoopTraffic 181312 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2611590 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013385 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.114916 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2419553 98.48% 98.48% # Request fanout histogram -system.membus.snoop_fanout::1 37235 1.52% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2576634 98.66% 98.66% # Request fanout histogram +system.membus.snoop_fanout::1 34956 1.34% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2456788 # Request fanout histogram -system.membus.reqLayer0.occupancy 98064494 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2611590 # Request fanout histogram +system.membus.reqLayer0.occupancy 98274995 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21142497 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20993495 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9055699898 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9731390131 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5680392120 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6232103011 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45554532 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45620246 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3907,83 +3884,82 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 11893981 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6468498 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1904661 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 211231 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 193743 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 17488 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 59678 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4527289 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38244 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38244 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4050158 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2718586 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 717362 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 373497 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1090859 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 293033 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 293033 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4468431 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 869390 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 835427 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9945746 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7459601 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17405347 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252717925 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 183230753 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 435948678 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2969827 # Total snoops (count) -system.toL2Bus.snoopTraffic 128627856 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8396274 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.355668 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.483046 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12430379 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6756092 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1976828 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 231635 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 213178 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 18457 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 59631 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4752657 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38211 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38211 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4279629 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2861492 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 742959 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 389463 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1132422 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 304770 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 304770 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4693673 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 888953 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 857088 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10167135 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8009990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18177125 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 258318649 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198738470 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 457057119 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3168754 # Total snoops (count) +system.toL2Bus.snoopTraffic 137382864 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8831298 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.353414 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.482382 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5427479 64.64% 64.64% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2951307 35.15% 99.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 17488 0.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5728650 64.87% 64.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3084191 34.92% 99.79% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 18457 0.21% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8396274 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9289434840 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8831298 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9716591105 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2606647 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2596400 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4518737086 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4626263938 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3678115853 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3958447661 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5420 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 5035 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13392 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 13834 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal index cbe8d6472..b30f1e5a4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal @@ -33,134 +33,134 @@ [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000015] Console: colour dummy device 80x25
-[ 0.000016] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000017] pid_max: default: 32768 minimum: 301
-[ 0.000024] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000025] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000098] hw perfevents: no hardware support available
+[ 0.000017] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000018] pid_max: default: 32768 minimum: 301
+[ 0.000025] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000026] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000102] hw perfevents: no hardware support available
[ 0.060026] CPU1: Booted secondary processor
-[ 1.080051] CPU2: failed to come online
-[ 2.100096] CPU3: failed to come online
-[ 2.100099] Brought up 2 CPUs
-[ 2.100099] SMP: Total of 2 processors activated.
-[ 2.100138] devtmpfs: initialized
+[ 1.080049] CPU2: failed to come online
+[ 2.100093] CPU3: failed to come online
+[ 2.100095] Brought up 2 CPUs
+[ 2.100096] SMP: Total of 2 processors activated.
+[ 2.100135] devtmpfs: initialized
[ 2.100443] atomic64_test: passed
-[ 2.100470] regulator-dummy: no parameters
-[ 2.100693] NET: Registered protocol family 16
-[ 2.100775] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.100781] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.100925] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.100928] Serial: AMBA PL011 UART driver
-[ 2.101044] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.101067] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.101650] console [ttyAMA0] enabled
-[ 2.101714] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.101743] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.101771] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.101798] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.140207] 3V3: 3300 mV
-[ 2.140239] vgaarb: loaded
-[ 2.140270] SCSI subsystem initialized
-[ 2.140299] libata version 3.00 loaded.
-[ 2.140331] usbcore: registered new interface driver usbfs
-[ 2.140346] usbcore: registered new interface driver hub
-[ 2.140370] usbcore: registered new device driver usb
-[ 2.140390] pps_core: LinuxPPS API ver. 1 registered
-[ 2.140399] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.140417] PTP clock support registered
-[ 2.140503] Switched to clocksource arch_sys_counter
-[ 2.141444] NET: Registered protocol family 2
-[ 2.141497] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.141512] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.141527] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.141543] TCP: reno registered
-[ 2.141550] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141561] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141588] NET: Registered protocol family 1
-[ 2.141628] RPC: Registered named UNIX socket transport module.
-[ 2.141638] RPC: Registered udp transport module.
-[ 2.141647] RPC: Registered tcp transport module.
-[ 2.141655] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.141667] PCI: CLS 0 bytes, default 64
-[ 2.141771] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.141835] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.142859] fuse init (API version 7.23)
-[ 2.142916] msgmni has been set to 469
-[ 2.143149] io scheduler noop registered
-[ 2.143186] io scheduler cfq registered (default)
-[ 2.143405] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.143418] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.143429] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.143442] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.143451] pci_bus 0000:00: scanning bus
-[ 2.143461] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.143473] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.143487] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.143514] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.143526] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.143536] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.143547] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.143557] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.143567] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.143578] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.143604] pci_bus 0000:00: fixups for bus
-[ 2.143612] pci_bus 0000:00: bus scan returning with max=00
-[ 2.143623] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.143640] pci 0000:00:00.0: fixup irq: got 33
-[ 2.143648] pci 0000:00:00.0: assigning IRQ 33
-[ 2.143658] pci 0000:00:01.0: fixup irq: got 34
-[ 2.143666] pci 0000:00:01.0: assigning IRQ 34
-[ 2.143676] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.143689] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.143702] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.143715] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.143726] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.143737] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.143748] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.143759] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.144053] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.144214] ata_piix 0000:00:01.0: version 2.13
-[ 2.144224] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.144241] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.144410] scsi0 : ata_piix
-[ 2.144458] scsi1 : ata_piix
-[ 2.144479] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.144492] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.144562] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.144575] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.144587] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.144599] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290528] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290538] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.290562] ata1.00: configured for UDMA/33
-[ 2.290599] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.290672] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.290676] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.290693] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.290693] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.290701] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.290789] sda: sda1
-[ 2.290864] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.410776] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.410789] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.410807] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.410817] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.410834] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.410846] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.410894] usbcore: registered new interface driver usb-storage
-[ 2.410940] mousedev: PS/2 mouse device common for all mice
-[ 2.411046] usbcore: registered new interface driver usbhid
-[ 2.411056] usbhid: USB HID core driver
-[ 2.411079] TCP: cubic registered
-[ 2.411086] NET: Registered protocol family 17
- -[ 2.411396] devtmpfs: mounted
-[ 2.411414] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 2.100471] regulator-dummy: no parameters
+[ 2.100695] NET: Registered protocol family 16
+[ 2.100778] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.100785] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.100927] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.100930] Serial: AMBA PL011 UART driver
+[ 2.101048] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.101072] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.101655] console [ttyAMA0] enabled
+[ 2.101721] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.101750] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.101779] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.101807] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.140200] 3V3: 3300 mV
+[ 2.140234] vgaarb: loaded
+[ 2.140266] SCSI subsystem initialized
+[ 2.140287] libata version 3.00 loaded.
+[ 2.140319] usbcore: registered new interface driver usbfs
+[ 2.140334] usbcore: registered new interface driver hub
+[ 2.140351] usbcore: registered new device driver usb
+[ 2.140371] pps_core: LinuxPPS API ver. 1 registered
+[ 2.140380] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.140398] PTP clock support registered
+[ 2.140483] Switched to clocksource arch_sys_counter
+[ 2.141317] NET: Registered protocol family 2
+[ 2.141370] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.141386] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.141401] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.141417] TCP: reno registered
+[ 2.141424] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141435] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141463] NET: Registered protocol family 1
+[ 2.141503] RPC: Registered named UNIX socket transport module.
+[ 2.141513] RPC: Registered udp transport module.
+[ 2.141522] RPC: Registered tcp transport module.
+[ 2.141530] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.141542] PCI: CLS 0 bytes, default 64
+[ 2.141648] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.141718] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.142752] fuse init (API version 7.23)
+[ 2.142809] msgmni has been set to 469
+[ 2.142890] io scheduler noop registered
+[ 2.142925] io scheduler cfq registered (default)
+[ 2.143148] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.143161] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.143172] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.143184] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.143195] pci_bus 0000:00: scanning bus
+[ 2.143204] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.143217] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.143231] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.143258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.143270] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.143280] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.143291] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.143302] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.143312] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.143323] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.143351] pci_bus 0000:00: fixups for bus
+[ 2.143359] pci_bus 0000:00: bus scan returning with max=00
+[ 2.143371] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.143388] pci 0000:00:00.0: fixup irq: got 33
+[ 2.143397] pci 0000:00:00.0: assigning IRQ 33
+[ 2.143406] pci 0000:00:01.0: fixup irq: got 34
+[ 2.143415] pci 0000:00:01.0: assigning IRQ 34
+[ 2.143425] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.143438] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.143451] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.143463] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.143475] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.143486] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.143497] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.143509] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.143798] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.143959] ata_piix 0000:00:01.0: version 2.13
+[ 2.143970] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.143987] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.144155] scsi0 : ata_piix
+[ 2.144211] scsi1 : ata_piix
+[ 2.144232] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.144244] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.144315] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.144327] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.144340] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.144352] e1000 0000:00:00.0: enabling bus mastering
+[ 2.300506] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.300516] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.300541] ata1.00: configured for UDMA/33
+[ 2.300579] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.300655] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.300670] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.300700] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.300709] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.300725] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.300818] sda: sda1
+[ 2.300900] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.420759] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.420772] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.420790] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.420801] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.420818] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.420830] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.420879] usbcore: registered new interface driver usb-storage
+[ 2.420923] mousedev: PS/2 mouse device common for all mice
+[ 2.421032] usbcore: registered new interface driver usbhid
+[ 2.421042] usbhid: USB HID core driver
+[ 2.421068] TCP: cubic registered
+[ 2.421076] NET: Registered protocol family 17
+ +[ 2.421363] devtmpfs: mounted
+[ 2.421381] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.447448] udevd[609]: starting version 182
+[ 2.457503] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.532422] random: dd urandom read with 18 bits of entropy available
+[ 2.532427] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.640730] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.640714] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini index b9ad3e9e4..b4ce59a93 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -229,7 +229,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -723,7 +723,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -840,7 +840,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -885,7 +885,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -897,7 +897,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -929,29 +929,36 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -971,6 +978,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -980,7 +988,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1002,9 +1010,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1357,7 +1365,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1670,10 +1678,11 @@ pio=system.iobus.master[21] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain -conf_table_reported=true +conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1681,7 +1690,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -1912,6 +1921,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1919,7 +1929,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout index 07f342b7e..34f117433 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12234 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:05:44 +gem5 executing on e108600-lin, pid 17601 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3 Selected 64-bit ARM architecture, updating default disk image... @@ -15,4 +15,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51327142820000 because m5_exit instruction encountered +Exiting @ tick 51558697863000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 7623e0029..2bd86426a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.558015 # Number of seconds simulated -sim_ticks 51558014828000 # Number of ticks simulated -final_tick 51558014828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.558698 # Number of seconds simulated +sim_ticks 51558697863000 # Number of ticks simulated +final_tick 51558697863000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133865 # Simulator instruction rate (inst/s) -host_op_rate 157345 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6235119796 # Simulator tick rate (ticks/s) -host_mem_usage 696436 # Number of bytes of host memory used -host_seconds 8268.97 # Real time elapsed on the host -sim_insts 1106923026 # Number of instructions simulated -sim_ops 1301083589 # Number of ops (including micro ops) simulated +host_inst_rate 167711 # Simulator instruction rate (inst/s) +host_op_rate 197118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7760882097 # Simulator tick rate (ticks/s) +host_mem_usage 692228 # Number of bytes of host memory used +host_seconds 6643.41 # Real time elapsed on the host +sim_insts 1114173091 # Number of instructions simulated +sim_ops 1309536110 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 667968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 559488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6546400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112650248 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 429376 # Number of bytes read from this memory -system.physmem.bytes_read::total 120853480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6546400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6546400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 140957120 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 691712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 570944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6573600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 114559048 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428096 # Number of bytes read from this memory +system.physmem.bytes_read::total 122823400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6573600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6573600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 143392768 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 140977700 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10437 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 118240 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1760173 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6709 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1904301 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2202455 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 143413348 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10808 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 118665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1789998 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6689 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1935081 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2240512 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2205028 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 10852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 126972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2184922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2344029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 126972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 126972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2733952 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 2243085 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 13416 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 11074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 127497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2221915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2382205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 127497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 127497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2781156 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2734351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2733952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 10852 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 126972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2185321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5078380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1904301 # Number of read requests accepted -system.physmem.writeReqs 2205028 # Number of write requests accepted -system.physmem.readBursts 1904301 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2205028 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 121838144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue -system.physmem.bytesWritten 140976896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 120853480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 140977700 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 2781555 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2781156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 13416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 11074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 127497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2222314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5163760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1935081 # Number of read requests accepted +system.physmem.writeReqs 2243085 # Number of write requests accepted +system.physmem.readBursts 1935081 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2243085 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 123796992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48192 # Total number of bytes read from write queue +system.physmem.bytesWritten 143410368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 122823400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 143413348 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 753 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2282 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114327 # Per bank write bursts -system.physmem.perBankRdBursts::1 123692 # Per bank write bursts -system.physmem.perBankRdBursts::2 118245 # Per bank write bursts -system.physmem.perBankRdBursts::3 117057 # Per bank write bursts -system.physmem.perBankRdBursts::4 115229 # Per bank write bursts -system.physmem.perBankRdBursts::5 125268 # Per bank write bursts -system.physmem.perBankRdBursts::6 115683 # Per bank write bursts -system.physmem.perBankRdBursts::7 119593 # Per bank write bursts -system.physmem.perBankRdBursts::8 115543 # Per bank write bursts -system.physmem.perBankRdBursts::9 144676 # Per bank write bursts -system.physmem.perBankRdBursts::10 112600 # Per bank write bursts -system.physmem.perBankRdBursts::11 120122 # Per bank write bursts -system.physmem.perBankRdBursts::12 113965 # Per bank write bursts -system.physmem.perBankRdBursts::13 118266 # Per bank write bursts -system.physmem.perBankRdBursts::14 113146 # Per bank write bursts -system.physmem.perBankRdBursts::15 116309 # Per bank write bursts -system.physmem.perBankWrBursts::0 135142 # Per bank write bursts -system.physmem.perBankWrBursts::1 141643 # Per bank write bursts -system.physmem.perBankWrBursts::2 136917 # Per bank write bursts -system.physmem.perBankWrBursts::3 137997 # Per bank write bursts -system.physmem.perBankWrBursts::4 135684 # Per bank write bursts -system.physmem.perBankWrBursts::5 143871 # Per bank write bursts -system.physmem.perBankWrBursts::6 135153 # Per bank write bursts -system.physmem.perBankWrBursts::7 138864 # Per bank write bursts -system.physmem.perBankWrBursts::8 135935 # Per bank write bursts -system.physmem.perBankWrBursts::9 142790 # Per bank write bursts -system.physmem.perBankWrBursts::10 134947 # Per bank write bursts -system.physmem.perBankWrBursts::11 140191 # Per bank write bursts -system.physmem.perBankWrBursts::12 134987 # Per bank write bursts -system.physmem.perBankWrBursts::13 137976 # Per bank write bursts -system.physmem.perBankWrBursts::14 134592 # Per bank write bursts -system.physmem.perBankWrBursts::15 136075 # Per bank write bursts +system.physmem.perBankRdBursts::0 114857 # Per bank write bursts +system.physmem.perBankRdBursts::1 123887 # Per bank write bursts +system.physmem.perBankRdBursts::2 121380 # Per bank write bursts +system.physmem.perBankRdBursts::3 115864 # Per bank write bursts +system.physmem.perBankRdBursts::4 115150 # Per bank write bursts +system.physmem.perBankRdBursts::5 124779 # Per bank write bursts +system.physmem.perBankRdBursts::6 116343 # Per bank write bursts +system.physmem.perBankRdBursts::7 120532 # Per bank write bursts +system.physmem.perBankRdBursts::8 117169 # Per bank write bursts +system.physmem.perBankRdBursts::9 147715 # Per bank write bursts +system.physmem.perBankRdBursts::10 116324 # Per bank write bursts +system.physmem.perBankRdBursts::11 125031 # Per bank write bursts +system.physmem.perBankRdBursts::12 116553 # Per bank write bursts +system.physmem.perBankRdBursts::13 122187 # Per bank write bursts +system.physmem.perBankRdBursts::14 118707 # Per bank write bursts +system.physmem.perBankRdBursts::15 117850 # Per bank write bursts +system.physmem.perBankWrBursts::0 135590 # Per bank write bursts +system.physmem.perBankWrBursts::1 141676 # Per bank write bursts +system.physmem.perBankWrBursts::2 140587 # Per bank write bursts +system.physmem.perBankWrBursts::3 138605 # Per bank write bursts +system.physmem.perBankWrBursts::4 137623 # Per bank write bursts +system.physmem.perBankWrBursts::5 144276 # Per bank write bursts +system.physmem.perBankWrBursts::6 136529 # Per bank write bursts +system.physmem.perBankWrBursts::7 140386 # Per bank write bursts +system.physmem.perBankWrBursts::8 138327 # Per bank write bursts +system.physmem.perBankWrBursts::9 145050 # Per bank write bursts +system.physmem.perBankWrBursts::10 137213 # Per bank write bursts +system.physmem.perBankWrBursts::11 144076 # Per bank write bursts +system.physmem.perBankWrBursts::12 138694 # Per bank write bursts +system.physmem.perBankWrBursts::13 142077 # Per bank write bursts +system.physmem.perBankWrBursts::14 140963 # Per bank write bursts +system.physmem.perBankWrBursts::15 139115 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 125 # Number of times write queue was full causing retry -system.physmem.totGap 51558013451500 # Total gap between requests +system.physmem.numWrRetry 498 # Number of times write queue was full causing retry +system.physmem.totGap 51558696478500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1883016 # Read request sizes (log2) +system.physmem.readPktSize::6 1913796 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2202455 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1140639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 689076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 126 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2240512 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1142122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 697940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 62817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 107 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,170 +160,167 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 38490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 83702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 117171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 125843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 130438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 138248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 140822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 137539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 142466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 143357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 133954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 146358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 136372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 127299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 130102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 120942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 365 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 933198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.628105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.352526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.404332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 371108 39.77% 39.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 233427 25.01% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88383 9.47% 74.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51664 5.54% 79.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37413 4.01% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26389 2.83% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21045 2.26% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17945 1.92% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 85824 9.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 933198 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 116229 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.379053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 52.340079 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 116223 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 28657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 36011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 84715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 118224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 127097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 131612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 133869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 139104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 141132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 137785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 140939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 143104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 134560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 133279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 134737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 146876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 129080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 132587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1141 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 951139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.933676 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.585937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.458614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 376624 39.60% 39.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 238014 25.02% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 91172 9.59% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 53576 5.63% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 39458 4.15% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 27371 2.88% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21519 2.26% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17750 1.87% 90.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 85655 9.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 951139 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 118362 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.342416 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 51.876252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 118357 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 116229 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 116228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.951965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.478061 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.079115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 111884 96.26% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 1770 1.52% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 397 0.34% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 626 0.54% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 488 0.42% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 246 0.21% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 362 0.31% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 120 0.10% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 64 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 59 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 51 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 11 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 17 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 10 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 37 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 24 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 14 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 5 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-623 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::624-639 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::752-767 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::976-991 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 116228 # Writes before turning the bus around for reads -system.physmem.totQLat 42075497859 # Total ticks spent queuing -system.physmem.totMemAccLat 77770266609 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9518605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22101.71 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 118362 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 118362 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.931642 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.417353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.979781 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 114164 96.45% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 1862 1.57% 98.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1234 1.04% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 621 0.52% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 196 0.17% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 102 0.09% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 42 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 35 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 40 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 18 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 4 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 11 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-895 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1024-1055 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 118362 # Writes before turning the bus around for reads +system.physmem.totQLat 71570448504 # Total ticks spent queuing +system.physmem.totMemAccLat 107839098504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9671640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37000.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40851.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.73 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 55750.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing -system.physmem.readRowHits 1533744 # Number of row buffer hits during reads -system.physmem.writeRowHits 1639539 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes -system.physmem.avgGap 12546577.18 # Average gap between requests -system.physmem.pageHitRate 77.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3530119320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1926156375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7402894200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 7162084800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1313077918185 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29782982922000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34483600624320 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.831109 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49545451951432 # Time in different power states -system.physmem_0.memoryStateTime::REF 1721635240000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 290927248568 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3524804640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1923256500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7446082800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 7111728720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1314046606680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29782133195250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34483704204030 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833118 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49544014933949 # Time in different power states -system.physmem_1.memoryStateTime::REF 1721635240000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 292364518051 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.69 # Average write queue length when enqueuing +system.physmem.readRowHits 1560611 # Number of row buffer hits during reads +system.physmem.writeRowHits 1663363 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.23 # Row buffer hit rate for writes +system.physmem.avgGap 12340030.64 # Average gap between requests +system.physmem.pageHitRate 77.22 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3363189900 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1787570235 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6802934880 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5821719840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 51899586960.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 51612190140 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3200334720 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 101759183310 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 76295730720 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12252381205680 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12554961718635 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.508122 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51437094541003 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5396479999 # Time in different power states +system.physmem_0.memoryStateTime::REF 22052840000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51015251458000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 198686963242 # Time in different power states +system.physmem_0.memoryStateTime::ACT 94153955748 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 223156166011 # Time in different power states +system.physmem_1.actEnergy 3427956840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1822002270 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7008167040 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5875188300 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 53218604400.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 52383682290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3161186880 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 106497624090 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 77662512480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12248740584255 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12559836053265 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.602662 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51435493097538 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5216830750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22612324000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 50999709861500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 202245988185 # Time in different power states +system.physmem_1.memoryStateTime::ACT 95365744212 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 233547114353 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -340,30 +337,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 290131106 # Number of BP lookups -system.cpu.branchPred.condPredicted 198353835 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13679752 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 208494226 # Number of BTB lookups -system.cpu.branchPred.BTBHits 130534623 # Number of BTB hits +system.cpu.branchPred.lookups 292003156 # Number of BP lookups +system.cpu.branchPred.condPredicted 199825428 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13707860 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 209782047 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131422635 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.608268 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37597374 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 402079 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 8125236 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6045082 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2080154 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 800698 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.647227 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37743675 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 403344 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 8164760 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6089475 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2075285 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 798713 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,88 +390,90 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 1423094 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1423094 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30587 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273540 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 668841 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 754253 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2502.822660 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 747574 99.11% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4739 0.63% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 871 0.12% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 433 0.06% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 327 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 64 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 235 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 754253 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 795185 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 776690 97.67% 97.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 15553 1.96% 99.63% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1840 0.23% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 320 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 153 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 44 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 795185 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1040609044948 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.747004 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.517062 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1036648437448 99.62% 99.62% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2501393000 0.24% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 710900000 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 286069000 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 201203000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 121106500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 48982500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 87667500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 3189000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 41500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::20-21 55500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1040609044948 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 273541 89.94% 89.94% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 30587 10.06% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 304128 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1423094 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 1433016 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1433016 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 32195 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277777 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 671696 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 761320 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2826.976830 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 21785.764506 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 754204 99.07% 99.07% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4652 0.61% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 981 0.13% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 445 0.06% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 347 0.05% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 34 0.00% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 244 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 36 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 13 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 353 0.05% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::917504-983039 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 761320 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 803371 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26077.733077 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21137.704877 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20668.738137 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-131071 799705 99.54% 99.54% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-262143 2825 0.35% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-393215 589 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-524287 118 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-655359 123 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-786431 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::786432-917503 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::1.17965e+06-1.31072e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 803371 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1075651264316 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.736998 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.521821 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1071482592816 99.61% 99.61% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2636080000 0.25% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 763976000 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 297116500 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 205516000 0.02% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 123566500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 47691000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 91565500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3134000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1075651264316 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 277778 89.61% 89.61% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 32195 10.39% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 309973 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1433016 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1423094 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304128 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1433016 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309973 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304128 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1727222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309973 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1742989 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 217549636 # DTB read hits -system.cpu.dtb.read_misses 1002675 # DTB read misses -system.cpu.dtb.write_hits 192429615 # DTB write hits -system.cpu.dtb.write_misses 420419 # DTB write misses +system.cpu.dtb.read_hits 218874380 # DTB read hits +system.cpu.dtb.read_misses 1009020 # DTB read misses +system.cpu.dtb.write_hits 193682033 # DTB write hits +system.cpu.dtb.write_misses 423996 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 84838 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 16158 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 89021 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 108 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 17262 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 86326 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 218552311 # DTB read accesses -system.cpu.dtb.write_accesses 192850034 # DTB write accesses +system.cpu.dtb.perms_faults 85593 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 219883400 # DTB read accesses +system.cpu.dtb.write_accesses 194106029 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 409979251 # DTB hits -system.cpu.dtb.misses 1423094 # DTB misses -system.cpu.dtb.accesses 411402345 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 412556413 # DTB hits +system.cpu.dtb.misses 1433016 # DTB misses +system.cpu.dtb.accesses 413989429 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -504,231 +503,234 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 177767 # Table walker walks requested -system.cpu.itb.walker.walksLong 177767 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1532 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 128663 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 19966 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 157801 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1393.783943 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9971.559116 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 155663 98.65% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 1042 0.66% 99.31% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 672 0.43% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 333 0.21% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 30 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 157801 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 150161 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28501.914612 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 144112 95.97% 95.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5152 3.43% 99.40% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 475 0.32% 99.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 255 0.17% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 99 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 55 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 150161 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 911756921068 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.951043 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.216068 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 44693483152 4.90% 4.90% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 867007398416 95.09% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 55571500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 466000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 911756921068 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 128663 98.82% 98.82% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1532 1.18% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 130195 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 178466 # Table walker walks requested +system.cpu.itb.walker.walksLong 178466 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1508 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 129505 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 20095 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 158371 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1754.443680 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 17709.281636 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-65535 157140 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-131071 1047 0.66% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-196607 42 0.03% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-327679 14 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-393215 7 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::524288-589823 40 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::589824-655359 48 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 158371 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 151108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29265.005824 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23190.077140 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 30431.733671 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 145001 95.96% 95.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 5046 3.34% 99.30% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 391 0.26% 99.56% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 366 0.24% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 100 0.07% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 51 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 85 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::720896-786431 24 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 151108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 912439402568 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.949255 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.219812 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 46367810152 5.08% 5.08% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 866006867916 94.91% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 63907500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 568000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 249000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 912439402568 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 129505 98.85% 98.85% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1508 1.15% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 131013 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177767 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 177767 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178466 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 178466 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130195 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 130195 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 307962 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 462600046 # ITB inst hits -system.cpu.itb.inst_misses 177767 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 131013 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 131013 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 309479 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 465485773 # ITB inst hits +system.cpu.itb.inst_misses 178466 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58185 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 62647 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 440221 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 443320 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 462777813 # ITB inst accesses -system.cpu.itb.hits 462600046 # DTB hits -system.cpu.itb.misses 177767 # DTB misses -system.cpu.itb.accesses 462777813 # DTB accesses -system.cpu.numPwrStateTransitions 34262 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 17131 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 2947433272.666569 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 58590018858.186401 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7811 45.60% 45.60% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9284 54.19% 99.79% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 465664239 # ITB inst accesses +system.cpu.itb.hits 465485773 # DTB hits +system.cpu.itb.misses 178466 # DTB misses +system.cpu.itb.accesses 465664239 # DTB accesses +system.cpu.numPwrStateTransitions 34324 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 17162 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2940404395.507225 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 58760863847.973442 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7839 45.68% 45.68% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.12% 99.80% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 17131 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1065535433949 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2131080190 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988780801904 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 17162 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1095477627305 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50463220235695 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2190964579 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 789533395 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1294232501 # Number of instructions fetch has processed -system.cpu.fetch.Branches 290131106 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174177079 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1253396684 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29442936 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4521296 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28032 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11449142 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1221670 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 685 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 462141962 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6901101 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 52491 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2074872372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.731015 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.142682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 794033282 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1302230220 # Number of instructions fetch has processed +system.cpu.fetch.Branches 292003156 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 175255785 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1304336456 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29502488 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4651258 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26755 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11711903 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1225327 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1089 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 465024484 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6899822 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 52313 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2130737314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.716190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.134027 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1354023092 65.26% 65.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 279633538 13.48% 78.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 86518146 4.17% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 354697596 17.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1403414987 65.87% 65.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 283475853 13.30% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 89003023 4.18% 83.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 354843451 16.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2074872372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136143 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.607313 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 615922756 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 835719938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 532432043 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80077312 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10720323 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41258933 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4059445 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1407827153 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 33008479 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10720323 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 679035070 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 79966926 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 552687037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 549603762 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 202859254 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1383638167 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 8109162 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7348509 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 966276 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1094350 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 119568064 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22725 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1333397174 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2200696007 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1641425227 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1433031 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1254726296 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78670875 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43643507 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39180007 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 166278031 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 222554034 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 196867138 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12635283 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11114743 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1330840515 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 43953891 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1360477402 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4212137 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 73710813 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41934009 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 368799 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2074872372 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.655692 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.916068 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2130737314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133276 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.594364 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 615599644 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 888388322 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542818505 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 73189293 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10741550 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41458105 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4067803 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1416661162 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 33069720 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10741550 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 678370602 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 94749069 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 569457122 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 557397759 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 220021212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1392357267 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 8139910 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7467928 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 990269 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1135391 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 140197147 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22858 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1342242693 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2216016664 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1651872272 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1433815 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1263306379 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78936311 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44081382 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39609601 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160762582 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 223936207 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 198122558 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12861166 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11120462 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1339067750 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44403277 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1369076757 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4228585 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 73934913 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42101353 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 368543 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2130737314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.642537 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.913709 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1226409345 59.11% 59.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 451307165 21.75% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 291780533 14.06% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 95920964 4.62% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9425546 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 28819 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1278640571 60.01% 60.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 452467629 21.24% 81.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 292658965 13.74% 94.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96618652 4.53% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10322243 0.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29254 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2074872372 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2130737314 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 73561900 34.17% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90692 0.04% 34.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26794 0.01% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 484 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 57931960 26.91% 61.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83660297 38.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 74049078 33.84% 33.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90108 0.04% 33.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26756 0.01% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 482 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 59033401 26.97% 60.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 85651168 39.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 939889673 69.09% 69.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2936613 0.22% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 130878 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 55 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 945875031 69.09% 69.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2941932 0.21% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 129428 0.01% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued @@ -751,100 +753,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 112363 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 112221 0.01% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 222587367 16.36% 85.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194820033 14.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 223931934 16.36% 85.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 196085738 14.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1360477402 # Type of FU issued -system.cpu.iq.rate 0.638398 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215272127 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.158233 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5012901497 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1447776434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1338315649 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2409942 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 914537 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 885572 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1574233532 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1515940 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5717597 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1369076757 # Type of FU issued +system.cpu.iq.rate 0.624874 # Inst issue rate +system.cpu.iq.fu_busy_cnt 218850993 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.159853 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5089559021 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1456673430 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1346855595 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2411384 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 915419 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 886368 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1586411072 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1516623 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5720273 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17343387 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24124 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 187368 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7978529 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17413416 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22608 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 184689 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8002869 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3596780 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1680866 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3613750 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2051788 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10720323 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12040487 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4569260 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1375079942 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10741550 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13180703 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5272349 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1383757283 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 222554034 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 196867138 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 38644291 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 177419 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4207009 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 187368 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4048268 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6103351 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10151619 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1346834094 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 217554512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12249639 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 223936207 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 198122558 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39070088 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 183909 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4898355 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 184689 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4057329 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6115164 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10172493 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1355379185 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 218880930 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12294353 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 285536 # number of nop insts executed -system.cpu.iew.exec_refs 409993947 # number of memory reference insts executed -system.cpu.iew.exec_branches 255680172 # Number of branches executed -system.cpu.iew.exec_stores 192439435 # Number of stores executed -system.cpu.iew.exec_rate 0.631996 # Inst execution rate -system.cpu.iew.wb_sent 1340240150 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1339201221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 574929948 # num instructions producing a value -system.cpu.iew.wb_consumers 943031378 # num instructions consuming a value -system.cpu.iew.wb_rate 0.628414 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.609662 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 62850702 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 43585092 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9678607 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2060674246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.631387 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.270689 # Number of insts commited each cycle +system.cpu.iew.exec_nop 286256 # number of nop insts executed +system.cpu.iew.exec_refs 412572980 # number of memory reference insts executed +system.cpu.iew.exec_branches 257403074 # Number of branches executed +system.cpu.iew.exec_stores 193692050 # Number of stores executed +system.cpu.iew.exec_rate 0.618622 # Inst execution rate +system.cpu.iew.wb_sent 1348783541 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1347741963 # cumulative count of insts written-back +system.cpu.iew.wb_producers 576070929 # num instructions producing a value +system.cpu.iew.wb_consumers 948341211 # num instructions consuming a value +system.cpu.iew.wb_rate 0.615136 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.607451 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 63015193 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 44034734 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9698166 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2116507295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.618725 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263721 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1383412740 67.13% 67.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 394991247 19.17% 86.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150433823 7.30% 93.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44582057 2.16% 95.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36156812 1.75% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18175173 0.88% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10964042 0.53% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5475656 0.27% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16482696 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1435626131 67.83% 67.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 397528537 18.78% 86.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150810671 7.13% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44606790 2.11% 95.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36101901 1.71% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18021060 0.85% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 11293216 0.53% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5858251 0.28% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16660738 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2060674246 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1106923026 # Number of instructions committed -system.cpu.commit.committedOps 1301083589 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2116507295 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1114173091 # Number of instructions committed +system.cpu.commit.committedOps 1309536110 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 394099255 # Number of memory references committed -system.cpu.commit.loads 205210646 # Number of loads committed -system.cpu.commit.membars 9122435 # Number of memory barriers committed -system.cpu.commit.branches 247396089 # Number of branches committed -system.cpu.commit.fp_insts 873905 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1189215854 # Number of committed integer instructions. -system.cpu.commit.function_calls 30973786 # Number of function calls committed. +system.cpu.commit.refs 396642479 # Number of memory references committed +system.cpu.commit.loads 206522790 # Number of loads committed +system.cpu.commit.membars 9192719 # Number of memory barriers committed +system.cpu.commit.branches 249090207 # Number of branches committed +system.cpu.commit.fp_insts 874521 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1196753296 # Number of committed integer instructions. +system.cpu.commit.function_calls 31104441 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 904226715 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2546778 0.20% 69.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 104952 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 910131481 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2552727 0.19% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 103687 0.01% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction @@ -867,577 +869,581 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105847 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105694 0.01% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 205210646 15.77% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 188888609 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 206522790 15.77% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 190119689 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1301083589 # Class of committed instruction -system.cpu.commit.bw_lim_events 16482696 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3398675710 # The number of ROB reads -system.cpu.rob.rob_writes 2741957858 # The number of ROB writes -system.cpu.timesIdled 9058128 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 56207818 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100984949503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1106923026 # Number of Instructions Simulated -system.cpu.committedOps 1301083589 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.925229 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.925229 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519419 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519419 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1599627417 # number of integer regfile reads -system.cpu.int_regfile_writes 942915680 # number of integer regfile writes -system.cpu.fp_regfile_reads 1421408 # number of floating regfile reads -system.cpu.fp_regfile_writes 762380 # number of floating regfile writes -system.cpu.cc_regfile_reads 312164706 # number of cc regfile reads -system.cpu.cc_regfile_writes 313034766 # number of cc regfile writes -system.cpu.misc_regfile_reads 3414318389 # number of misc regfile reads -system.cpu.misc_regfile_writes 44468731 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 13662519 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983620 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 361203380 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13663031 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.436548 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1659288500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983620 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 1309536110 # Class of committed instruction +system.cpu.commit.bw_lim_events 16660738 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3462896243 # The number of ROB reads +system.cpu.rob.rob_writes 2759222856 # The number of ROB writes +system.cpu.timesIdled 9103079 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60227265 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100926431181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1114173091 # Number of Instructions Simulated +system.cpu.committedOps 1309536110 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.966449 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.966449 # CPI: Total CPI of All Threads +system.cpu.ipc 0.508531 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.508531 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1609897597 # number of integer regfile reads +system.cpu.int_regfile_writes 948614350 # number of integer regfile writes +system.cpu.fp_regfile_reads 1422281 # number of floating regfile reads +system.cpu.fp_regfile_writes 763660 # number of floating regfile writes +system.cpu.cc_regfile_reads 314738541 # number of cc regfile reads +system.cpu.cc_regfile_writes 315610902 # number of cc regfile writes +system.cpu.misc_regfile_reads 3478507383 # number of misc regfile reads +system.cpu.misc_regfile_writes 44953668 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 13773933 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.982218 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 363424605 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13774445 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.383974 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.982218 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1599492126 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1599492126 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 186946586 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 186946586 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 163344159 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 163344159 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 463383 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 463383 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333988 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333988 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4793284 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4793284 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5278947 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5278947 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 350624733 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 350624733 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 351088116 # number of overall hits -system.cpu.dcache.overall_hits::total 351088116 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12788061 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12788061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18648516 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18648516 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2041461 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2041461 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1270506 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1270506 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 548369 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 548369 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 32707083 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 32707083 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 34748544 # number of overall misses -system.cpu.dcache.overall_misses::total 34748544 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 205827865000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 205827865000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1003464059741 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1003464059741 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 29968640002 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 29968640002 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8933513500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 8933513500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 300500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 300500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239260564743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239260564743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239260564743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239260564743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 199734647 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 199734647 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 181992675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 181992675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2504844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2504844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5341653 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5341653 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5278956 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5278956 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 383331816 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 383331816 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385836660 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385836660 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.064025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102468 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.102468 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.815005 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.815005 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791842 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791842 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102659 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102659 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.085323 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.085323 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.090060 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.090060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37889.669487 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35663.668807 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24419954 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 1609792532 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1609792532 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 188105539 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 188105539 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164299305 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164299305 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 464298 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 464298 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 335039 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 335039 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4843113 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4843113 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5333928 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5333928 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 352739883 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 352739883 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 353204181 # number of overall hits +system.cpu.dcache.overall_hits::total 353204181 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12867394 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12867394 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18868212 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18868212 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2064415 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2064415 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1270711 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1270711 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 552556 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 552556 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 33006317 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 33006317 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 35070732 # number of overall misses +system.cpu.dcache.overall_misses::total 35070732 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 226129752000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 226129752000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113756894884 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1113756894884 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30103485720 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 30103485720 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9429427500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 9429427500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 286500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 286500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1369990132604 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1369990132604 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1369990132604 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1369990132604 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 200972933 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 200972933 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 183167517 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 183167517 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2528713 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2528713 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605750 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1605750 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5395669 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5395669 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5333936 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5333936 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 385746200 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385746200 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 388274913 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 388274913 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.064026 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103011 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.103011 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816390 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.816390 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791350 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791350 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102407 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102407 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.085565 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.085565 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.090324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.090324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17573.857768 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17573.857768 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59028.216075 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59028.216075 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23690.269243 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23690.269243 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.107428 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.107428 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35812.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35812.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41506.907075 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41506.907075 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39063.630967 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39063.630967 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29294390 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2093623 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2113869 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.663969 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.858186 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 10319802 # number of writebacks -system.cpu.dcache.writebacks::total 10319802 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5736139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5736139 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15576096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15576096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6849 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 6849 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265006 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 265006 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21319084 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21319084 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21319084 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21319084 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7051922 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7051922 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3072420 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3072420 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2034687 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2034687 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263657 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1263657 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283363 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 283363 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 11387999 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 11387999 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 13422686 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 13422686 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 10422476 # number of writebacks +system.cpu.dcache.writebacks::total 10422476 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5755479 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5755479 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15769683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15769683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6881 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6881 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 266620 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 266620 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21532043 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21532043 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21532043 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21532043 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111915 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7111915 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3098529 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3098529 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2057605 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2057605 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263830 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1263830 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 285936 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 285936 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 11474274 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 11474274 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 13531879 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 13531879 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32559356000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32559356000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28426038502 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28426038502 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4117736500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4117736500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 291500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 291500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 286407793715 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 318967149715 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225596500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225596500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225596500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225596500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035306 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035306 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.812301 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.812301 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787574 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787574 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053048 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053048 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029708 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029708 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16891256 # number of replacements -system.cpu.icache.tags.tagsinuse 511.956016 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 444441322 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16891768 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.311119 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13164566500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.956016 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999914 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 120215948500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 120215948500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164231979720 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 164231979720 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 35080858000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 35080858000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28539216720 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28539216720 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4259524000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4259524000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 278500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 278500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312987144940 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 312987144940 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 348068002940 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 348068002940 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225685500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225685500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225685500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225685500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035387 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035387 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016916 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016916 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813697 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813697 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787065 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787065 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052994 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052994 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029746 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029746 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034851 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034851 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16903.456875 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16903.456875 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53003.208852 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53003.208852 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17049.364674 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17049.364674 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22581.531314 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22581.531314 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14896.774103 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14896.774103 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34812.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34812.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27277.293966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27277.293966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25722.074735 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25722.074735 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184782.307373 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184782.307373 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92376.073893 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92376.073893 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16962264 # number of replacements +system.cpu.icache.tags.tagsinuse 511.953467 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 447249112 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16962776 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.366505 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13767456500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.953467 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 479012658 # Number of tag accesses -system.cpu.icache.tags.data_accesses 479012658 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 444441322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 444441322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 444441322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 444441322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 444441322 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 234300237389 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 462120664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 462120664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 462120664 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 462120664 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 462120664 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 462120664 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038257 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.038257 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.038257 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.038257 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.038257 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.038257 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13252.769101 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13252.769101 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13252.769101 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13252.769101 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 16371 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 481966186 # Number of tag accesses +system.cpu.icache.tags.data_accesses 481966186 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 447249112 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 447249112 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 447249112 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 447249112 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 447249112 # number of overall hits +system.cpu.icache.overall_hits::total 447249112 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17754074 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17754074 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17754074 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17754074 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17754074 # number of overall misses +system.cpu.icache.overall_misses::total 17754074 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 238230546873 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 238230546873 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 238230546873 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 238230546873 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 238230546873 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 238230546873 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465003186 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465003186 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465003186 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465003186 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465003186 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465003186 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038181 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.038181 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.038181 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.038181 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.038181 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.038181 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13418.359463 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13418.359463 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13418.359463 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13418.359463 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 22063 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1212 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1484 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 13.507426 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 14.867251 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16891256 # number of writebacks -system.cpu.icache.writebacks::total 16891256 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 787348 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 787348 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 787348 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 787348 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 787348 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 787348 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16891994 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16891994 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16891994 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16891994 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16891994 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16891994 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 16962264 # number of writebacks +system.cpu.icache.writebacks::total 16962264 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791074 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 791074 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 791074 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 791074 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 791074 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 791074 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963000 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16963000 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16963000 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16963000 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16963000 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16963000 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210691534398 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 210691534398 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210691534398 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 210691534398 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210691534398 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 210691534398 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1610722500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1610722500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1610722500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1610722500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036553 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.036553 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.036553 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12472.863440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12472.863440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2372905 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65457.290128 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 58959202 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2435994 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.203345 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2520974000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9397.889077 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 196.572797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 228.214718 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6628.882550 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.143400 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.002999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.003482 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.747768 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998799 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62867 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55850 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959274 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 505094110 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 505094110 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1274032 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 302472 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7331831049 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144970240788 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1344547500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804287500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7148835000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1344547500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804287500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7148835000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012019 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 891304000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2269682000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76822000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76822000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 182500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 182500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127318887048 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127318887048 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9809383542 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9809383542 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 45465885070 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 45465885070 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12316948002 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12316948002 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 891304000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9809383542 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172784772118 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 184863837660 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 891304000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9809383542 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172784772118 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 184863837660 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1486487500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804372500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290860000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1486487500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804372500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290860000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012171 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094837 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094837 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.444444 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437822 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437822 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005741 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045756 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045756 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.466977 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.466977 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060787 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060787 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 62084255 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 31529230 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3455 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.092878 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.092878 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437237 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437237 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005743 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.047479 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.047479 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.471162 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.471162 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061372 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061372 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115042.931725 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19076.732059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19076.732059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45625 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45625 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94799.663632 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94799.663632 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100703.051484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100703.051484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101451.929412 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101451.929412 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20684.448732 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20684.448732 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.469429 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.842324 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.675421 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.038077 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 62444778 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31707340 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2080 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2080 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 2242102 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28488845 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 2265526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28668320 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 12415627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16891256 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3619797 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43003 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3045422 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3045422 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16891994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9356331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1295806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263657 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50717623 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41210208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 777423 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3005376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 95710630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2162455328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1454268658 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2489712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10275752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3629489450 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2999840 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 138927432 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 35281285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026592 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.160887 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 12556358 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16962264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3627230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43361 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3071629 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3071629 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16963000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1296315 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1263830 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50930633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41545171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 782892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3048631 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 96307327 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171543584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467959922 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2514816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10453048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3652471370 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3035082 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 141349672 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 35524572 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026277 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.159958 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 34343098 97.34% 97.34% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 938187 2.66% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 34591090 97.37% 97.37% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 933482 2.63% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35281285 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 58941748976 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35524572 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 59309730487 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1470395 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1500879 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25369728010 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25476019939 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19308156079 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19475244130 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 466604190 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 468898263 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1721722349 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1742663628 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40300 # Transaction distribution -system.iobus.trans_dist::ReadResp 40300 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40311 # Transaction distribution +system.iobus.trans_dist::ReadResp 40311 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1612,11 +1618,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353742 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1631,16 +1637,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41887500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41893500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 344000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1654,79 +1660,79 @@ system.iobus.reqLayer14.occupancy 9500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25106500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25183500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36499000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568968673 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569168088 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147718000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115465 # number of replacements -system.iocache.tags.tagsinuse 10.450543 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115471 # number of replacements +system.iocache.tags.tagsinuse 10.450359 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13091229344000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.877255 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.573288 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.367328 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.285830 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653159 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13091904207000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.527977 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.922382 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220499 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432649 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039668 # Number of tag accesses -system.iocache.tags.data_accesses 1039668 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039767 # Number of tag accesses +system.iocache.tags.data_accesses 1039767 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115479 # number of demand (read+write) misses -system.iocache.demand_misses::total 115519 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115490 # number of demand (read+write) misses +system.iocache.demand_misses::total 115530 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115479 # number of overall misses -system.iocache.overall_misses::total 115519 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1629675592 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1634761592 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115490 # number of overall misses +system.iocache.overall_misses::total 115530 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1926111562 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1931197062 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12811525081 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12811525081 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14441200673 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14446637673 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14441200673 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14446637673 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13315765026 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13315765026 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15241876588 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15247313088 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15241876588 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15247313088 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115479 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115519 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115490 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115530 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115479 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115519 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115490 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115530 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1740,53 +1746,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184677.089019 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218231.538862 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217894.286585 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125058.541651 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125058.541651 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32070 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124838.418079 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 124838.418079 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131977.088964 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131977.088964 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 47583 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.390922 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.760266 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115479 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115519 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115490 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115530 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115479 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115519 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188925592 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1192161592 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115490 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115530 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1484811562 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1488047062 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7471582182 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7471582182 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8660507774 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8663944774 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8660507774 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8663944774 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7975666597 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7975666597 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9460478159 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9463914659 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9460478159 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9463914659 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1800,95 +1806,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168231.538862 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 167894.286585 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 5074419 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2524015 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74773.743690 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74773.743690 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 5147706 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2561464 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54986 # Transaction distribution -system.membus.trans_dist::ReadResp 608005 # Transaction distribution +system.membus.trans_dist::ReadResp 629139 # Transaction distribution system.membus.trans_dist::WriteReq 33703 # Transaction distribution system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::WritebackDirty 2202455 # Transaction distribution -system.membus.trans_dist::CleanEvict 284620 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4643 # Transaction distribution +system.membus.trans_dist::WritebackDirty 2240512 # Transaction distribution +system.membus.trans_dist::CleanEvict 283345 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 1332798 # Transaction distribution -system.membus.trans_dist::ReadExResp 1332798 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 553019 # Transaction distribution -system.membus.trans_dist::InvalidateReq 696755 # Transaction distribution +system.membus.trans_dist::ReadExReq 1342476 # Transaction distribution +system.membus.trans_dist::ReadExResp 1342476 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 574153 # Transaction distribution +system.membus.trans_dist::InvalidateReq 702122 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6767333 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6896995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237693 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237693 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7134688 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6871030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7000692 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7238382 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254577484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254747538 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 262001234 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2809 # Total snoops (count) -system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2675908 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013150 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.113918 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258984332 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 259154386 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7252416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 266406802 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2841 # Total snoops (count) +system.membus.snoopTraffic 181312 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2712040 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013104 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.113719 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2640719 98.68% 98.68% # Request fanout histogram -system.membus.snoop_fanout::1 35189 1.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2676502 98.69% 98.69% # Request fanout histogram +system.membus.snoop_fanout::1 35538 1.31% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2675908 # Request fanout histogram -system.membus.reqLayer0.occupancy 103923000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2712040 # Request fanout histogram +system.membus.reqLayer0.occupancy 104012000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5620000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5608000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14223305475 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14521699612 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10050154677 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10216122095 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44814659 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44869281 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1931,30 +1937,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17131 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 17162 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal index 3c0eb417b..b157c1f08 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal @@ -31,136 +31,136 @@ [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
-[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000021] Console: colour dummy device 80x25
-[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000025] pid_max: default: 32768 minimum: 301
-[ 0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000147] hw perfevents: no hardware support available
-[ 1.060066] CPU1: failed to come online
-[ 2.080127] CPU2: failed to come online
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000019] Console: colour dummy device 80x25
+[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000022] pid_max: default: 32768 minimum: 301
+[ 0.000032] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000120] hw perfevents: no hardware support available
+[ 1.060065] CPU1: failed to come online
+[ 2.080126] CPU2: failed to come online
[ 3.100188] CPU3: failed to come online
-[ 3.100191] Brought up 1 CPUs
-[ 3.100192] SMP: Total of 1 processors activated.
-[ 3.100247] devtmpfs: initialized
-[ 3.100685] atomic64_test: passed
-[ 3.100727] regulator-dummy: no parameters
-[ 3.101141] NET: Registered protocol family 16
-[ 3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.101638] Serial: AMBA PL011 UART driver
-[ 3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.102416] console [ttyAMA0] enabled
-[ 3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130494] 3V3: 3300 mV
-[ 3.130534] vgaarb: loaded
-[ 3.130580] SCSI subsystem initialized
-[ 3.130617] libata version 3.00 loaded.
-[ 3.130659] usbcore: registered new interface driver usbfs
-[ 3.130676] usbcore: registered new interface driver hub
-[ 3.130707] usbcore: registered new device driver usb
-[ 3.130732] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.130759] PTP clock support registered
-[ 3.130873] Switched to clocksource arch_sys_counter
-[ 3.131846] NET: Registered protocol family 2
-[ 3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.131960] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.131975] TCP: reno registered
-[ 3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132036] NET: Registered protocol family 1
-[ 3.132085] RPC: Registered named UNIX socket transport module.
-[ 3.132095] RPC: Registered udp transport module.
-[ 3.132103] RPC: Registered tcp transport module.
-[ 3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.132123] PCI: CLS 0 bytes, default 64
-[ 3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.133901] fuse init (API version 7.23)
-[ 3.133978] msgmni has been set to 469
-[ 3.136097] io scheduler noop registered
-[ 3.136147] io scheduler cfq registered (default)
-[ 3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.136528] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.136552] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.136562] pci_bus 0000:00: scanning bus
-[ 3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.136647] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.136658] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.136669] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.136679] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.136690] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136734] pci_bus 0000:00: fixups for bus
-[ 3.136742] pci_bus 0000:00: bus scan returning with max=00
-[ 3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.136774] pci 0000:00:00.0: fixup irq: got 33
-[ 3.136782] pci 0000:00:00.0: assigning IRQ 33
-[ 3.136793] pci 0000:00:01.0: fixup irq: got 34
-[ 3.136801] pci 0000:00:01.0: assigning IRQ 34
-[ 3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.136851] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.136862] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.136874] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.136885] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.136896] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.137572] ata_piix 0000:00:01.0: version 2.13
-[ 3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.137604] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.137866] scsi0 : ata_piix
-[ 3.137956] scsi1 : ata_piix
-[ 3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.138131] e1000 0000:00:00.0: enabling bus mastering
-[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.290909] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.290935] ata1.00: configured for UDMA/33
-[ 3.290984] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.291146] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.291287] sda: sda1
-[ 3.291392] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.411240] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.411304] usbcore: registered new interface driver usb-storage
-[ 3.411354] mousedev: PS/2 mouse device common for all mice
-[ 3.411491] usbcore: registered new interface driver usbhid
-[ 3.411501] usbhid: USB HID core driver
-[ 3.411531] TCP: cubic registered
-[ 3.411538] NET: Registered protocol family 17
- -[ 3.411900] devtmpfs: mounted
-[ 3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 3.100190] Brought up 1 CPUs
+[ 3.100191] SMP: Total of 1 processors activated.
+[ 3.100238] devtmpfs: initialized
+[ 3.100663] atomic64_test: passed
+[ 3.100701] regulator-dummy: no parameters
+[ 3.101063] NET: Registered protocol family 16
+[ 3.101179] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.101187] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.101343] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.101347] Serial: AMBA PL011 UART driver
+[ 3.101513] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101543] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.102115] console [ttyAMA0] enabled
+[ 3.102184] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.102216] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.102248] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.102278] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130478] 3V3: 3300 mV
+[ 3.130515] vgaarb: loaded
+[ 3.130558] SCSI subsystem initialized
+[ 3.130595] libata version 3.00 loaded.
+[ 3.130635] usbcore: registered new interface driver usbfs
+[ 3.130652] usbcore: registered new interface driver hub
+[ 3.130683] usbcore: registered new device driver usb
+[ 3.130706] pps_core: LinuxPPS API ver. 1 registered
+[ 3.130716] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130734] PTP clock support registered
+[ 3.130840] Switched to clocksource arch_sys_counter
+[ 3.131799] NET: Registered protocol family 2
+[ 3.131866] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131883] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131902] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131917] TCP: reno registered
+[ 3.131924] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131937] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131972] NET: Registered protocol family 1
+[ 3.132017] RPC: Registered named UNIX socket transport module.
+[ 3.132028] RPC: Registered udp transport module.
+[ 3.132036] RPC: Registered tcp transport module.
+[ 3.132044] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.132057] PCI: CLS 0 bytes, default 64
+[ 3.132193] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.132284] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.133790] fuse init (API version 7.23)
+[ 3.133866] msgmni has been set to 469
+[ 3.135967] io scheduler noop registered
+[ 3.136016] io scheduler cfq registered (default)
+[ 3.136336] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.136349] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.136360] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.136373] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.136383] pci_bus 0000:00: scanning bus
+[ 3.136393] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.136406] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.136420] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136454] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.136466] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.136477] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.136488] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.136499] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.136510] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.136521] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136554] pci_bus 0000:00: fixups for bus
+[ 3.136562] pci_bus 0000:00: bus scan returning with max=00
+[ 3.136574] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.136592] pci 0000:00:00.0: fixup irq: got 33
+[ 3.136601] pci 0000:00:00.0: assigning IRQ 33
+[ 3.136611] pci 0000:00:01.0: fixup irq: got 34
+[ 3.136620] pci 0000:00:01.0: assigning IRQ 34
+[ 3.136631] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.136644] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.136657] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.136670] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.136682] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.136693] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.136705] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.136716] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.137147] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.137373] ata_piix 0000:00:01.0: version 2.13
+[ 3.137384] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.137403] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.137653] scsi0 : ata_piix
+[ 3.137740] scsi1 : ata_piix
+[ 3.137768] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.137780] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.137872] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.137884] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.137899] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.137911] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290863] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290873] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290899] ata1.00: configured for UDMA/33
+[ 3.290941] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.291042] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.291065] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.291102] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.291112] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.291131] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.291239] sda: sda1
+[ 3.291342] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.411129] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.411142] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.411163] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.411173] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.411193] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.411205] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.411268] usbcore: registered new interface driver usb-storage
+[ 3.411318] mousedev: PS/2 mouse device common for all mice
+[ 3.411454] usbcore: registered new interface driver usbhid
+[ 3.411464] usbhid: USB HID core driver
+[ 3.411492] TCP: cubic registered
+[ 3.411499] NET: Registered protocol family 17
+ +[ 3.411840] devtmpfs: mounted
+[ 3.411860] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.450359] udevd[607]: starting version 182
+[ 3.450256] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.543431] random: dd urandom read with 19 bits of entropy available
+[ 3.603394] random: dd urandom read with 21 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -168,8 +168,8 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
-Configuring network interfaces... [ 3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
-udhcpc (v1.21.1) started
+Configuring network interfaces... udhcpc (v1.21.1) started
+[ 3.741068] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini index 2a00a6a90..9e59e49a8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -153,7 +153,7 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -250,7 +250,7 @@ port=system.cpu0.toL2Bus.slave[3] [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -310,7 +310,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -382,7 +382,7 @@ port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -531,7 +531,7 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -628,7 +628,7 @@ port=system.cpu1.toL2Bus.slave[3] [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -688,7 +688,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -760,7 +760,7 @@ port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -907,7 +907,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -953,7 +953,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1051,27 +1051,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1091,6 +1091,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1100,7 +1101,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1122,9 +1123,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1477,7 +1478,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1790,10 +1791,11 @@ pio=system.iobus.master[21] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain -conf_table_reported=true +conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1801,7 +1803,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2032,6 +2034,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2039,7 +2042,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout index c648cad5f..7bd8ed2ad 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:41:50 -gem5 executing on e108600-lin, pid 23131 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:42:59 +gem5 executing on e108600-lin, pid 17314 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual Selected 64-bit ARM architecture, updating default disk image... @@ -15,4 +15,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47403574916500 because m5_exit instruction encountered +Exiting @ tick 47405012960500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index c73396a86..68cea9e8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.374315 # Number of seconds simulated -sim_ticks 47374315410500 # Number of ticks simulated -final_tick 47374315410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.405013 # Number of seconds simulated +sim_ticks 47405012960500 # Number of ticks simulated +final_tick 47405012960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 573964 # Simulator instruction rate (inst/s) -host_op_rate 675116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30496109280 # Simulator tick rate (ticks/s) -host_mem_usage 762100 # Number of bytes of host memory used -host_seconds 1553.45 # Real time elapsed on the host -sim_insts 891626325 # Number of instructions simulated -sim_ops 1048762579 # Number of ops (including micro ops) simulated +host_inst_rate 480061 # Simulator instruction rate (inst/s) +host_op_rate 564722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25874318289 # Simulator tick rate (ticks/s) +host_mem_usage 758156 # Number of bytes of host memory used +host_seconds 1832.13 # Real time elapsed on the host +sim_insts 879531552 # Number of instructions simulated +sim_ops 1034641707 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 107264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 103104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3762996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12951880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13484096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 112000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 117056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2426936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10199632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12856576 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 431488 # Number of bytes read from this memory -system.physmem.bytes_read::total 56553028 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3762996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2426936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6189932 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74832448 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 107584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 111616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3269620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13856200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15427200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 122176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 126272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2852024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9626320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10834112 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 432576 # Number of bytes read from this memory +system.physmem.bytes_read::total 56765700 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3269620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2852024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6121644 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74832256 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74853032 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1676 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1611 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 99204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 202386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 210689 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1829 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 38009 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 159382 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 200884 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6742 # Number of read requests responded to by this memory -system.physmem.num_reads::total 924162 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1169257 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74852840 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1681 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 91495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 216516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 241050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1973 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 150424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 169283 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6759 # Number of read requests responded to by this memory +system.physmem.num_reads::total 927485 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1169254 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1171831 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 79431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 273395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 284629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 215299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 271383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1193749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 79431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51229 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 130660 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1579600 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1171828 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 68972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 292294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 325434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 60163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 203065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 228544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1197462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 68972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 60163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 129135 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1578573 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1580034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1579600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 79431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 273829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 284629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51229 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 215299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 271383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2773783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 924162 # Number of read requests accepted -system.physmem.writeReqs 1171831 # Number of write requests accepted -system.physmem.readBursts 924162 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1171831 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59123712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22656 # Total number of bytes read from write queue -system.physmem.bytesWritten 74852544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56553028 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 74853032 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 354 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1579007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1578573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 68972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 292728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 325434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 60163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 203066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 228544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2776469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 927485 # Number of read requests accepted +system.physmem.writeReqs 1171828 # Number of write requests accepted +system.physmem.readBursts 927485 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1171828 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59337472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21568 # Total number of bytes read from write queue +system.physmem.bytesWritten 74850880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56765700 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74852840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 337 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 54791 # Per bank write bursts -system.physmem.perBankRdBursts::1 60963 # Per bank write bursts -system.physmem.perBankRdBursts::2 51680 # Per bank write bursts -system.physmem.perBankRdBursts::3 61600 # Per bank write bursts -system.physmem.perBankRdBursts::4 56399 # Per bank write bursts -system.physmem.perBankRdBursts::5 67623 # Per bank write bursts -system.physmem.perBankRdBursts::6 62592 # Per bank write bursts -system.physmem.perBankRdBursts::7 58195 # Per bank write bursts -system.physmem.perBankRdBursts::8 51047 # Per bank write bursts -system.physmem.perBankRdBursts::9 95684 # Per bank write bursts -system.physmem.perBankRdBursts::10 47816 # Per bank write bursts -system.physmem.perBankRdBursts::11 53141 # Per bank write bursts -system.physmem.perBankRdBursts::12 48535 # Per bank write bursts -system.physmem.perBankRdBursts::13 54663 # Per bank write bursts -system.physmem.perBankRdBursts::14 49130 # Per bank write bursts -system.physmem.perBankRdBursts::15 49949 # Per bank write bursts -system.physmem.perBankWrBursts::0 71660 # Per bank write bursts -system.physmem.perBankWrBursts::1 78743 # Per bank write bursts -system.physmem.perBankWrBursts::2 71851 # Per bank write bursts -system.physmem.perBankWrBursts::3 78616 # Per bank write bursts -system.physmem.perBankWrBursts::4 73485 # Per bank write bursts -system.physmem.perBankWrBursts::5 81529 # Per bank write bursts -system.physmem.perBankWrBursts::6 75635 # Per bank write bursts -system.physmem.perBankWrBursts::7 74455 # Per bank write bursts -system.physmem.perBankWrBursts::8 70456 # Per bank write bursts -system.physmem.perBankWrBursts::9 72917 # Per bank write bursts -system.physmem.perBankWrBursts::10 67611 # Per bank write bursts -system.physmem.perBankWrBursts::11 70918 # Per bank write bursts -system.physmem.perBankWrBursts::12 67621 # Per bank write bursts -system.physmem.perBankWrBursts::13 71486 # Per bank write bursts -system.physmem.perBankWrBursts::14 70570 # Per bank write bursts -system.physmem.perBankWrBursts::15 72018 # Per bank write bursts +system.physmem.perBankRdBursts::0 53188 # Per bank write bursts +system.physmem.perBankRdBursts::1 58555 # Per bank write bursts +system.physmem.perBankRdBursts::2 49548 # Per bank write bursts +system.physmem.perBankRdBursts::3 58849 # Per bank write bursts +system.physmem.perBankRdBursts::4 61060 # Per bank write bursts +system.physmem.perBankRdBursts::5 64213 # Per bank write bursts +system.physmem.perBankRdBursts::6 58593 # Per bank write bursts +system.physmem.perBankRdBursts::7 62574 # Per bank write bursts +system.physmem.perBankRdBursts::8 53530 # Per bank write bursts +system.physmem.perBankRdBursts::9 96457 # Per bank write bursts +system.physmem.perBankRdBursts::10 50033 # Per bank write bursts +system.physmem.perBankRdBursts::11 57571 # Per bank write bursts +system.physmem.perBankRdBursts::12 47029 # Per bank write bursts +system.physmem.perBankRdBursts::13 51615 # Per bank write bursts +system.physmem.perBankRdBursts::14 49510 # Per bank write bursts +system.physmem.perBankRdBursts::15 54823 # Per bank write bursts +system.physmem.perBankWrBursts::0 69378 # Per bank write bursts +system.physmem.perBankWrBursts::1 74382 # Per bank write bursts +system.physmem.perBankWrBursts::2 69427 # Per bank write bursts +system.physmem.perBankWrBursts::3 75087 # Per bank write bursts +system.physmem.perBankWrBursts::4 76532 # Per bank write bursts +system.physmem.perBankWrBursts::5 78990 # Per bank write bursts +system.physmem.perBankWrBursts::6 75385 # Per bank write bursts +system.physmem.perBankWrBursts::7 77589 # Per bank write bursts +system.physmem.perBankWrBursts::8 70916 # Per bank write bursts +system.physmem.perBankWrBursts::9 76207 # Per bank write bursts +system.physmem.perBankWrBursts::10 70858 # Per bank write bursts +system.physmem.perBankWrBursts::11 75862 # Per bank write bursts +system.physmem.perBankWrBursts::12 66596 # Per bank write bursts +system.physmem.perBankWrBursts::13 70423 # Per bank write bursts +system.physmem.perBankWrBursts::14 68869 # Per bank write bursts +system.physmem.perBankWrBursts::15 73044 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 85 # Number of times write queue was full causing retry -system.physmem.totGap 47374312061000 # Total gap between requests +system.physmem.numWrRetry 516 # Number of times write queue was full causing retry +system.physmem.totGap 47405009605000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 880937 # Read request sizes (log2) +system.physmem.readPktSize::6 884260 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1169257 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 656925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 77551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1169254 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 645919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 88942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 21962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,173 +189,184 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 71567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 72784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 77929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 71715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 64345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 259 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 927168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 144.500035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.409552 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 191.008164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 615708 66.41% 66.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189300 20.42% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44500 4.80% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20695 2.23% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14869 1.60% 95.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9173 0.99% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6380 0.69% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5518 0.60% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21025 2.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 927168 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60983 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.148533 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.608088 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60979 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 28620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 36458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 65994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 73600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 75174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 70698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 71278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 75021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 68576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1170 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 929017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 144.440810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.331936 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.352121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 617371 66.45% 66.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189527 20.40% 86.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44674 4.81% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20356 2.19% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14838 1.60% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9142 0.98% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6196 0.67% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5371 0.58% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21542 2.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 929017 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60832 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.240992 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.606668 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60830 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60983 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60983 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.178640 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.436589 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.785486 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49393 80.99% 80.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4571 7.50% 88.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2800 4.59% 93.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1776 2.91% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1006 1.65% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 308 0.51% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 149 0.24% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 125 0.20% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 64 0.10% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 38 0.06% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 29 0.05% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 41 0.07% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 435 0.71% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 54 0.09% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 52 0.09% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 33 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60832 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60832 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.225819 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.418138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.471341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49295 81.03% 81.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4521 7.43% 88.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2878 4.73% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1749 2.88% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1023 1.68% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 226 0.37% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 91 0.15% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 113 0.19% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 47 0.08% 98.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 23 0.04% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.02% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 42 0.07% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 494 0.81% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 82 0.13% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 51 0.08% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 57 0.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 26 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 21 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 13 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60983 # Writes before turning the bus around for reads -system.physmem.totQLat 30413749694 # Total ticks spent queuing -system.physmem.totMemAccLat 47735149694 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4619040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32922.15 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 60832 # Writes before turning the bus around for reads +system.physmem.totQLat 46218732203 # Total ticks spent queuing +system.physmem.totMemAccLat 63602757203 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4635740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 49850.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51672.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 68600.44 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing -system.physmem.readRowHits 683627 # Number of row buffer hits during reads -system.physmem.writeRowHits 482581 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.26 # Row buffer hit rate for writes -system.physmem.avgGap 22602323.61 # Average gap between requests -system.physmem.pageHitRate 55.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3700302480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2019014250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3695975400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3926705040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1192499073090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27378533808750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31678634457810 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.688048 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45546210437205 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581932300000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 246167130795 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3308936400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1805471250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3509181000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3651784560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1178425765395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27390878815500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31675839532905 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.629051 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45566794873385 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581932300000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 225582219115 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 685692 # Number of row buffer hits during reads +system.physmem.writeRowHits 481982 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes +system.physmem.avgGap 22581201.38 # Average gap between requests +system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3446827860 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1832028660 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3331381200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3115139400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 41510941680.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 46501533090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2234866560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 80625696300 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 57761558880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11279719224960 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11520096687780 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.014314 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47297174723637 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3911587994 # Time in different power states +system.physmem_0.memoryStateTime::REF 17636282000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 46969945639000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 150420602883 # Time in different power states +system.physmem_0.memoryStateTime::ACT 86288423369 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 176810425254 # Time in different power states +system.physmem_1.actEnergy 3186367800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1693590855 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3288455520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2989885500 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 39461117280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47361781080 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2153404320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 72224847060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 55366694400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11285008491285 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11512750460370 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.859346 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47295506898407 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3731843770 # Time in different power states +system.physmem_1.memoryStateTime::REF 16766470000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 46992934432500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 144184093324 # Time in different power states +system.physmem_1.memoryStateTime::ACT 89007700573 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 158388420333 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -382,17 +393,17 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -422,73 +433,71 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 101108 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 101108 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9051 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76906 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 101094 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 101094 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 101094 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85971 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 24170.842493 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22339.898543 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14600.032387 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 76182 88.61% 88.61% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 8727 10.15% 98.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 200 0.23% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 718 0.84% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 29 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 34 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 12 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 19 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85971 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -250064880 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.334382 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.471774 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -166447796 66.56% 66.56% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -83617084 33.44% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -250064880 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 76906 89.47% 89.47% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9051 10.53% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85957 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101108 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 110745 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 110745 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10295 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84545 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 110723 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.234820 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 78.136585 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 110722 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 110723 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 94862 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23879.314162 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22054.085361 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16759.177694 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 93763 98.84% 98.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 840 0.89% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 113 0.12% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 94862 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -2682325288 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 2.121047 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 3007013124 -112.10% -112.10% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -5689338412 212.10% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -2682325288 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 84546 89.14% 89.14% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10295 10.86% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 94841 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 110745 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101108 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85957 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 110745 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94841 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85957 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 187065 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 205586 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 84046306 # DTB read hits -system.cpu0.dtb.read_misses 73432 # DTB read misses -system.cpu0.dtb.write_hits 77237834 # DTB write hits -system.cpu0.dtb.write_misses 27676 # DTB write misses +system.cpu0.dtb.read_hits 86849149 # DTB read hits +system.cpu0.dtb.read_misses 83538 # DTB read misses +system.cpu0.dtb.write_hits 78785461 # DTB write hits +system.cpu0.dtb.write_misses 27207 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35922 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37555 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4635 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4746 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9711 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 84119738 # DTB read accesses -system.cpu0.dtb.write_accesses 77265510 # DTB write accesses +system.cpu0.dtb.perms_faults 9443 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86932687 # DTB read accesses +system.cpu0.dtb.write_accesses 78812668 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 161284140 # DTB hits -system.cpu0.dtb.misses 101108 # DTB misses -system.cpu0.dtb.accesses 161385248 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 165634610 # DTB hits +system.cpu0.dtb.misses 110745 # DTB misses +system.cpu0.dtb.accesses 165745355 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -518,763 +527,759 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 58460 # Table walker walks requested -system.cpu0.itb.walker.walksLong 58460 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 540 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52669 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 58460 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 58460 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 58460 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 53209 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26190.982728 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24044.890366 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17871.734437 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 47169 88.65% 88.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 4943 9.29% 97.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 65 0.12% 98.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 859 1.61% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.07% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 25 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 53209 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 52669 98.99% 98.99% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 540 1.01% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 53209 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 57780 # Table walker walks requested +system.cpu0.itb.walker.walksLong 57780 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 572 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51544 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 57780 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 57780 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 57780 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52116 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25803.102694 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23425.328726 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 22386.426518 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 51056 97.97% 97.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 692 1.33% 99.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 219 0.42% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 60 0.12% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.10% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 14 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52116 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 51544 98.90% 98.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 572 1.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52116 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 58460 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 58460 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57780 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57780 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53209 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53209 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 111669 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 449335815 # ITB inst hits -system.cpu0.itb.inst_misses 58460 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52116 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52116 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 109896 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 463942995 # ITB inst hits +system.cpu0.itb.inst_misses 57780 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24946 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26477 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 449394275 # ITB inst accesses -system.cpu0.itb.hits 449335815 # DTB hits -system.cpu0.itb.misses 58460 # DTB misses -system.cpu0.itb.accesses 449394275 # DTB accesses -system.cpu0.numPwrStateTransitions 8624 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 4312 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 10857440365.954313 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 156382311444.961365 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3059 70.94% 70.94% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 1229 28.50% 99.44% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.05% 99.49% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.54% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.58% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.65% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 14 0.32% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 464000775 # ITB inst accesses +system.cpu0.itb.hits 463942995 # DTB hits +system.cpu0.itb.misses 57780 # DTB misses +system.cpu0.itb.accesses 464000775 # DTB accesses +system.cpu0.numPwrStateTransitions 8984 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 4492 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 10426010818.709705 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 169261679723.888153 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3260 72.57% 72.57% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1205 26.83% 99.40% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 8 0.18% 99.58% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.60% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 12 0.27% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7470353528320 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 4312 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 557032552505 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46817282857995 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94748630821 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7033293863000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 4492 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 571372362856 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46833640597644 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94810025915 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4312 # number of quiesce instructions executed -system.cpu0.committedInsts 449083110 # Number of instructions committed -system.cpu0.committedOps 528384419 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 485390643 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 507449 # Number of float alu accesses -system.cpu0.num_func_calls 26866500 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68160489 # number of instructions that are conditional controls -system.cpu0.num_int_insts 485390643 # number of integer instructions -system.cpu0.num_fp_insts 507449 # number of float instructions -system.cpu0.num_int_register_reads 703891240 # number of times the integer registers were read -system.cpu0.num_int_register_writes 384865941 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 816779 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 435492 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 117650799 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 117386896 # number of times the CC registers were written -system.cpu0.num_mem_refs 161276211 # number of memory refs -system.cpu0.num_load_insts 84042257 # Number of load instructions -system.cpu0.num_store_insts 77233954 # Number of store instructions -system.cpu0.num_idle_cycles 93634565715.988022 # Number of idle cycles -system.cpu0.num_busy_cycles 1114065105.011976 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011758 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988242 # Percentage of idle cycles -system.cpu0.Branches 100200450 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 366086093 69.25% 69.25% # Class of executed instruction -system.cpu0.op_class::IntMult 1185979 0.22% 69.47% # Class of executed instruction -system.cpu0.op_class::IntDiv 59083 0.01% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 72839 0.01% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::MemRead 84042257 15.90% 85.39% # Class of executed instruction -system.cpu0.op_class::MemWrite 77233954 14.61% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 4492 # number of quiesce instructions executed +system.cpu0.committedInsts 463690677 # Number of instructions committed +system.cpu0.committedOps 544305781 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 499985272 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 430429 # Number of float alu accesses +system.cpu0.num_func_calls 27825312 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 70353837 # number of instructions that are conditional controls +system.cpu0.num_int_insts 499985272 # number of integer instructions +system.cpu0.num_fp_insts 430429 # number of float instructions +system.cpu0.num_int_register_reads 725660016 # number of times the integer registers were read +system.cpu0.num_int_register_writes 396645033 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 713342 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 322808 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 121489824 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 121106505 # number of times the CC registers were written +system.cpu0.num_mem_refs 165624912 # number of memory refs +system.cpu0.num_load_insts 86844124 # Number of load instructions +system.cpu0.num_store_insts 78780788 # Number of store instructions +system.cpu0.num_idle_cycles 93667281189.358337 # Number of idle cycles +system.cpu0.num_busy_cycles 1142744725.641658 # Number of busy cycles +system.cpu0.not_idle_fraction 0.012053 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.987947 # Percentage of idle cycles +system.cpu0.Branches 103560532 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 377679680 69.35% 69.35% # Class of executed instruction +system.cpu0.op_class::IntMult 1190205 0.22% 69.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 61578 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 44848 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::MemRead 86844124 15.95% 85.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 78780788 14.47% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 528680248 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5566798 # number of replacements -system.cpu0.dcache.tags.tagsinuse 502.671926 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155470196 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5567308 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.925560 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.671926 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981781 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.981781 # Average percentage of cache occupancy +system.cpu0.op_class::total 544601223 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5731745 # number of replacements +system.cpu0.dcache.tags.tagsinuse 479.859189 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 159669170 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5732255 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.854513 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.859189 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937225 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.937225 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 452 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 328131694 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 328131694 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 78275725 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78275725 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72837974 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72837974 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200143 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 200143 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 232092 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 232092 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1764306 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1764306 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721538 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1721538 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 151345791 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 151345791 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 151545934 # number of overall hits -system.cpu0.dcache.overall_hits::total 151545934 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2974115 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2974115 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1412109 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1412109 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649854 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 649854 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801670 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 801670 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 161158 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 161158 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202775 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 202775 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5187894 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5187894 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5837748 # number of overall misses -system.cpu0.dcache.overall_misses::total 5837748 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44497648000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 44497648000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28844482000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 28844482000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25694293000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25694293000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2462602000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2462602000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4821620000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4821620000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2416000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2416000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 99036423000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 99036423000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 99036423000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 99036423000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 81249840 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 81249840 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74250083 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74250083 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 849997 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 849997 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033762 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1033762 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1925464 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1925464 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1924313 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1924313 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156533685 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156533685 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 157383682 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 157383682 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036605 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036605 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019018 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.019018 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764537 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.764537 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.775488 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.775488 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.105375 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.105375 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033142 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033142 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037092 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037092 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14961.643380 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14961.643380 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20426.526564 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20426.526564 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32050.959871 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32050.959871 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15280.668661 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15280.668661 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23778.177783 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23778.177783 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 337018109 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 337018109 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 80850678 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80850678 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 74290365 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 74290365 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 206988 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 206988 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 237888 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 237888 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1848102 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1848102 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1813975 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1813975 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 155378931 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155378931 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155585919 # number of overall hits +system.cpu0.dcache.overall_hits::total 155585919 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3109712 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3109712 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1421405 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1421405 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649654 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 649654 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796576 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 796576 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167654 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 167654 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200528 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 200528 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5327693 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5327693 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5977347 # number of overall misses +system.cpu0.dcache.overall_misses::total 5977347 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 48841831500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 48841831500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 30112535000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 30112535000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25700725500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 25700725500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2575322000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2575322000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4758884500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4758884500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2246000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 104655092000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 104655092000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 104655092000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 104655092000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83960390 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83960390 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 75711770 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 75711770 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 856642 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 856642 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1034464 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1034464 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015756 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2015756 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014503 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2014503 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 160706624 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 160706624 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 161563266 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 161563266 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037038 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037038 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018774 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018774 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758373 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.758373 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.770037 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.770037 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083172 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083172 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033152 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033152 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036997 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036997 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15706.223438 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15706.223438 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21185.049300 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21185.049300 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32263.996781 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32263.996781 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.933828 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.933828 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23731.770626 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23731.770626 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19089.908738 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19089.908738 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16964.833528 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16964.833528 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19643.604089 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19643.604089 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17508.619125 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17508.619125 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5566798 # number of writebacks -system.cpu0.dcache.writebacks::total 5566798 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 29633 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 29633 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21518 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21518 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45711 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45711 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 51151 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 51151 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 51151 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 51151 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2944482 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2944482 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1390591 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1390591 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648168 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 648168 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801670 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 801670 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115447 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115447 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202775 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 202775 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5136743 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5136743 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5784911 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5784911 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21025 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22388 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 43413 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40085054500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40085054500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26946583500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26946583500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14957704500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14957704500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24892623000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24892623000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1575244000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1575244000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4618898000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4618898000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2363000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2363000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 91924261000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 91924261000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106881965500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 106881965500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3989550000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3989550000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3989550000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3989550000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036240 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036240 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018728 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018728 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762553 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762553 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.775488 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.775488 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059958 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059958 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.105375 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.105375 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032816 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032816 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036757 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036757 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13613.618456 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13613.618456 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19377.792248 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19377.792248 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23076.894416 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23076.894416 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31050.959871 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31050.959871 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13644.737412 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13644.737412 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22778.439157 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22778.439157 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5731745 # number of writebacks +system.cpu0.dcache.writebacks::total 5731745 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26385 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 26385 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21245 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21245 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44162 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44162 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 47630 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 47630 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 47630 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 47630 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3083327 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3083327 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1400160 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1400160 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648080 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 648080 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796576 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 796576 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123492 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123492 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200528 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 200528 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5280063 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5280063 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5928143 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5928143 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16381 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34075 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44323294000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44323294000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28148510000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28148510000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14944693500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14944693500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24904149500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24904149500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1681387500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1681387500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4558410500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4558410500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2192000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2192000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 97375953500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 97375953500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112320647000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 112320647000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3040589500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3040589500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3040589500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3040589500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036724 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036724 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018493 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018493 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756535 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756535 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.770037 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.770037 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061263 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061263 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099542 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099542 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032855 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032855 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036692 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036692 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14375.151906 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14375.151906 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20103.780996 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20103.780996 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23059.951703 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23059.951703 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31263.996781 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31263.996781 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13615.355651 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13615.355651 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22732.039915 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22732.039915 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17895.437050 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.437050 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18475.991333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18475.991333 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189752.675386 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189752.675386 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91897.588280 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91897.588280 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5174135 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.907744 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 444161163 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5174647 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.834099 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30089682000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907744 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18442.195387 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18442.195387 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.020509 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.020509 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185616.842684 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185616.842684 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89232.267058 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89232.267058 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 4959559 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.903947 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 458982923 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4960071 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 92.535555 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30768955000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903947 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 903846282 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 903846282 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 444161163 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 444161163 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 444161163 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 444161163 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 444161163 # number of overall hits -system.cpu0.icache.overall_hits::total 444161163 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5174652 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5174652 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5174652 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5174652 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5174652 # number of overall misses -system.cpu0.icache.overall_misses::total 5174652 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55704586500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 55704586500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 55704586500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 55704586500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 55704586500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 55704586500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 449335815 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 449335815 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 449335815 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 449335815 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 449335815 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 449335815 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011516 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011516 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011516 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011516 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011516 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011516 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10764.895205 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10764.895205 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10764.895205 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10764.895205 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 932846061 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 932846061 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 458982923 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 458982923 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 458982923 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 458982923 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 458982923 # number of overall hits +system.cpu0.icache.overall_hits::total 458982923 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4960072 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4960072 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4960072 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4960072 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4960072 # number of overall misses +system.cpu0.icache.overall_misses::total 4960072 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54306348500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 54306348500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 54306348500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 54306348500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 54306348500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 54306348500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 463942995 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 463942995 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 463942995 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 463942995 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 463942995 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 463942995 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010691 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010691 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010691 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010691 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010691 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010691 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.701652 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.701652 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10948.701652 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10948.701652 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5174135 # number of writebacks -system.cpu0.icache.writebacks::total 5174135 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5174652 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5174652 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5174652 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5174652 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5174652 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5174652 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 4959559 # number of writebacks +system.cpu0.icache.writebacks::total 4959559 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4960072 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4960072 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4960072 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4960072 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4960072 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4960072 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 53117260500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 53117260500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 53117260500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 53117260500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 53117260500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 53117260500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011516 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011516 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011516 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10264.895205 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7568346 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7568354 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51826313000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 51826313000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51826313000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 51826313000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51826313000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 51826313000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010691 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010691 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10448.701753 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7732053 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7732077 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 981182 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2342884 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15723.839714 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9135802 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2358598 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.873404 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15407.459260 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.158261 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.135006 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 251.087187 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.940397 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002329 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001656 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.015325 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.959707 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 345 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15297 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 167 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 1019171 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2286879 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15893.622807 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9162734 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2302009 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.980321 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5406430500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15603.896064 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 29.949034 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 16.856945 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 242.920764 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.952386 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001828 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001029 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014827 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.970070 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 306 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14757 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 139 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 67 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 53 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1333 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5696 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7896 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021057 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933655 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 370311903 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 370311903 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 225709 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148168 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 373877 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3696575 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3696575 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7043197 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7043197 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 878685 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 878685 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4695575 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4695575 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2752703 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2752703 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216682 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 216682 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 225709 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 148168 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4695575 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3631388 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8700840 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 225709 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 148168 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4695575 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3631388 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8700840 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 18676 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10607 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 29283 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 251664 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 251664 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202763 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 202763 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 12 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 12 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278535 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 278535 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 479077 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 479077 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 955394 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 955394 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582714 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 582714 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 18676 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10607 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 479077 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1233929 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1742289 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 18676 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10607 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 479077 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1233929 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1742289 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 564732000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 371950000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 936682000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 916815500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 916815500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 321936500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 321936500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2282499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2282499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12626438998 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 12626438998 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17151939500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17151939500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33121351500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33121351500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 399249500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 399249500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 564732000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 371950000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17151939500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 45747790498 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 63836411998 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 564732000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 371950000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17151939500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 45747790498 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 63836411998 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 244385 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 158775 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 403160 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3696575 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3696575 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7043197 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7043197 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 251664 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 251664 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202763 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 202763 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 12 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 12 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1157220 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1157220 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5174652 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5174652 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3708097 # 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number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6702281000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062868 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1283,123 +1288,124 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236016 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236016 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092581 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257538 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257538 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728943 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728943 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.166278 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.204964 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.204964 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092084 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242633 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242633 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.726644 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.726644 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159374 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.235841 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25987.228085 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43310.223511 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18525.289672 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18525.289672 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15274.090934 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15274.090934 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 163708.250000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 163708.250000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38278.277545 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38278.277545 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29802.051653 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28643.524399 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28643.524399 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32147.228314 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32147.228314 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30433.782810 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34231.791627 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181726.848989 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114058.293063 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 88010.665008 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 84550.596270 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 22270826 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11431607 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 634641 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 634635 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 532548 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9516927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 22389 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 22388 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5262772 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7044356 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1133181 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 892107 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 438346 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 371201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 524392 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1190804 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1167926 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5174652 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4606140 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 845268 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 799396 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15609689 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18074319 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 333482 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 538074 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34555564 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662494868 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 674962485 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1270200 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1955080 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1340682633 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5171785 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 107950516 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 16772894 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.051983 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.221994 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231324 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28364.489475 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49385.735208 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18573.965548 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18573.965548 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15227.675321 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15227.675321 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178549.700000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178549.700000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48088.156473 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48088.156473 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31960.284185 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32588.368843 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32588.368843 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32541.105310 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32541.105310 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34607.596091 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39204.122111 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177595.049142 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112632.020300 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85375.920763 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86817.111399 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 22159208 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11368269 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 619514 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 619512 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 553426 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9465318 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 17695 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 17694 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5316723 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6896635 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1098455 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 916448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 433150 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 369627 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 506111 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1214944 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1192020 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4960072 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4756139 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 842201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 794505 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14965952 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18512478 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327835 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 591529 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34397794 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 635028820 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696134983 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241656 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2161912 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1334567371 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5130075 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 104832276 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 16684270 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.051566 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.221149 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15900995 94.80% 94.80% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 871893 5.20% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15823936 94.84% 94.84% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 860332 5.16% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 16772894 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 22046960997 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 16684270 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 21945410994 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 203834159 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 195855793 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7805103000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7483231500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7957435977 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8196031021 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 174707000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 172628000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 293689000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 321290000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1429,75 +1435,71 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 113512 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 113512 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10824 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86665 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 27 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 113485 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.290787 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 77.918264 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 113483 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 113485 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 97516 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23769.576275 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22071.904189 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14608.572728 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 88342 90.59% 90.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 8042 8.25% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 147 0.15% 98.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 810 0.83% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 18 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 45 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 17 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 36 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 97516 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 14762172 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 194.841712 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2861524688 -19384.17% -19384.17% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 2876286860 19484.17% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 14762172 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 86666 88.90% 88.90% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10824 11.10% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97490 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 113512 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 99152 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 99152 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8586 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75770 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 99148 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.080687 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 25.406685 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 99147 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 99148 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84360 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24513.021574 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22367.425597 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 18734.439703 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 83116 98.53% 98.53% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 940 1.11% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.19% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 58 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84360 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 407519048 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 2.490877 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -607560648 -149.09% -149.09% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1015079696 249.09% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 407519048 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 75770 89.82% 89.82% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8586 10.18% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84356 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99152 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 113512 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97490 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99152 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84356 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97490 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 211002 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84356 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 183508 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 83873503 # DTB read hits -system.cpu1.dtb.read_misses 85876 # DTB read misses -system.cpu1.dtb.write_hits 75393075 # DTB write hits -system.cpu1.dtb.write_misses 27636 # DTB write misses +system.cpu1.dtb.read_hits 78885011 # DTB read hits +system.cpu1.dtb.read_misses 72039 # DTB read misses +system.cpu1.dtb.write_hits 71761800 # DTB write hits +system.cpu1.dtb.write_misses 27113 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 39012 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36637 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3907 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3802 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10199 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 83959379 # DTB read accesses -system.cpu1.dtb.write_accesses 75420711 # DTB write accesses +system.cpu1.dtb.perms_faults 10123 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 78957050 # DTB read accesses +system.cpu1.dtb.write_accesses 71788913 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 159266578 # DTB hits -system.cpu1.dtb.misses 113512 # DTB misses -system.cpu1.dtb.accesses 159380090 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 150646811 # DTB hits +system.cpu1.dtb.misses 99152 # DTB misses +system.cpu1.dtb.accesses 150745963 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1527,759 +1529,759 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 59776 # Table walker walks requested -system.cpu1.itb.walker.walksLong 59776 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 674 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53293 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 59776 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 59776 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 59776 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53967 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25622.306224 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23504.254601 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18586.945639 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 52820 97.87% 97.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 977 1.81% 99.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 34 0.06% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.11% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 61 0.11% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53967 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1314622148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1314622148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1314622148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 53293 98.75% 98.75% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 674 1.25% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53967 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 58316 # Table walker walks requested +system.cpu1.itb.walker.walksLong 58316 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52495 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 58316 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 58316 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 58316 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53121 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27183.693831 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24219.790403 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 26514.333195 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 51734 97.39% 97.39% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 949 1.79% 99.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 242 0.46% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.15% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 33 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 53121 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -615394148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -615394148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -615394148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 52495 98.82% 98.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 626 1.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53121 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59776 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59776 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58316 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58316 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53967 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53967 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 113743 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 442849873 # ITB inst hits -system.cpu1.itb.inst_misses 59776 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53121 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53121 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 111437 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 416140593 # ITB inst hits +system.cpu1.itb.inst_misses 58316 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 27503 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25699 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 442909649 # ITB inst accesses -system.cpu1.itb.hits 442849873 # DTB hits -system.cpu1.itb.misses 59776 # DTB misses -system.cpu1.itb.accesses 442909649 # DTB accesses -system.cpu1.numPwrStateTransitions 28574 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 14287 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3279405691.982362 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 123453533761.994095 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4140 28.98% 28.98% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 10126 70.88% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 416198909 # ITB inst accesses +system.cpu1.itb.hits 416140593 # DTB hits +system.cpu1.itb.misses 58316 # DTB misses +system.cpu1.itb.accesses 416198909 # DTB accesses +system.cpu1.numPwrStateTransitions 28692 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 14346 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3269284130.341071 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 86001867955.202789 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3953 27.55% 27.55% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10364 72.24% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813601970000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 14287 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 521446289148 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46852869121352 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94748630821 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7510077904252 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 14346 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 503862826627 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46901150133873 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94810025921 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14287 # number of quiesce instructions executed -system.cpu1.committedInsts 442543215 # Number of instructions committed -system.cpu1.committedOps 520378160 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 478315040 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 404780 # Number of float alu accesses -system.cpu1.num_func_calls 26483096 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67217461 # number of instructions that are conditional controls -system.cpu1.num_int_insts 478315040 # number of integer instructions -system.cpu1.num_fp_insts 404780 # number of float instructions -system.cpu1.num_int_register_reads 696723237 # number of times the integer registers were read -system.cpu1.num_int_register_writes 379679857 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 664337 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 317564 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 114632172 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 114267384 # number of times the CC registers were written -system.cpu1.num_mem_refs 159256484 # number of memory refs -system.cpu1.num_load_insts 83870110 # Number of load instructions -system.cpu1.num_store_insts 75386374 # Number of store instructions -system.cpu1.num_idle_cycles 93705738242.702026 # Number of idle cycles -system.cpu1.num_busy_cycles 1042892578.297978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011007 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988993 # Percentage of idle cycles -system.cpu1.Branches 98643380 # Number of branches fetched -system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 360264761 69.19% 69.19% # Class of executed instruction -system.cpu1.op_class::IntMult 1062033 0.20% 69.39% # Class of executed instruction -system.cpu1.op_class::IntDiv 60918 0.01% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 40731 0.01% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 83870110 16.11% 85.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 75386374 14.48% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 14346 # number of quiesce instructions executed +system.cpu1.committedInsts 415840875 # Number of instructions committed +system.cpu1.committedOps 490335926 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 450775425 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 467875 # Number of float alu accesses +system.cpu1.num_func_calls 24835210 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 63203882 # number of instructions that are conditional controls +system.cpu1.num_int_insts 450775425 # number of integer instructions +system.cpu1.num_fp_insts 467875 # number of float instructions +system.cpu1.num_int_register_reads 655878523 # number of times the integer registers were read +system.cpu1.num_int_register_writes 357644258 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 746575 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 415812 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 107608929 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 107374492 # number of times the CC registers were written +system.cpu1.num_mem_refs 150638767 # number of memory refs +system.cpu1.num_load_insts 78882725 # Number of load instructions +system.cpu1.num_store_insts 71756042 # Number of store instructions +system.cpu1.num_idle_cycles 93802300267.744019 # Number of idle cycles +system.cpu1.num_busy_cycles 1007725653.255979 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010629 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989371 # Percentage of idle cycles +system.cpu1.Branches 92635099 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 338840052 69.06% 69.06% # Class of executed instruction +system.cpu1.op_class::IntMult 1031473 0.21% 69.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 58381 0.01% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 67037 0.01% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::MemRead 78882725 16.08% 85.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 71756042 14.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 520684927 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5203972 # number of replacements -system.cpu1.dcache.tags.tagsinuse 424.411021 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 153866536 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5204484 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.564225 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8378899013000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 424.411021 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.828928 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.828928 # Average percentage of cache occupancy +system.cpu1.op_class::total 490635753 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 4949273 # number of replacements +system.cpu1.dcache.tags.tagsinuse 456.328608 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 145491110 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4949785 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.393420 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379669141000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.328608 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891267 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.891267 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 323742508 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 323742508 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 78110378 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 78110378 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 71558729 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 71558729 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177304 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 177304 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 95899 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 95899 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1773602 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1773602 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1738086 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1738086 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 149765006 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 149765006 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 149942310 # number of overall hits -system.cpu1.dcache.overall_hits::total 149942310 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2993339 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2993339 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1322577 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1322577 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630415 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 630415 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446111 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 446111 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170906 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 170906 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 205163 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 205163 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4762027 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4762027 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5392442 # number of overall misses -system.cpu1.dcache.overall_misses::total 5392442 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43487315000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 43487315000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24009342500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 24009342500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10785817000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10785817000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2544188500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2544188500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4864957000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4864957000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2180500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2180500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 78282474500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 78282474500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 78282474500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 78282474500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 81103717 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 81103717 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72881306 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72881306 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807719 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 807719 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 542010 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 542010 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1944508 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1944508 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1943249 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1943249 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154527033 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154527033 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155334752 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155334752 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036908 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036908 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018147 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018147 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780488 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780488 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.823068 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.823068 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087892 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087892 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105577 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105577 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030817 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.030817 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034715 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034715 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14528.028733 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14528.028733 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18153.455338 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18153.455338 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24177.428936 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24177.428936 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14886.478532 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14886.478532 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23712.643118 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23712.643118 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 306227498 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 306227498 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 73475131 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73475131 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68103188 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68103188 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 168046 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 168046 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 87192 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 87192 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1644934 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1644934 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602204 # 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number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160663 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 160663 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202242 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 202242 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4540855 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4540855 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5150044 # number of overall misses +system.cpu1.dcache.overall_misses::total 5150044 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42649111500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 42649111500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25017964000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 25017964000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10518897000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10518897000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2505987000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2505987000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4791659000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4791659000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2159000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2159000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 78185972500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 78185972500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 78185972500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 78185972500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 76279994 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 76279994 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69396149 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69396149 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 777235 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 777235 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 530223 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 530223 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1805597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1805597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1804446 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1804446 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 146206366 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146206366 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 146983601 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 146983601 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036771 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036771 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018632 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018632 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783790 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783790 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.835556 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.835556 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088981 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088981 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112080 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112080 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031058 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031058 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035038 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035038 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.416985 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.416985 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19349.357019 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19349.357019 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23743.027012 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23743.027012 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15597.785427 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15597.785427 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23692.699835 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23692.699835 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16438.897658 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16438.897658 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14517.073063 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14517.073063 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17218.337185 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17218.337185 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15181.612526 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15181.612526 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5203972 # number of writebacks -system.cpu1.dcache.writebacks::total 5203972 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14156 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 14156 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 216 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44175 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44175 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 14372 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 14372 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 14372 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 14372 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2979183 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2979183 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1322361 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1322361 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630415 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 630415 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446111 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 446111 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126731 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126731 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 205163 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 205163 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4747655 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4747655 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5378070 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5378070 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17577 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33702 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39805955500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39805955500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22681350000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22681350000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12330973000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12330973000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10339706000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10339706000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1686365000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1686365000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4659843000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4659843000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2131500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2131500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72827011500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 72827011500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85157984500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 85157984500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2978895500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2978895500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2978895500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2978895500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036733 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036733 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018144 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018144 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780488 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780488 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.823068 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.823068 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105577 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105577 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030724 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030724 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034622 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034622 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.366354 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13361.366354 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17152.161929 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17152.161929 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19560.088196 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19560.088196 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23177.428936 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23177.428936 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13306.649517 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13306.649517 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22712.881952 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22712.881952 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4949273 # number of writebacks +system.cpu1.dcache.writebacks::total 4949273 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18154 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 18154 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 423 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 423 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43805 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43805 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 18577 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 18577 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 18577 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 18577 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2786709 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2786709 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1292538 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1292538 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 609189 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 609189 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 443031 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 443031 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116858 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116858 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202242 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 202242 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4522278 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4522278 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5131467 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5131467 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22203 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42958 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38628648000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38628648000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23695979500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23695979500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13886318000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13886318000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10075866000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10075866000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1623112500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1623112500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4589466000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4589466000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2110000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2110000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72400493500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 72400493500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 86286811500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 86286811500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3923399500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3923399500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3923399500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3923399500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036533 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036533 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018626 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018626 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783790 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783790 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.835556 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.835556 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064720 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064720 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112080 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112080 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030931 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030931 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034912 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034912 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13861.744445 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13861.744445 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18332.907427 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18332.907427 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22794.761560 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22794.761560 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22743.027012 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22743.027012 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13889.613890 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13889.613890 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22692.942119 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22692.942119 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15339.575327 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15339.575327 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15834.301989 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15834.301989 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169476.901633 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169476.901633 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.279568 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 88389.279568 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4895837 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.209399 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 437953524 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4896349 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 89.444916 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8378871626000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.209399 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969159 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969159 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16009.739671 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16009.739671 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16815.232662 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16815.232662 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176705.828041 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176705.828041 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91331.055915 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91331.055915 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 4981311 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.212019 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 411158765 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4981823 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 82.531789 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8379594860000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.212019 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 890596095 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 890596095 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 437953524 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 437953524 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 437953524 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 437953524 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 437953524 # number of overall hits -system.cpu1.icache.overall_hits::total 437953524 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4896349 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4896349 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4896349 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4896349 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4896349 # number of overall misses -system.cpu1.icache.overall_misses::total 4896349 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51444170000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 51444170000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 51444170000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 51444170000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 51444170000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 51444170000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 442849873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 442849873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 442849873 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 442849873 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 442849873 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 442849873 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011056 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011056 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011056 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011056 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011056 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011056 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10506.638722 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10506.638722 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10506.638722 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10506.638722 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 837263014 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 837263014 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 411158765 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 411158765 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 411158765 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 411158765 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 411158765 # number of overall hits +system.cpu1.icache.overall_hits::total 411158765 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4981828 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4981828 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4981828 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4981828 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4981828 # number of overall misses +system.cpu1.icache.overall_misses::total 4981828 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54111358000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 54111358000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 54111358000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 54111358000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 54111358000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 54111358000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 416140593 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 416140593 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 416140593 # 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average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10861.747535 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10861.747535 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4895837 # 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average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94563.636364 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94563.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7252070 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7252079 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 8 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51620444000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 51620444000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51620444000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 51620444000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51620444000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 51620444000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10472000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10472000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10472000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10472000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011972 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011972 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011972 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10361.747535 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95200 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95200 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6872416 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6872436 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 18 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 909185 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1859788 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13078.836793 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 8983696 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1875537 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.789933 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 852028 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 1861043 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12976.163549 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 8767962 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1876890 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.671537 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12823.617935 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.493162 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 11.479573 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 226.246124 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.782692 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001068 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000701 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013809 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.798269 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15409 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 107 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 144 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 868 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6435 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7258 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940491 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 348956442 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 348956442 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 258658 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151547 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 410205 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3266667 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3266667 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6832390 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6832390 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 881671 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 881671 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4452144 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4452144 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2841120 # 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number of overall hits -system.cpu1.l2cache.overall_hits::total 8585140 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18381 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9249 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 27630 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 207506 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 207506 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 205160 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 205160 # number of SCUpgradeReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 12709.863020 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.854479 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 23.050365 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 215.395684 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.775748 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001700 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001407 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013147 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.792002 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 377 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15415 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 69 # 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mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.063106 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43068 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 360967500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 843363000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27800562984 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3852073000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3852073000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3071337500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3071337500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1741999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1741999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9224946500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9224946500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14216700500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14216700500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26383538000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26383538000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6621907000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6621907000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 360967500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14216700500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35608484500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 50668548000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 360967500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14216700500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35608484500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 78469110984 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9647000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3745274000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3754921000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9647000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3745274000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3754921000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.071192 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2288,128 +2290,129 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.205818 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.205818 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090722 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.239512 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239512 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.567411 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.567411 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.156724 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226946 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226946 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090876 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253009 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253009 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565542 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565542 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161990 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.225464 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26936.029678 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41804.228740 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18587.327591 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18587.327591 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15206.589959 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15206.589959 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 588000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34644.743535 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34644.743535 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27535.565786 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27162.496717 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27162.496717 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27231.035824 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27231.035824 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28339.662371 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32444.781937 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161459.720089 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160997.031718 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 84207.984689 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 84217.274932 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 20954555 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10760929 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 564007 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 564007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228826 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29868.359541 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41689.317380 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18486.785462 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18486.785462 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15186.672699 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15186.672699 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 580666.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 580666.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37417.342684 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37417.342684 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31402.300057 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29685.784689 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29685.784689 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26547.838498 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26547.838498 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31349.139312 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34369.290310 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168683.241003 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168284.004840 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87184.552353 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87185.868859 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 20600525 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10578683 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 558580 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 558580 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 525208 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9244496 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 16125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 16125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4351848 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6833141 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1083593 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 850253 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 408331 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 372440 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 477174 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1146242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1123232 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4896349 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4644090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 493781 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 444195 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14688755 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16849115 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339302 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 606054 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32483226 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 626700344 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 649733422 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1286368 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2216312 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1279936446 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4601099 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 75959664 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 15521649 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.052382 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.222797 # Request fanout histogram +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 484798 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9068801 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 20755 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 20755 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4199993 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6807874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1098101 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 809012 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 385894 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368515 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 474989 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1114310 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1093127 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4981828 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4385137 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 490192 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 441051 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14945187 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16097398 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332311 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 526789 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 31901685 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 637641336 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617397659 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1265008 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1907912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1258211915 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4504290 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 75632944 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 15215883 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.052359 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.222750 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14708591 94.76% 94.76% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 813058 5.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14419192 94.76% 94.76% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 796691 5.24% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 15521649 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20731667993 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 15215883 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20375325498 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 171895510 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176794994 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7344633500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7472852000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7734220026 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7357432377 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 178506000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 174185000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 329015998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 288300000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40399 # Transaction distribution -system.iobus.trans_dist::ReadResp 40399 # Transaction distribution -system.iobus.trans_dist::WriteReq 136980 # Transaction distribution -system.iobus.trans_dist::WriteResp 136980 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47798 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40355 # Transaction distribution +system.iobus.trans_dist::ReadResp 40355 # Transaction distribution +system.iobus.trans_dist::WriteReq 136628 # Transaction distribution +system.iobus.trans_dist::WriteResp 136628 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2420,15 +2423,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122940 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231738 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231738 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354758 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47818 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2439,23 +2442,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155955 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513345 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37010502 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36982500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2469,75 +2472,75 @@ system.iobus.reqLayer16.occupancy 14000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26741000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26451500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37417000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 570750713 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569427501 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92947000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148178000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115853 # number of replacements -system.iocache.tags.tagsinuse 11.245503 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115615 # number of replacements +system.iocache.tags.tagsinuse 11.298649 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115869 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9136243501000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.839816 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.405687 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239988 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.462855 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.702844 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9136560427000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.416178 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.882471 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463511 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242654 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706166 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043178 # Number of tag accesses -system.iocache.tags.data_accesses 1043178 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040856 # Number of tag accesses +system.iocache.tags.data_accesses 1040856 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8885 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8922 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115869 # number of demand (read+write) misses -system.iocache.demand_misses::total 115909 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses +system.iocache.demand_misses::total 115651 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115869 # number of overall misses -system.iocache.overall_misses::total 115909 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5278000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1633593087 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1638871087 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115611 # number of overall misses +system.iocache.overall_misses::total 115651 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5193500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1828649003 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1833842503 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12911092626 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12911092626 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5647000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14544685713 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14550332713 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5647000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14544685713 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14550332713 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13346157998 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13346157998 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5562500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15174807001 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15180369501 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5562500 # 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number of overall (read+write) accesses +system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2551,53 +2554,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142648.648649 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183859.660889 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183688.756669 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140364.864865 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 205859.394686 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 205587.724552 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120682.463041 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120682.463041 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 141175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125532.380687 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 141175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125532.380687 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31750 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125048.328442 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125048.328442 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131260.166371 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131260.166371 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 41899 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3454 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.192241 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.852617 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106953 # number of writebacks -system.iocache.writebacks::total 106953 # number of writebacks +system.iocache.writebacks::writebacks 106702 # number of writebacks +system.iocache.writebacks::total 106702 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8885 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2611,662 +2614,659 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92648.648649 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133859.660889 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133688.756669 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90364.864865 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 155859.394686 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 155587.724552 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70601.106698 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70601.106698 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1378015 # number of replacements -system.l2c.tags.tagsinuse 64998.786153 # Cycle average of tags in use -system.l2c.tags.total_refs 6107230 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1440978 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.238253 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9552186500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11716.268844 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.184810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 146.917074 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4004.381376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 14231.433494 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7902.194687 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 315.518093 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 369.695425 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2763.350410 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11175.503416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12240.338524 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.178776 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002242 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061102 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.217154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.120578 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004814 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.005641 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042165 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.170525 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.186773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.991803 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 12060 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 189 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50714 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 60 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 153 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1009 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1115 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9723 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 184 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9563 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 39124 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.184021 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002884 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.773834 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 69629880 # Number of tag accesses -system.l2c.tags.data_accesses 69629880 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2641101 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2641101 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 213424 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 155298 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 368722 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 50511 # 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number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 512398 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 278781 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2494703 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 136557 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 120325 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 256882 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10681 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 422841 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 630910 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 276728 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9775 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4116 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14223.146945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 128.223998 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 149.509582 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3193.954857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6240.562219 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5949.868833 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.180717 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004651 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.005443 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.054714 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.291221 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217028 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001957 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002281 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.048736 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.095223 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.090788 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992758 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11266 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 259 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48663 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 297 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10816 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 888 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4525 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43209 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.171906 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003952 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.742538 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 68586261 # Number of tag accesses +system.l2c.tags.data_accesses 68586261 # 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average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 78070.533332 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80725.208799 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80065.548777 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97673.842846 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19906.284749 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19870.744158 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19898.586767 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163719.381879 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143473.769616 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106203.079428 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 79289.613802 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74823.486677 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 72216.646766 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3586859 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2135577 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.113100 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.123828 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.118083 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012676 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011369 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.012028 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.613362 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462767 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.542745 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208316 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.161585 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.235132 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.779663 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.455362 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.684738 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.255958 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.255958 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20237.632473 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20659.972419 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20443.328506 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24145.700637 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24889.891697 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24494.500846 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98522.851552 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99422.497215 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 98882.548681 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99545.289138 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106746.113985 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114384.543404 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19876.275455 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20102.436048 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19920.298767 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159587.876320 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150694.833566 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109809.654497 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76719.266383 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77883.788062 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74703.544659 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3576184 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2127782 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81835 # Transaction distribution -system.membus.trans_dist::ReadResp 841453 # Transaction distribution -system.membus.trans_dist::WriteReq 38513 # Transaction distribution -system.membus.trans_dist::WriteResp 38513 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1169257 # Transaction distribution -system.membus.trans_dist::CleanEvict 224172 # Transaction distribution -system.membus.trans_dist::UpgradeReq 330190 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 306798 # Transaction distribution -system.membus.trans_dist::UpgradeResp 21 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 142313 # Transaction distribution -system.membus.trans_dist::ReadExResp 124217 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 759618 # Transaction distribution -system.membus.trans_dist::InvalidateReq 654423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122940 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 81817 # Transaction distribution +system.membus.trans_dist::ReadResp 843472 # Transaction distribution +system.membus.trans_dist::WriteReq 38449 # Transaction distribution +system.membus.trans_dist::WriteResp 38449 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1169254 # Transaction distribution +system.membus.trans_dist::CleanEvict 223620 # Transaction distribution +system.membus.trans_dist::UpgradeReq 320332 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 305580 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 143723 # Transaction distribution +system.membus.trans_dist::ReadExResp 125482 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 761655 # Transaction distribution +system.membus.trans_dist::InvalidateReq 651499 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4320804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4469902 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238504 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238504 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4708406 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155955 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4313500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4462434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238025 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238025 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4700459 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124129580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124337871 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7276480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131614351 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 603280 # Total snoops (count) -system.membus.snoopTraffic 185472 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2313692 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013382 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.114902 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124357036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 124565390 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7261504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7261504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131826894 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 595046 # Total snoops (count) +system.membus.snoopTraffic 184128 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2303059 # Request fanout histogram +system.membus.snoop_fanout::mean 0.014256 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.118544 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2282731 98.66% 98.66% # Request fanout histogram -system.membus.snoop_fanout::1 30961 1.34% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2270227 98.57% 98.57% # Request fanout histogram +system.membus.snoop_fanout::1 32832 1.43% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2313692 # Request fanout histogram -system.membus.reqLayer0.occupancy 101576998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2303059 # Request fanout histogram +system.membus.reqLayer0.occupancy 101257500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21542999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21679000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8037178912 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8033203938 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4828786098 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4846349578 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45456460 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45469982 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3309,78 +3309,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10929949 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5951808 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1800454 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 181173 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 166358 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14815 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81837 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4119674 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38513 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38513 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3703405 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2363493 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 695815 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 407836 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1103651 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 294367 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 294367 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4038548 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 834564 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 806756 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8843715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7139942 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15983657 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216752505 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175713942 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 392466447 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2839573 # Total snoops (count) -system.toL2Bus.snoopTraffic 122328784 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7769609 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.368989 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486467 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10759482 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5851735 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1766751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 181547 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 166860 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14687 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 81819 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4062742 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38449 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38449 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3651776 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2342209 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 672985 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 402667 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1075652 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 288170 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 288170 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3981632 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 828938 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 799211 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8607895 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7128520 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15736415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 211923339 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 174059331 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 385982670 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2818319 # Total snoops (count) +system.toL2Bus.snoopTraffic 121467536 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7671705 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.367658 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486122 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4917524 63.29% 63.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2837270 36.52% 99.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14815 0.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4865825 63.43% 63.43% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2791193 36.38% 99.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14687 0.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7769609 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8597464366 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7671705 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8456586164 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2599172 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2556167 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4012155776 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3921212144 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3555978029 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3534160915 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal index 8a6e02412..1ab2ced54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000027] Console: colour dummy device 80x25
-[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000032] pid_max: default: 32768 minimum: 301
-[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000186] hw perfevents: no hardware support available
-[ 0.060051] CPU1: Booted secondary processor
-[ 1.080095] CPU2: failed to come online
-[ 2.100183] CPU3: failed to come online
-[ 2.100186] Brought up 2 CPUs
-[ 2.100188] SMP: Total of 2 processors activated.
-[ 2.100259] devtmpfs: initialized
-[ 2.100898] atomic64_test: passed
-[ 2.100952] regulator-dummy: no parameters
-[ 2.101389] NET: Registered protocol family 16
-[ 2.101557] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.101563] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.102363] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.102366] Serial: AMBA PL011 UART driver
-[ 2.102592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.102637] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.103214] console [ttyAMA0] enabled
-[ 2.103383] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.103459] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.103535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.103603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.130362] 3V3: 3300 mV
-[ 2.130420] vgaarb: loaded
-[ 2.130477] SCSI subsystem initialized
-[ 2.130513] libata version 3.00 loaded.
-[ 2.130567] usbcore: registered new interface driver usbfs
-[ 2.130587] usbcore: registered new interface driver hub
-[ 2.130614] usbcore: registered new device driver usb
-[ 2.130645] pps_core: LinuxPPS API ver. 1 registered
-[ 2.130654] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.130674] PTP clock support registered
-[ 2.130822] Switched to clocksource arch_sys_counter
-[ 2.132478] NET: Registered protocol family 2
-[ 2.132574] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.132613] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.132642] TCP: reno registered
-[ 2.132649] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.132663] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.132704] NET: Registered protocol family 1
-[ 2.132763] RPC: Registered named UNIX socket transport module.
-[ 2.132774] RPC: Registered udp transport module.
-[ 2.132782] RPC: Registered tcp transport module.
-[ 2.132791] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.132804] PCI: CLS 0 bytes, default 64
-[ 2.133012] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.133128] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.135205] fuse init (API version 7.23)
-[ 2.135350] msgmni has been set to 469
-[ 2.135656] io scheduler noop registered
-[ 2.135718] io scheduler cfq registered (default)
-[ 2.136286] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.136300] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.136311] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.136324] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.136335] pci_bus 0000:00: scanning bus
-[ 2.136346] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.136360] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.136375] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.136416] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.136429] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.136440] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.136452] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.136463] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.136474] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.136486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.136527] pci_bus 0000:00: fixups for bus
-[ 2.136536] pci_bus 0000:00: bus scan returning with max=00
-[ 2.136548] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.136569] pci 0000:00:00.0: fixup irq: got 33
-[ 2.136578] pci 0000:00:00.0: assigning IRQ 33
-[ 2.136589] pci 0000:00:01.0: fixup irq: got 34
-[ 2.136598] pci 0000:00:01.0: assigning IRQ 34
-[ 2.136609] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.136623] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.136636] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.136650] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.136662] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.136674] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.136686] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.136698] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.137491] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.137826] ata_piix 0000:00:01.0: version 2.13
-[ 2.137837] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.137864] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.138204] scsi0 : ata_piix
-[ 2.138329] scsi1 : ata_piix
-[ 2.138380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.138393] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.138543] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.138556] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.138573] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.138585] e1000 0000:00:00.0: enabling bus mastering
-[ 2.280852] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.280862] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.280892] ata1.00: configured for UDMA/33
-[ 2.280951] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.281082] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.281116] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.281160] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.281170] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.281192] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.281337] sda: sda1
-[ 2.281470] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.401164] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.401177] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.401211] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.401224] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.401253] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.401268] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.401414] usbcore: registered new interface driver usb-storage
-[ 2.401486] mousedev: PS/2 mouse device common for all mice
-[ 2.401677] usbcore: registered new interface driver usbhid
-[ 2.401687] usbhid: USB HID core driver
-[ 2.401726] TCP: cubic registered
-[ 2.401734] NET: Registered protocol family 17
- -[ 2.402215] devtmpfs: mounted
-[ 2.402270] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000029] Console: colour dummy device 80x25
+[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000033] pid_max: default: 32768 minimum: 301
+[ 0.000047] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000190] hw perfevents: no hardware support available
+[ 0.060052] CPU1: Booted secondary processor
+[ 1.080092] CPU2: failed to come online
+[ 2.100178] CPU3: failed to come online
+[ 2.100181] Brought up 2 CPUs
+[ 2.100182] SMP: Total of 2 processors activated.
+[ 2.100254] devtmpfs: initialized
+[ 2.100899] atomic64_test: passed
+[ 2.100953] regulator-dummy: no parameters
+[ 2.101395] NET: Registered protocol family 16
+[ 2.101565] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101572] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.102371] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.102374] Serial: AMBA PL011 UART driver
+[ 2.102603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.102648] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.103226] console [ttyAMA0] enabled
+[ 2.103397] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.103474] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.103550] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.103618] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.130484] 3V3: 3300 mV
+[ 2.130542] vgaarb: loaded
+[ 2.130598] SCSI subsystem initialized
+[ 2.130640] libata version 3.00 loaded.
+[ 2.130696] usbcore: registered new interface driver usbfs
+[ 2.130716] usbcore: registered new interface driver hub
+[ 2.130745] usbcore: registered new device driver usb
+[ 2.130775] pps_core: LinuxPPS API ver. 1 registered
+[ 2.130785] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.130805] PTP clock support registered
+[ 2.130963] Switched to clocksource arch_sys_counter
+[ 2.132610] NET: Registered protocol family 2
+[ 2.132708] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.132728] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.132748] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.132775] TCP: reno registered
+[ 2.132782] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132796] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132838] NET: Registered protocol family 1
+[ 2.132904] RPC: Registered named UNIX socket transport module.
+[ 2.132915] RPC: Registered udp transport module.
+[ 2.132923] RPC: Registered tcp transport module.
+[ 2.132932] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.132945] PCI: CLS 0 bytes, default 64
+[ 2.133141] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.133256] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.135328] fuse init (API version 7.23)
+[ 2.135440] msgmni has been set to 469
+[ 2.135797] io scheduler noop registered
+[ 2.135862] io scheduler cfq registered (default)
+[ 2.136433] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.136447] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.136458] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.136472] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.136482] pci_bus 0000:00: scanning bus
+[ 2.136494] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.136508] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.136523] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.136564] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.136577] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.136588] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.136600] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.136611] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.136622] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.136634] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.136675] pci_bus 0000:00: fixups for bus
+[ 2.136684] pci_bus 0000:00: bus scan returning with max=00
+[ 2.136697] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.136718] pci 0000:00:00.0: fixup irq: got 33
+[ 2.136727] pci 0000:00:00.0: assigning IRQ 33
+[ 2.136739] pci 0000:00:01.0: fixup irq: got 34
+[ 2.136748] pci 0000:00:01.0: assigning IRQ 34
+[ 2.136760] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.136773] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.136787] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.136801] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.136813] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.136825] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.136837] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.136849] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.137426] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.137740] ata_piix 0000:00:01.0: version 2.13
+[ 2.137750] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.137778] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.138110] scsi0 : ata_piix
+[ 2.138200] scsi1 : ata_piix
+[ 2.138235] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.138247] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.138381] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.138393] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.138410] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.138423] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290984] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290994] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.291024] ata1.00: configured for UDMA/33
+[ 2.291083] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.291212] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.291226] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.291255] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.291265] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.291288] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.291434] sda: sda1
+[ 2.291570] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.411274] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.411288] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.411313] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.411324] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.411348] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.411360] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.411448] usbcore: registered new interface driver usb-storage
+[ 2.411534] mousedev: PS/2 mouse device common for all mice
+[ 2.411744] usbcore: registered new interface driver usbhid
+[ 2.411754] usbhid: USB HID core driver
+[ 2.411794] TCP: cubic registered
+[ 2.411802] NET: Registered protocol family 17
+ +[ 2.412341] devtmpfs: mounted
+[ 2.412395] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.442337] udevd[608]: starting version 182
+[ 2.452586] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.533997] random: dd urandom read with 18 bits of entropy available
+[ 2.534161] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.671053] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.671190] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini index ebadfb41e..d16508053 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -153,7 +153,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -250,7 +250,7 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -310,7 +310,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -382,7 +382,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -499,7 +499,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -544,7 +544,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -556,7 +556,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -588,29 +588,36 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -630,6 +637,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -639,7 +647,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -661,9 +669,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1016,7 +1024,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1329,10 +1337,11 @@ pio=system.iobus.master[21] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain -conf_table_reported=true +conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1340,7 +1349,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -1571,6 +1580,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1578,7 +1588,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout index ad2b5e63e..b93a4d4b7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:07:38 -gem5 executing on e108600-lin, pid 24412 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:50:54 +gem5 executing on e108600-lin, pid 17458 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing Selected 64-bit ARM architecture, updating default disk image... @@ -15,4 +15,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51759347706500 because m5_exit instruction encountered +Exiting @ tick 51821888787500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index db63d86a7..39817260d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.820895 # Number of seconds simulated -sim_ticks 51820894502500 # Number of ticks simulated -final_tick 51820894502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821889 # Number of seconds simulated +sim_ticks 51821888787500 # Number of ticks simulated +final_tick 51821888787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 612269 # Simulator instruction rate (inst/s) -host_op_rate 719485 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35448799247 # Simulator tick rate (ticks/s) -host_mem_usage 680056 # Number of bytes of host memory used -host_seconds 1461.85 # Real time elapsed on the host -sim_insts 895045967 # Number of instructions simulated -sim_ops 1051780871 # Number of ops (including micro ops) simulated +host_inst_rate 515124 # Simulator instruction rate (inst/s) +host_op_rate 605315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31054928912 # Simulator tick rate (ticks/s) +host_mem_usage 676612 # Number of bytes of host memory used +host_seconds 1668.72 # Real time elapsed on the host +sim_insts 859596485 # Number of instructions simulated +sim_ops 1010098639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 268032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 256704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5200500 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 51306824 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 409600 # Number of bytes read from this memory -system.physmem.bytes_read::total 57441660 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5200500 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5200500 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78712256 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 216448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 219200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5035380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 42867656 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 394432 # Number of bytes read from this memory +system.physmem.bytes_read::total 48733116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5035380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5035380 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69868992 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 78732836 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4011 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 121665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 801682 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6400 # Number of read requests responded to by this memory -system.physmem.num_reads::total 937946 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1229879 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69889572 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3382 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3425 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 119085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 669820 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 801875 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1091703 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1232452 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 100355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 990080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1108465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 100355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1518929 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1094276 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 97167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 827211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 940396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 97167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 97167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1348253 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1519326 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1518929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 100355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 990477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2627791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 937946 # Number of read requests accepted -system.physmem.writeReqs 1232452 # Number of write requests accepted -system.physmem.readBursts 937946 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1232452 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59993856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 34688 # Total number of bytes read from write queue -system.physmem.bytesWritten 78731584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 57441660 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78732836 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 542 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1348650 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1348253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 97167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 827609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2289046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 801875 # Number of read requests accepted +system.physmem.writeReqs 1094276 # Number of write requests accepted +system.physmem.readBursts 801875 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1094276 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 51277952 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 42048 # Total number of bytes read from write queue +system.physmem.bytesWritten 69886912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 48733116 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 69889572 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 657 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2265 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 58989 # Per bank write bursts -system.physmem.perBankRdBursts::1 58919 # Per bank write bursts -system.physmem.perBankRdBursts::2 58679 # Per bank write bursts -system.physmem.perBankRdBursts::3 55735 # Per bank write bursts -system.physmem.perBankRdBursts::4 54249 # Per bank write bursts -system.physmem.perBankRdBursts::5 59544 # Per bank write bursts -system.physmem.perBankRdBursts::6 52586 # Per bank write bursts -system.physmem.perBankRdBursts::7 53926 # Per bank write bursts -system.physmem.perBankRdBursts::8 52975 # Per bank write bursts -system.physmem.perBankRdBursts::9 101116 # Per bank write bursts -system.physmem.perBankRdBursts::10 56481 # Per bank write bursts -system.physmem.perBankRdBursts::11 59298 # Per bank write bursts -system.physmem.perBankRdBursts::12 53072 # Per bank write bursts -system.physmem.perBankRdBursts::13 58564 # Per bank write bursts -system.physmem.perBankRdBursts::14 50527 # Per bank write bursts -system.physmem.perBankRdBursts::15 52744 # Per bank write bursts -system.physmem.perBankWrBursts::0 76908 # Per bank write bursts -system.physmem.perBankWrBursts::1 78477 # Per bank write bursts -system.physmem.perBankWrBursts::2 80133 # Per bank write bursts -system.physmem.perBankWrBursts::3 78953 # Per bank write bursts -system.physmem.perBankWrBursts::4 75778 # Per bank write bursts -system.physmem.perBankWrBursts::5 80212 # Per bank write bursts -system.physmem.perBankWrBursts::6 72590 # Per bank write bursts -system.physmem.perBankWrBursts::7 74527 # Per bank write bursts -system.physmem.perBankWrBursts::8 74121 # Per bank write bursts -system.physmem.perBankWrBursts::9 79665 # Per bank write bursts -system.physmem.perBankWrBursts::10 76241 # Per bank write bursts -system.physmem.perBankWrBursts::11 79585 # Per bank write bursts -system.physmem.perBankWrBursts::12 74881 # Per bank write bursts -system.physmem.perBankWrBursts::13 79432 # Per bank write bursts -system.physmem.perBankWrBursts::14 73606 # Per bank write bursts -system.physmem.perBankWrBursts::15 75072 # Per bank write bursts +system.physmem.perBankRdBursts::0 50164 # Per bank write bursts +system.physmem.perBankRdBursts::1 52640 # Per bank write bursts +system.physmem.perBankRdBursts::2 46199 # Per bank write bursts +system.physmem.perBankRdBursts::3 47700 # Per bank write bursts +system.physmem.perBankRdBursts::4 47678 # Per bank write bursts +system.physmem.perBankRdBursts::5 54947 # Per bank write bursts +system.physmem.perBankRdBursts::6 45482 # Per bank write bursts +system.physmem.perBankRdBursts::7 44174 # Per bank write bursts +system.physmem.perBankRdBursts::8 47146 # Per bank write bursts +system.physmem.perBankRdBursts::9 89983 # Per bank write bursts +system.physmem.perBankRdBursts::10 47048 # Per bank write bursts +system.physmem.perBankRdBursts::11 49101 # Per bank write bursts +system.physmem.perBankRdBursts::12 43837 # Per bank write bursts +system.physmem.perBankRdBursts::13 45399 # Per bank write bursts +system.physmem.perBankRdBursts::14 43891 # Per bank write bursts +system.physmem.perBankRdBursts::15 45829 # Per bank write bursts +system.physmem.perBankWrBursts::0 68109 # Per bank write bursts +system.physmem.perBankWrBursts::1 72083 # Per bank write bursts +system.physmem.perBankWrBursts::2 69263 # Per bank write bursts +system.physmem.perBankWrBursts::3 69948 # Per bank write bursts +system.physmem.perBankWrBursts::4 67942 # Per bank write bursts +system.physmem.perBankWrBursts::5 73995 # Per bank write bursts +system.physmem.perBankWrBursts::6 66206 # Per bank write bursts +system.physmem.perBankWrBursts::7 65273 # Per bank write bursts +system.physmem.perBankWrBursts::8 68509 # Per bank write bursts +system.physmem.perBankWrBursts::9 70672 # Per bank write bursts +system.physmem.perBankWrBursts::10 68078 # Per bank write bursts +system.physmem.perBankWrBursts::11 68626 # Per bank write bursts +system.physmem.perBankWrBursts::12 64922 # Per bank write bursts +system.physmem.perBankWrBursts::13 66812 # Per bank write bursts +system.physmem.perBankWrBursts::14 65438 # Per bank write bursts +system.physmem.perBankWrBursts::15 66107 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 41 # Number of times write queue was full causing retry -system.physmem.totGap 51820891581500 # Total gap between requests +system.physmem.numWrRetry 528 # Number of times write queue was full causing retry +system.physmem.totGap 51821885925500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 894830 # Read request sizes (log2) +system.physmem.readPktSize::6 758759 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1229879 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 903506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1091703 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 767795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,154 +160,185 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 67316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 70490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 74148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 71564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 70236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 72767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 75611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 72543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 77682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 70723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 68261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 67880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 67043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 563432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.214486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 148.153142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.290760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 250076 44.38% 44.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 147098 26.11% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49891 8.85% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26994 4.79% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18337 3.25% 87.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11939 2.12% 89.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8931 1.59% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7653 1.36% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 42513 7.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 563432 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 66023 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.197810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 125.335088 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 66020 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 30627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 64549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 63213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 64819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 67440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 65819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 58775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1157 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 494449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.049629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.402723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 288.016754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 219085 44.31% 44.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 131738 26.64% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 43693 8.84% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22796 4.61% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15362 3.11% 87.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9595 1.94% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7428 1.50% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5929 1.20% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 38823 7.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 494449 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 57195 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.008130 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 134.294281 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 57192 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 66023 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 66023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.632613 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.082710 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.894597 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 62853 95.20% 95.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 1132 1.71% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1165 1.76% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 145 0.22% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 61 0.09% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 50 0.08% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 451 0.68% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 71 0.11% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 27 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 4 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 11 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 20 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 9 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 66023 # Writes before turning the bus around for reads -system.physmem.totQLat 12434281516 # Total ticks spent queuing -system.physmem.totMemAccLat 30010606516 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4687020000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13264.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 57195 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 57195 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.092281 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.359425 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.356307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 44576 77.94% 77.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9441 16.51% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 730 1.28% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 284 0.50% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 871 1.52% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 293 0.51% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 48 0.08% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 36 0.06% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 15 0.03% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.03% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 14 0.02% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 33 0.06% 98.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 518 0.91% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 69 0.12% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 50 0.09% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 58 0.10% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 36 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.01% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 17 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 20 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 11 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 57195 # Writes before turning the bus around for reads +system.physmem.totQLat 29399013585 # Total ticks spent queuing +system.physmem.totMemAccLat 44421851085 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4006090000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36692.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32014.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 55442.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing -system.physmem.readRowHits 702833 # Number of row buffer hits during reads -system.physmem.writeRowHits 901319 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.27 # Row buffer hit rate for writes -system.physmem.avgGap 23876216.06 # Average gap between requests -system.physmem.pageHitRate 74.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2165373000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1181503125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3530451600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4001905440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384688532160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1300349435715 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29951875881000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34647793082040 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.606693 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49827060150280 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730413360000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 263420580720 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2094172920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1142653875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3781260600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3969667440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384688532160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1299689474040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29952454794750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34647820555785 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.607223 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49827979372630 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730413360000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 262496082370 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing +system.physmem.readRowHits 600273 # Number of row buffer hits during reads +system.physmem.writeRowHits 798478 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.92 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.12 # Row buffer hit rate for writes +system.physmem.avgGap 27330041.71 # Average gap between requests +system.physmem.pageHitRate 73.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1812881700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 963565680 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2777345760 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2885715180 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 48801801360.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 38319920670 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3025839840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 94040362440 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 72590911200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12330316288695 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12595556394525 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.054753 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51729925726993 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5744734750 # Time in different power states +system.physmem_0.memoryStateTime::REF 20754236000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51334657894500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 189038733198 # Time in different power states +system.physmem_0.memoryStateTime::ACT 65464048007 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 206229141045 # Time in different power states +system.physmem_1.actEnergy 1717491300 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 912868275 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2943350760 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2814436080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 46544843280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 38176673400 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2758502400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 87988375470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 69794301120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12334956932460 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12588629106345 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.921078 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51730316233255 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5091528742 # Time in different power states +system.physmem_1.memoryStateTime::REF 19793960000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51356223942250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 181755962683 # Time in different power states +system.physmem_1.memoryStateTime::ACT 66066776003 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 192956617822 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -324,9 +355,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -334,7 +365,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -364,69 +395,74 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 214264 # Table walker walks requested -system.cpu.dtb.walker.walksLong 214264 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17030 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 164948 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 21 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 214243 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.140028 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 46.737844 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 214241 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 195978 # Table walker walks requested +system.cpu.dtb.walker.walksLong 195978 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13491 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152311 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 195958 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.153094 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 48.869782 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 195956 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 214243 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 181999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24181.814186 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20419.578200 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15522.698406 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 180089 98.95% 98.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 1633 0.90% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 118 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 77 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 52 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 181999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 4819875556 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 1.150179 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -723841796 -15.02% -15.02% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 5543717352 115.02% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 4819875556 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 164949 90.64% 90.64% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 17030 9.36% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 181979 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 214264 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::total 195958 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 165822 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23748.733582 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 19720.854851 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 19654.042010 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 164137 98.98% 98.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1390 0.84% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 75 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 54 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 79 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 19 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 53 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 165822 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -2782551036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.846086 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.360866 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -428273296 15.39% 15.39% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -2354277740 84.61% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -2782551036 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 152312 91.86% 91.86% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 13491 8.14% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 165803 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 195978 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 214264 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 181979 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 195978 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 165803 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 181979 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 396243 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 165803 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 361781 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168009449 # DTB read hits -system.cpu.dtb.read_misses 157878 # DTB read misses -system.cpu.dtb.write_hits 152852610 # DTB write hits -system.cpu.dtb.write_misses 56386 # DTB write misses +system.cpu.dtb.read_hits 161602593 # DTB read hits +system.cpu.dtb.read_misses 145506 # DTB read misses +system.cpu.dtb.write_hits 146806893 # DTB write hits +system.cpu.dtb.write_misses 50472 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 43022 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 75936 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72949 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 8201 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 7287 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 168167327 # DTB read accesses -system.cpu.dtb.write_accesses 152908996 # DTB write accesses +system.cpu.dtb.perms_faults 19275 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 161748099 # DTB read accesses +system.cpu.dtb.write_accesses 146857365 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320862059 # DTB hits -system.cpu.dtb.misses 214264 # DTB misses -system.cpu.dtb.accesses 321076323 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 308409486 # DTB hits +system.cpu.dtb.misses 195978 # DTB misses +system.cpu.dtb.accesses 308605464 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -456,674 +492,671 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 122945 # Table walker walks requested -system.cpu.itb.walker.walksLong 122945 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 120718 # Table walker walks requested +system.cpu.itb.walker.walksLong 120718 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 110624 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 122945 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 122945 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 122945 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 111743 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27331.219853 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23493.082733 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 18310.002732 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 109587 98.07% 98.07% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1865 1.67% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 133 0.12% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 84 0.08% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 40 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 22 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 111743 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -850328296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -850328296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -850328296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 110624 99.00% 99.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1119 1.00% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 111743 # Table walker page sizes translated +system.cpu.itb.walker.walksLongTerminationLevel::Level3 108838 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 120718 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 120718 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 120718 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 109957 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27485.576180 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23297.926209 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24382.701456 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 107960 98.18% 98.18% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1664 1.51% 99.70% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 68 0.06% 99.76% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 86 0.08% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 74 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 23 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 5 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 76 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 109957 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -556629296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -556629296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -556629296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 108838 98.98% 98.98% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1119 1.02% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 109957 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122945 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 122945 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120718 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 120718 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111743 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 111743 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 234688 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 895597591 # ITB inst hits -system.cpu.itb.inst_misses 122945 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 109957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 230675 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 860126625 # ITB inst hits +system.cpu.itb.inst_misses 120718 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 43022 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53957 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 52157 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 895720536 # ITB inst accesses -system.cpu.itb.hits 895597591 # DTB hits -system.cpu.itb.misses 122945 # DTB misses -system.cpu.itb.accesses 895720536 # DTB accesses -system.cpu.numPwrStateTransitions 32698 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16349 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3072754762.549147 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59826711358.002258 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7060 43.18% 43.18% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9253 56.60% 99.78% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 6 0.04% 99.82% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 860247343 # ITB inst accesses +system.cpu.itb.hits 860126625 # DTB hits +system.cpu.itb.misses 120718 # DTB misses +system.cpu.itb.accesses 860247343 # DTB accesses +system.cpu.numPwrStateTransitions 32322 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16161 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3111677574.020791 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60407510991.245888 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 6870 42.51% 42.51% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9256 57.27% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988775178432 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16349 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1584426889584 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50236467612916 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103641789005 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16161 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1534067513750 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50287821273750 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 103643777575 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16349 # number of quiesce instructions executed -system.cpu.committedInsts 895045967 # Number of instructions committed -system.cpu.committedOps 1051780871 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 965574423 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 894989 # Number of float alu accesses -system.cpu.num_func_calls 52935800 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 136802593 # number of instructions that are conditional controls -system.cpu.num_int_insts 965574423 # number of integer instructions -system.cpu.num_fp_insts 894989 # number of float instructions -system.cpu.num_int_register_reads 1409614532 # number of times the integer registers were read -system.cpu.num_int_register_writes 766141547 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1442074 # number of times the floating registers were read -system.cpu.num_fp_register_writes 760100 # number of times the floating registers were written -system.cpu.num_cc_register_reads 235678872 # number of times the CC registers were read -system.cpu.num_cc_register_writes 235085086 # number of times the CC registers were written -system.cpu.num_mem_refs 320845878 # number of memory refs -system.cpu.num_load_insts 168002679 # Number of load instructions -system.cpu.num_store_insts 152843199 # Number of store instructions -system.cpu.num_idle_cycles 100472935225.830063 # Number of idle cycles -system.cpu.num_busy_cycles 3168853779.169939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030575 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969425 # Percentage of idle cycles -system.cpu.Branches 199903261 # Number of branches fetched +system.cpu.kern.inst.quiesce 16161 # number of quiesce instructions executed +system.cpu.committedInsts 859596485 # Number of instructions committed +system.cpu.committedOps 1010098639 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 927989339 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 896850 # Number of float alu accesses +system.cpu.num_func_calls 51273640 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 130821573 # number of instructions that are conditional controls +system.cpu.num_int_insts 927989339 # number of integer instructions +system.cpu.num_fp_insts 896850 # number of float instructions +system.cpu.num_int_register_reads 1348541336 # number of times the integer registers were read +system.cpu.num_int_register_writes 735865236 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1446705 # number of times the floating registers were read +system.cpu.num_fp_register_writes 758956 # number of times the floating registers were written +system.cpu.num_cc_register_reads 224361660 # number of times the CC registers were read +system.cpu.num_cc_register_writes 223761478 # number of times the CC registers were written +system.cpu.num_mem_refs 308390268 # number of memory refs +system.cpu.num_load_insts 161593947 # Number of load instructions +system.cpu.num_store_insts 146796321 # Number of store instructions +system.cpu.num_idle_cycles 100575642547.498062 # Number of idle cycles +system.cpu.num_busy_cycles 3068135027.501941 # Number of busy cycles +system.cpu.not_idle_fraction 0.029603 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970397 # Percentage of idle cycles +system.cpu.Branches 191892206 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 729096517 69.28% 69.28% # Class of executed instruction -system.cpu.op_class::IntMult 2224980 0.21% 69.49% # Class of executed instruction -system.cpu.op_class::IntDiv 97778 0.01% 69.50% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.51% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu.op_class::MemRead 168002679 15.96% 85.48% # Class of executed instruction -system.cpu.op_class::MemWrite 152843199 14.52% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 699904687 69.25% 69.25% # Class of executed instruction +system.cpu.op_class::IntMult 2167959 0.21% 69.47% # Class of executed instruction +system.cpu.op_class::IntDiv 97409 0.01% 69.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 111537 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::MemRead 161593947 15.99% 85.48% # Class of executed instruction +system.cpu.op_class::MemWrite 146796321 14.52% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1052375619 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 10244350 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.965651 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 310416272 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10244862 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.299703 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3504161500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.965651 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy +system.cpu.op_class::total 1010671903 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9712865 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.962733 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 298498000 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9713377 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.730610 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3801165500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.962733 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999927 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1293353364 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1293353364 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 156944978 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 156944978 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 145025968 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 145025968 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395817 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395817 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335163 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335163 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3689072 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3689072 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3994801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3994801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 302306109 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 302306109 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 302701926 # number of overall hits -system.cpu.dcache.overall_hits::total 302701926 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5326710 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5326710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2212553 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2212553 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1311764 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1311764 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1232866 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1232866 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 307422 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 307422 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8772129 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8772129 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10083893 # number of overall misses -system.cpu.dcache.overall_misses::total 10083893 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84631439000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84631439000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66820707500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66820707500 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 25293878500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 25293878500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4522600000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4522600000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 197000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 197000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 176746025000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 176746025000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 176746025000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 176746025000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162271688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162271688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147238521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147238521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707581 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1707581 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1568029 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1568029 # 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miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015027 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.768200 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.768200 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786252 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786252 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076923 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076923 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1243014374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1243014374 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 151150245 # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587246 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1587246 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559381 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1559381 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3768387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766720 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3766720 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 299202891 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 299202891 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 300790137 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300790137 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032411 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032411 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014638 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014638 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758475 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758475 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786304 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786304 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077690 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077690 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.028199 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.028199 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032239 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032239 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15888.125879 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15888.125879 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30200.726265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30200.726265 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20516.324159 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20516.324159 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14711.373942 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14711.373942 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 65666.666667 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 65666.666667 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20148.589356 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20148.589356 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17527.558553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17527.558553 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.027939 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.027939 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031794 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031794 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17080.496873 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17080.496873 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30928.948857 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30928.948857 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20360.760985 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20360.760985 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15238.501870 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15238.501870 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20991.229024 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20991.229024 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18348.717427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18348.717427 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7906430 # number of writebacks -system.cpu.dcache.writebacks::total 7906430 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21920 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21920 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21246 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21246 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70972 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70972 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 43166 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 43166 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 43166 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 43166 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5304790 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5304790 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2191307 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2191307 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1309953 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1309953 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1232866 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1232866 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 236450 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 236450 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8728963 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8728963 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 10038916 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 10038916 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7498102 # number of writebacks +system.cpu.dcache.writebacks::total 7498102 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21612 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21612 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21289 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21289 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70591 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70591 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 42901 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 42901 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 42901 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 42901 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5041417 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5041417 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2048924 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2048924 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203533 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1203533 # 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number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78748278500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 78748278500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63964841000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 63964841000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21083631000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21083631000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 24061012500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 24061012500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3160913500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3160913500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 194000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166774132000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 166774132000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187857763000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187857763000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6233075000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6233075000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6233075000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6233075000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032691 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032691 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014883 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014883 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.767140 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.767140 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786252 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786252 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059164 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80551413000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 80551413000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61232027000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61232027000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21569596000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21569596000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23739139000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23739139000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3061958500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3061958500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165522579000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165522579000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187092175000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187092175000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014487 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014487 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758252 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758252 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786304 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786304 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058957 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058957 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028060 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028060 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032095 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032095 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14844.749462 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14844.749462 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29190.269095 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29190.269095 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16094.952262 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16094.952262 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19516.324159 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19516.324159 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13368.211038 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13368.211038 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 64666.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19105.835596 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19105.835596 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18712.952972 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18712.952972 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184924.790838 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184924.790838 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92456.909339 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92456.909339 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13792548 # number of replacements -system.cpu.icache.tags.tagsinuse 511.891104 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 881804526 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13793060 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63.931030 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31603903500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.891104 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999787 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031650 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031650 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15977.931006 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15977.931006 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29884.967427 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29884.967427 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17921.898278 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17921.898278 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19360.760985 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19360.760985 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13781.803901 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13781.803901 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.942083 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.942083 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.496040 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.496040 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.352816 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.352816 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.690519 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.690519 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 13489644 # number of replacements +system.cpu.icache.tags.tagsinuse 511.886684 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 846636464 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13490156 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62.759576 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 32464202500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.886684 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999779 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999779 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 909390656 # Number of tag accesses -system.cpu.icache.tags.data_accesses 909390656 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 881804526 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 881804526 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 881804526 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 881804526 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 881804526 # number of overall hits -system.cpu.icache.overall_hits::total 881804526 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13793065 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13793065 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13793065 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13793065 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13793065 # number of overall misses -system.cpu.icache.overall_misses::total 13793065 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 185289814000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 185289814000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 185289814000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 185289814000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 185289814000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 185289814000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 895597591 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 895597591 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 895597591 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 895597591 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 895597591 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 895597591 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015401 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015401 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015401 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015401 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015401 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015401 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13433.548961 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13433.548961 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13433.548961 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13433.548961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13433.548961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13433.548961 # average overall miss latency +system.cpu.icache.tags.tag_accesses 873616786 # Number of tag accesses +system.cpu.icache.tags.data_accesses 873616786 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 846636464 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 846636464 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 846636464 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 846636464 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 846636464 # number of overall hits +system.cpu.icache.overall_hits::total 846636464 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13490161 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13490161 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13490161 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13490161 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13490161 # number of overall misses +system.cpu.icache.overall_misses::total 13490161 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 183617881000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 183617881000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 183617881000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 183617881000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 183617881000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 183617881000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 860126625 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 860126625 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 860126625 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 860126625 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 860126625 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 860126625 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015684 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015684 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015684 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015684 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015684 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015684 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13611.244595 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13611.244595 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13611.244595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13611.244595 # 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number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9012030 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 23398883 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011781 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016831 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013808 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.129833 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.129833 # miss rate for UpgradeReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170127720000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170127720000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170127720000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170127720000 # 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average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1158676 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65394.159072 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 44435371 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1220446 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 36.409125 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6958052500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 10890.998401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 465.362855 # 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mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039607 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.405254 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.405254 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.033474 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079060 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.033474 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 119428.235640 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19040.005048 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19040.005048 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88532.387800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88532.387800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 105441.333211 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 105441.333211 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107862.107316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107862.107316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18663.276991 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18663.276991 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95911.082542 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97084.261549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95911.082542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97084.261549 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.380822 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.687184 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.076065 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.215576 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 46934872 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23731321 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2030 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2030 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1965 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1965 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1068832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21713957 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1010835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20969000 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9029679 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13792548 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2522886 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 30473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 30476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2160837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2160837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13793065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6853863 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1261524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1232866 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41464928 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30930790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 605749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 980040 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 73981507 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1765651732 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1083027398 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1906472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2843832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2853429434 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1738629 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 75129128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 26510522 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.020074 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.140252 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8483175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13489644 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2388366 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 28800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 28802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2020127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2020127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13490161 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6470086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1256693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226147 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40556216 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592159 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 883944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 71365293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726880020 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023309382 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1851200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2485592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2754526194 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1584975 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66236232 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 25469090 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019778 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.139236 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 25978363 97.99% 97.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 532159 2.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24965367 98.02% 98.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 503723 1.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 26510522 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 46319770000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25469090 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 44744307000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1608386 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1625890 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20732722500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20278366500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14200291468 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13408934951 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 367440000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 360759000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 624561000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 573245000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40312 # Transaction distribution -system.iobus.trans_dist::ReadResp 40312 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40346 # Transaction distribution +system.iobus.trans_dist::ReadResp 40346 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1298,11 +1329,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230982 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230982 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353766 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1317,16 +1348,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334360 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492552 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1344,75 +1375,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25722000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25714500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38610500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38601500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568931558 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569287162 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147742000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147810000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115472 # number of replacements -system.iocache.tags.tagsinuse 10.457340 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115506 # number of replacements +system.iocache.tags.tagsinuse 10.457104 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153794616000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511175 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946165 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219448 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434135 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13154766855000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510739 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946366 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219421 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434148 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653569 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039776 # Number of tag accesses -system.iocache.tags.data_accesses 1039776 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040082 # Number of tag accesses +system.iocache.tags.data_accesses 1040082 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8827 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8864 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8898 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115491 # number of demand (read+write) misses -system.iocache.demand_misses::total 115531 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115525 # number of demand (read+write) misses +system.iocache.demand_misses::total 115565 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115491 # number of overall misses -system.iocache.overall_misses::total 115531 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1606262152 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1611348152 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115525 # number of overall misses +system.iocache.overall_misses::total 115565 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2019214145 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2024300645 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12771737406 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12771737406 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14377999558 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14383436558 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14377999558 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14383436558 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13409527517 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13409527517 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15428741662 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15434179162 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15428741662 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15434179162 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8827 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8864 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8898 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115491 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115531 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115525 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115565 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115491 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115531 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115525 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115565 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1426,53 +1457,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 181971.468449 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 181785.666968 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 227876.554001 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 227500.634412 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119738.031632 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119738.031632 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124494.545532 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124498.503068 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124494.545532 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124498.503068 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31144 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125717.463408 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125717.463408 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 133554.096500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 133554.096500 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51750 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3368 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3356 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.247031 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.420143 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8827 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8864 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8861 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8898 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115491 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115531 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115525 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115565 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115491 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115531 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1164912152 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1168148152 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115525 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115565 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1576164145 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1579400645 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7431704095 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7431704095 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8596616247 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8600053247 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8596616247 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8600053247 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8069228353 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8069228353 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9645392498 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9648829998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9645392498 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9648829998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1486,95 +1517,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131971.468449 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 131785.666968 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177876.554001 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 177500.634412 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69673.967740 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69673.967740 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74435.378055 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74439.356078 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74435.378055 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74439.356078 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 2941993 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1455813 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3308 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75650.907082 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75650.907082 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 2643885 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1308749 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3600 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76831 # Transaction distribution -system.membus.trans_dist::ReadResp 451336 # Transaction distribution +system.membus.trans_dist::ReadResp 424674 # Transaction distribution system.membus.trans_dist::WriteReq 33710 # Transaction distribution system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1229879 # Transaction distribution -system.membus.trans_dist::CleanEvict 192681 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4527 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1091703 # Transaction distribution +system.membus.trans_dist::CleanEvict 181416 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 523443 # Transaction distribution -system.membus.trans_dist::ReadExResp 523443 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 374505 # Transaction distribution -system.membus.trans_dist::InvalidateReq 616914 # Transaction distribution +system.membus.trans_dist::ReadExReq 414305 # Transaction distribution +system.membus.trans_dist::ReadExResp 414305 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 347843 # Transaction distribution +system.membus.trans_dist::InvalidateReq 603558 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3690757 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3820461 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4057864 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256260 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237234 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237234 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3623198 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 128940576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 129110426 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7233920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 136344346 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3126 # Total snoops (count) -system.membus.snoopTraffic 199552 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1629933 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019638 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.138754 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111403936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111573786 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7218752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7218752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 118792538 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3397 # Total snoops (count) +system.membus.snoopTraffic 216896 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1480779 # Request fanout histogram +system.membus.snoop_fanout::mean 0.023089 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.150185 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1597924 98.04% 98.04% # Request fanout histogram -system.membus.snoop_fanout::1 32009 1.96% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1446590 97.69% 97.69% # Request fanout histogram +system.membus.snoop_fanout::1 34189 2.31% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1629933 # Request fanout histogram -system.membus.reqLayer0.occupancy 106906500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1480779 # Request fanout histogram +system.membus.reqLayer0.occupancy 106893000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5804000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5820500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8036011189 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7180364209 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4923968289 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4203282304 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44661763 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44877398 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1617,28 +1648,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal index 0cb0b7645..42937e8d5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000044] Console: colour dummy device 80x25
-[ 0.000048] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000050] pid_max: default: 32768 minimum: 301
-[ 0.000073] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000075] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000316] hw perfevents: no hardware support available
-[ 1.060136] CPU1: failed to come online
-[ 2.080267] CPU2: failed to come online
-[ 3.100398] CPU3: failed to come online
-[ 3.100403] Brought up 1 CPUs
-[ 3.100405] SMP: Total of 1 processors activated.
-[ 3.100517] devtmpfs: initialized
-[ 3.101614] atomic64_test: passed
-[ 3.101697] regulator-dummy: no parameters
-[ 3.102519] NET: Registered protocol family 16
-[ 3.102798] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.102809] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.104232] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.104240] Serial: AMBA PL011 UART driver
-[ 3.104622] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.104693] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.105277] console [ttyAMA0] enabled
-[ 3.105422] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.105471] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.105522] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.105568] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130937] 3V3: 3300 mV
-[ 3.131019] vgaarb: loaded
-[ 3.131116] SCSI subsystem initialized
-[ 3.131186] libata version 3.00 loaded.
-[ 3.131272] usbcore: registered new interface driver usbfs
-[ 3.131299] usbcore: registered new interface driver hub
-[ 3.131354] usbcore: registered new device driver usb
-[ 3.131399] pps_core: LinuxPPS API ver. 1 registered
-[ 3.131409] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131433] PTP clock support registered
-[ 3.131670] Switched to clocksource arch_sys_counter
-[ 3.133769] NET: Registered protocol family 2
-[ 3.133932] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.133964] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.134004] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.134042] TCP: reno registered
-[ 3.134050] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134070] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134144] NET: Registered protocol family 1
-[ 3.134216] RPC: Registered named UNIX socket transport module.
-[ 3.134227] RPC: Registered udp transport module.
-[ 3.134236] RPC: Registered tcp transport module.
-[ 3.134245] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.134259] PCI: CLS 0 bytes, default 64
-[ 3.134575] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.134796] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.138336] fuse init (API version 7.23)
-[ 3.138502] msgmni has been set to 469
-[ 3.143073] io scheduler noop registered
-[ 3.143173] io scheduler cfq registered (default)
-[ 3.144095] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.144109] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.144122] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.144136] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.144147] pci_bus 0000:00: scanning bus
-[ 3.144161] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.144177] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.144195] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.144258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.144272] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.144285] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.144297] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.144310] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.144322] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.144336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.144395] pci_bus 0000:00: fixups for bus
-[ 3.144405] pci_bus 0000:00: bus scan returning with max=00
-[ 3.144419] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.144446] pci 0000:00:00.0: fixup irq: got 33
-[ 3.144456] pci 0000:00:00.0: assigning IRQ 33
-[ 3.144470] pci 0000:00:01.0: fixup irq: got 34
-[ 3.144480] pci 0000:00:01.0: assigning IRQ 34
-[ 3.144494] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.144509] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.144524] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.144538] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.144552] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.144565] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.144578] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.144591] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.145478] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.146000] ata_piix 0000:00:01.0: version 2.13
-[ 3.146012] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.146049] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.146644] scsi0 : ata_piix
-[ 3.146827] scsi1 : ata_piix
-[ 3.146881] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.146894] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.147093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.147106] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.147129] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.147142] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301707] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301718] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301753] ata1.00: configured for UDMA/33
-[ 3.301838] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.302037] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.302073] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.302130] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.302141] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.302170] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.302373] sda: sda1
-[ 3.302577] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.422032] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.422047] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.422076] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.422087] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.422118] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.422131] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.422262] usbcore: registered new interface driver usb-storage
-[ 3.422357] mousedev: PS/2 mouse device common for all mice
-[ 3.422646] usbcore: registered new interface driver usbhid
-[ 3.422657] usbhid: USB HID core driver
-[ 3.422710] TCP: cubic registered
-[ 3.422720] NET: Registered protocol family 17
- -[ 3.423384] devtmpfs: mounted
-[ 3.423472] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000040] Console: colour dummy device 80x25
+[ 0.000043] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000046] pid_max: default: 32768 minimum: 301
+[ 0.000066] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000069] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000252] hw perfevents: no hardware support available
+[ 1.060135] CPU1: failed to come online
+[ 2.080266] CPU2: failed to come online
+[ 3.100397] CPU3: failed to come online
+[ 3.100402] Brought up 1 CPUs
+[ 3.100404] SMP: Total of 1 processors activated.
+[ 3.100503] devtmpfs: initialized
+[ 3.101571] atomic64_test: passed
+[ 3.101646] regulator-dummy: no parameters
+[ 3.102401] NET: Registered protocol family 16
+[ 3.102664] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.102675] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.103283] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.103290] Serial: AMBA PL011 UART driver
+[ 3.103646] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.103712] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.104302] console [ttyAMA0] enabled
+[ 3.104405] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.104456] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.104507] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.104554] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.131002] 3V3: 3300 mV
+[ 3.131076] vgaarb: loaded
+[ 3.131168] SCSI subsystem initialized
+[ 3.131239] libata version 3.00 loaded.
+[ 3.131320] usbcore: registered new interface driver usbfs
+[ 3.131346] usbcore: registered new interface driver hub
+[ 3.131401] usbcore: registered new device driver usb
+[ 3.131444] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131455] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131477] PTP clock support registered
+[ 3.131699] Switched to clocksource arch_sys_counter
+[ 3.133732] NET: Registered protocol family 2
+[ 3.133887] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.133915] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.133949] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.133976] TCP: reno registered
+[ 3.133984] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134003] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134067] NET: Registered protocol family 1
+[ 3.134134] RPC: Registered named UNIX socket transport module.
+[ 3.134145] RPC: Registered udp transport module.
+[ 3.134154] RPC: Registered tcp transport module.
+[ 3.134163] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.134177] PCI: CLS 0 bytes, default 64
+[ 3.134494] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.134701] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.138130] fuse init (API version 7.23)
+[ 3.138291] msgmni has been set to 469
+[ 3.142786] io scheduler noop registered
+[ 3.142885] io scheduler cfq registered (default)
+[ 3.143673] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.143688] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.143701] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.143715] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.143727] pci_bus 0000:00: scanning bus
+[ 3.143740] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.143755] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.143773] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.143833] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.143848] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.143860] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.143873] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.143886] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.143899] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.143912] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.143970] pci_bus 0000:00: fixups for bus
+[ 3.143980] pci_bus 0000:00: bus scan returning with max=00
+[ 3.143994] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.144020] pci 0000:00:00.0: fixup irq: got 33
+[ 3.144030] pci 0000:00:00.0: assigning IRQ 33
+[ 3.144044] pci 0000:00:01.0: fixup irq: got 34
+[ 3.144054] pci 0000:00:01.0: assigning IRQ 34
+[ 3.144070] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.144084] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.144099] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.144114] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.144127] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.144141] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.144154] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.144168] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.145036] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.145534] ata_piix 0000:00:01.0: version 2.13
+[ 3.145546] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.145577] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.146149] scsi0 : ata_piix
+[ 3.146327] scsi1 : ata_piix
+[ 3.146380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.146394] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.146583] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.146596] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.146618] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.146632] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301733] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301744] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301779] ata1.00: configured for UDMA/33
+[ 3.301852] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.302048] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.302084] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.302142] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.302153] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.302182] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.302382] sda: sda1
+[ 3.302584] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.422057] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.422072] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.422102] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.422113] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.422144] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.422157] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.422289] usbcore: registered new interface driver usb-storage
+[ 3.422380] mousedev: PS/2 mouse device common for all mice
+[ 3.422670] usbcore: registered new interface driver usbhid
+[ 3.422681] usbhid: USB HID core driver
+[ 3.422731] TCP: cubic registered
+[ 3.422741] NET: Registered protocol family 17
+ +[ 3.423377] devtmpfs: mounted
+[ 3.423427] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.470435] udevd[607]: starting version 182
+[ 3.470296] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.596617] random: dd urandom read with 22 bits of entropy available
+[ 3.606651] random: dd urandom read with 20 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.791906] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.801935] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|