diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/long/fs | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/long/fs')
25 files changed, 1100 insertions, 285 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 048f742ca..bf1bde417 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -936,9 +936,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -998,10 +997,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -1057,9 +1055,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index a7ff9525f..9e5305367 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:31:55 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index fbb891fc7..e3ecd4b02 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,23 +4,50 @@ sim_seconds 1.899401 # Nu sim_ticks 1899401490000 # Number of ticks simulated final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69911 # Simulator instruction rate (inst/s) -host_op_rate 69911 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2348556801 # Simulator tick rate (ticks/s) -host_mem_usage 300512 # Number of bytes of host memory used -host_seconds 808.75 # Real time elapsed on the host +host_inst_rate 124517 # Simulator instruction rate (inst/s) +host_op_rate 124517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4182952627 # Simulator tick rate (ticks/s) +host_mem_usage 300876 # Number of bytes of host memory used +host_seconds 454.08 # Real time elapsed on the host sim_insts 56540749 # Number of instructions simulated sim_ops 56540749 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30421696 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1133376 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10508736 # Number of bytes written to this memory -system.physmem.num_reads 475339 # Number of read requests responded to by this memory -system.physmem.num_writes 164199 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16016464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 596702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5532657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21549121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 865216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25431680 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 268160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1206144 # Number of bytes read from this memory +system.physmem.bytes_read::total 30421696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 865216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 268160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1133376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10508736 # Number of bytes written to this memory +system.physmem.bytes_written::total 10508736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 397370 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4190 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 18846 # Number of read requests responded to by this memory +system.physmem.num_reads::total 475339 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 164199 # Number of write requests responded to by this memory +system.physmem.num_writes::total 164199 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 455520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13389312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 141181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 635013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16016464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 455520 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 141181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 596702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5532657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5532657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5532657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 455520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13389312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 141181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 635013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21549121 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 397771 # number of replacements system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use system.l2c.total_refs 2469954 # Total number of references to valid blocks. @@ -142,38 +169,50 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.014629 # mi system.l2c.ReadReq_miss_rate::cpu0.data 0.301431 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.023663 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.026314 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.141923 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945624 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847087 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.924975 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.867133 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901235 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.885246 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.414779 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.474003 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.421493 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.014629 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.325894 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.023663 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.123786 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.175450 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.014629 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.325894 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.023663 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.123786 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.175450 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52306.597145 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52040.352799 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52326.955075 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 50733.511307 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52042.436289 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 692.922763 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3665.472779 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1263.403904 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17356.854839 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5568.493151 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 10982.407407 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52463.410281 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52413.706697 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52457.073833 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52161.894298 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52161.894298 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -254,44 +293,59 @@ system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014628 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.301431 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026314 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141914 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.945624 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847087 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.924975 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.867133 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.901235 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.885246 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.414779 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.474003 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.421493 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.175443 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.175443 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.837812 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39448.492462 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40026.250295 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.041511 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40004.297994 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40002.474567 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40004.032258 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.712329 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40002.777778 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40298.511698 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40214.276765 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40287.773030 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41698 # number of replacements system.iocache.tagsinuse 0.205020 # Cycle average of tags in use @@ -327,13 +381,21 @@ system.iocache.demand_accesses::total 41730 # nu system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115247.179775 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137665.980121 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137570.352360 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137570.352360 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked @@ -361,13 +423,21 @@ system.iocache.demand_mshr_miss_latency::total 3570695996 system.iocache.overall_mshr_miss_latency::tsunami.ide 3570695996 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.179775 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85662.254476 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -751,11 +821,17 @@ system.cpu0.icache.demand_accesses::total 7876403 # n system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.123657 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.123657 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.123657 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14933.529195 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14933.529195 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14933.529195 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked @@ -785,11 +861,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 11020233999 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.117352 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.117352 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.117352 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11922.673044 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1225027 # number of replacements system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use @@ -849,17 +931,29 @@ system.cpu0.dcache.demand_accesses::total 13473054 # n system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.193416 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.311981 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104660 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.010046 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.241498 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.241498 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22449.520533 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30909.202624 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14534.120482 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12237.192118 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26881.500057 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26881.500057 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked @@ -911,20 +1005,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118800 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049117 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083087 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.010046 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.090541 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.090541 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24163.211588 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29457.684102 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11127.026043 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9233.497537 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -1265,11 +1374,17 @@ system.cpu1.icache.demand_accesses::total 1679880 # n system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.112150 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.112150 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.112150 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15322.238028 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15322.238028 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15322.238028 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked @@ -1299,11 +1414,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 2188079500 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105852 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.105852 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.105852 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12305.163144 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 156190 # number of replacements system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use @@ -1363,17 +1484,29 @@ system.cpu1.dcache.demand_accesses::total 2874738 # n system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.125808 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.220031 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.138024 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081077 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.160323 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.160323 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15786.348523 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32638.570657 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13052.205690 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13354.471956 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24258.512904 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24258.512904 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked @@ -1425,20 +1558,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.069742 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.035185 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106355 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080913 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.057083 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.057083 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12373.655046 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30498.203530 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8775.237127 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10377.215190 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed @@ -1466,6 +1614,7 @@ system.cpu0.kern.ipl_used::21 1 # fr system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.801750 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed @@ -1523,7 +1672,7 @@ system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.278972 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode @@ -1550,6 +1699,7 @@ system.cpu1.kern.ipl_used::0 0.998669 # fr system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.782648 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed @@ -1595,7 +1745,7 @@ system.cpu1.kern.mode_good::idle 169 system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.702972 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.370812 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index a8321f91c..3ccfd349b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -512,9 +512,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -574,10 +573,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -633,9 +631,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 6b30da191..f3bacddca 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:06 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:16:04 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index ae2948145..d7b6a1ccb 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,23 +4,40 @@ sim_seconds 1.858684 # Nu sim_ticks 1858684403000 # Number of ticks simulated final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73473 # Simulator instruction rate (inst/s) -host_op_rate 73473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2572309842 # Simulator tick rate (ticks/s) -host_mem_usage 296656 # Number of bytes of host memory used -host_seconds 722.57 # Real time elapsed on the host +host_inst_rate 125153 # Simulator instruction rate (inst/s) +host_op_rate 125153 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4381630644 # Simulator tick rate (ticks/s) +host_mem_usage 297044 # Number of bytes of host memory used +host_seconds 424.20 # Real time elapsed on the host sim_insts 53089851 # Number of instructions simulated sim_ops 53089851 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 29847552 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1082432 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10195968 # Number of bytes written to this memory -system.physmem.num_reads 466368 # Number of read requests responded to by this memory -system.physmem.num_writes 159312 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16058429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 582365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5485583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21544012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 1082432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 26112576 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652544 # Number of bytes read from this memory +system.physmem.bytes_read::total 29847552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1082432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1082432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10195968 # Number of bytes written to this memory +system.physmem.bytes_written::total 10195968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16913 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 408009 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41446 # Number of read requests responded to by this memory +system.physmem.num_reads::total 466368 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 159312 # Number of write requests responded to by this memory +system.physmem.num_writes::total 159312 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 582365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14048956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1427108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16058429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 582365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 582365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5485583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5485583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5485583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 582365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14048956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1427108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21544012 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 391653 # number of replacements system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use system.l2c.total_refs 2427420 # Total number of references to valid blocks. @@ -98,21 +115,32 @@ system.l2c.overall_accesses::cpu.data 1403007 # nu system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.144884 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.680851 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.389089 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.175120 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.175120 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52055.178139 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 13296.875000 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52452.302421 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52164.425310 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52164.425310 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,25 +195,40 @@ system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998 system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.144884 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.680851 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.389089 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.175120 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.175120 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40034.215681 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41968.750000 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40285.591605 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.266745 # Cycle average of tags in use @@ -221,13 +264,21 @@ system.iocache.demand_accesses::total 41725 # nu system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115248.543353 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137703.090248 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137609.989311 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137609.989311 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked @@ -255,13 +306,21 @@ system.iocache.demand_mshr_miss_latency::total 3571928992 system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85699.532971 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -645,11 +704,17 @@ system.cpu.icache.demand_accesses::total 9001683 # nu system.cpu.icache.overall_accesses::cpu.inst 9001683 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 9001683 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120654 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120654 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.120654 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120654 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.120654 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120654 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14978.890385 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14978.890385 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14978.890385 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked @@ -679,11 +744,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12299507497 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12299507497 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12299507497 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114017 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114017 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114017 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.817785 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.817785 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1402627 # number of replacements system.cpu.dcache.tagsinuse 511.995944 # Cycle average of tags in use @@ -743,17 +814,29 @@ system.cpu.dcache.demand_accesses::total 15284608 # nu system.cpu.dcache.overall_accesses::cpu.data 15284608 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15284608 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197665 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.197665 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315555 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.315555 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107789 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000014 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000014 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.245154 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245154 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.245154 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245154 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21564.412465 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21564.412465 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29908.900809 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29908.900809 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14827.843607 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14827.843607 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27833.333333 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27833.333333 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25891.032108 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25891.032108 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 927127320 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked @@ -805,20 +888,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1233731998 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2137812498 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 2137812498 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118919 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118919 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048701 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048701 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082959 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082959 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000014 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000014 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090634 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090634 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22826.893897 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22826.893897 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28446.182850 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28446.182850 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11814.556470 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11814.556470 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24666.666667 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24666.666667 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed @@ -842,6 +940,7 @@ system.cpu.kern.ipl_used::0 0.981743 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815921 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -899,7 +998,7 @@ system.cpu.kern.mode_good::idle 170 system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401737 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.389995 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index b11582c4e..5d60c7bc8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -570,9 +571,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -631,10 +631,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -1046,9 +1045,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 1bca46ae4..086d512f2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:41:59 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:58:44 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2501685689500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 2501dfd76..e9f646cad 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.501686 # Nu sim_ticks 2501685689500 # Number of ticks simulated final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54158 # Simulator instruction rate (inst/s) -host_op_rate 69928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2274069684 # Simulator tick rate (ticks/s) -host_mem_usage 384504 # Number of bytes of host memory used -host_seconds 1100.09 # Real time elapsed on the host +host_inst_rate 49441 # Simulator instruction rate (inst/s) +host_op_rate 63837 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2075989543 # Simulator tick rate (ticks/s) +host_mem_usage 387400 # Number of bytes of host memory used +host_seconds 1205.06 # Real time elapsed on the host sim_insts 59579009 # Number of instructions simulated sim_ops 76926775 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585736 # Number of bytes written to this memory -system.physmem.num_reads 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes 856669 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory +system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 119797 # number of replacements system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use system.l2c.total_refs 1834134 # Total number of references to valid blocks. @@ -139,32 +170,44 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -241,37 +284,52 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -676,11 +734,17 @@ system.cpu.icache.demand_accesses::total 13709800 # nu system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked @@ -714,13 +778,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 645895 # number of replacements system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use @@ -780,17 +852,29 @@ system.cpu.dcache.demand_accesses::total 25214634 # nu system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked @@ -842,20 +926,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -876,7 +975,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 632f13a19..aff8253f7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -953,9 +954,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -1014,10 +1014,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -1429,9 +1428,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 3d3cfe606..c0177ee1d 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:41:59 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:58:50 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2570833934500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index a45391ada..6e759f59e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,32 +4,90 @@ sim_seconds 2.570834 # Nu sim_ticks 2570833934500 # Number of ticks simulated final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63716 # Simulator instruction rate (inst/s) -host_op_rate 82290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2641493756 # Simulator tick rate (ticks/s) -host_mem_usage 388068 # Number of bytes of host memory used -host_seconds 973.25 # Real time elapsed on the host +host_inst_rate 53678 # Simulator instruction rate (inst/s) +host_op_rate 69325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2225327298 # Simulator tick rate (ticks/s) +host_mem_usage 390932 # Number of bytes of host memory used +host_seconds 1155.26 # Real time elapsed on the host sim_insts 62012062 # Number of instructions simulated sim_ops 80088895 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 131429540 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1199424 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10175696 # Number of bytes written to this memory -system.physmem.num_reads 15128117 # Number of read requests responded to by this memory -system.physmem.num_writes 868949 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51123310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 466551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3958130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55081440 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory +system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 130926 # number of replacements system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use system.l2c.total_refs 1855308 # Total number of references to valid blocks. @@ -211,12 +269,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000137 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.014302 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.052466 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.849004 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836304 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.842250 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784080 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607287 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.696438 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.650892 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.552698 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.592636 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000869 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.024345 # miss rate for demand accesses @@ -225,6 +287,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.demand_miss_rate::cpu1.itb.walker 0.000137 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.014302 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.240884 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.100520 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000869 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.024345 # miss rate for overall accesses @@ -233,6 +296,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.overall_miss_rate::cpu1.itb.walker 0.000137 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.014302 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.240884 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.100520 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.338109 # average ReadReq miss latency @@ -241,12 +305,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52188.524590 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52316.416593 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.878665 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52259.373529 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3478.081138 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6680.529301 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5169.101633 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2849.619289 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8968.333333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5494.596542 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52435.364432 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52479.021964 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52459.519720 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency @@ -255,6 +323,7 @@ system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52188.524590 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52416.535382 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency @@ -263,6 +332,7 @@ system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52188.524590 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52416.535382 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,12 +451,16 @@ system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052326 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.024846 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.849004 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836304 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.842250 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784080 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607287 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.696438 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650892 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552698 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.592636 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for demand accesses @@ -395,6 +469,7 @@ system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.100469 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for overall accesses @@ -403,6 +478,7 @@ system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.100469 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average ReadReq mshr miss latency @@ -411,12 +487,16 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency @@ -425,6 +505,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency @@ -433,16 +514,20 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -802,11 +887,17 @@ system.cpu0.icache.demand_accesses::total 3831829 # n system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked @@ -840,13 +931,21 @@ system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 232498 # number of replacements system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use @@ -906,17 +1005,29 @@ system.cpu0.dcache.demand_accesses::total 9184667 # n system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked @@ -968,20 +1079,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -1335,11 +1461,17 @@ system.cpu1.icache.demand_accesses::total 10441732 # n system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked @@ -1373,13 +1505,21 @@ system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 417022 # number of replacements system.cpu1.dcache.tagsinuse 464.475329 # Cycle average of tags in use @@ -1439,17 +1579,29 @@ system.cpu1.dcache.demand_accesses::total 17145866 # n system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.128275 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15102.598715 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33117.439237 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12016.421751 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.894140 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8688.894140 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked @@ -1503,21 +1655,37 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -1538,7 +1706,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index e70ebd6c7..911c40f55 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -511,9 +512,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -572,10 +572,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -987,9 +986,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c9bc70145..c37c93eb0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:41:59 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:55:16 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2501685689500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 097a484ee..93f3afbea 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.501686 # Nu sim_ticks 2501685689500 # Number of ticks simulated final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62639 # Simulator instruction rate (inst/s) -host_op_rate 80877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2630163340 # Simulator tick rate (ticks/s) -host_mem_usage 384244 # Number of bytes of host memory used -host_seconds 951.15 # Real time elapsed on the host +host_inst_rate 57858 # Simulator instruction rate (inst/s) +host_op_rate 74704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2429415836 # Simulator tick rate (ticks/s) +host_mem_usage 387132 # Number of bytes of host memory used +host_seconds 1029.75 # Real time elapsed on the host sim_insts 59579009 # Number of instructions simulated sim_ops 76926775 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585736 # Number of bytes written to this memory -system.physmem.num_reads 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes 856669 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory +system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 119797 # number of replacements system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use system.l2c.total_refs 1834134 # Total number of references to valid blocks. @@ -139,32 +170,44 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -241,37 +284,52 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -631,11 +689,17 @@ system.cpu.icache.demand_accesses::total 13709800 # nu system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked @@ -669,13 +733,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 645895 # number of replacements system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use @@ -735,17 +807,29 @@ system.cpu.dcache.demand_accesses::total 25214634 # nu system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked @@ -797,20 +881,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -831,7 +930,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 7261617c5..a9da64c54 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 17:03:49 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 3dd4a07d4..bfc607b4f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,23 +4,48 @@ sim_seconds 5.157514 # Nu sim_ticks 5157514159500 # Number of ticks simulated final_tick 5157514159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128842 # Simulator instruction rate (inst/s) -host_op_rate 253899 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1558019011 # Simulator tick rate (ticks/s) -host_mem_usage 389972 # Number of bytes of host memory used -host_seconds 3310.30 # Real time elapsed on the host +host_inst_rate 123762 # Simulator instruction rate (inst/s) +host_op_rate 243888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1496586873 # Simulator tick rate (ticks/s) +host_mem_usage 369148 # Number of bytes of host memory used +host_seconds 3446.18 # Real time elapsed on the host sim_insts 426506235 # Number of instructions simulated sim_ops 840483958 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15959488 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1257664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 12050112 # Number of bytes written to this memory -system.physmem.num_reads 249367 # Number of read requests responded to by this memory -system.physmem.num_writes 188283 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3094415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 243851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2336419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5430833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::pc.south_bridge.ide 2798400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 6720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 1088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1257664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11895616 # Number of bytes read from this memory +system.physmem.bytes_read::total 15959488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1257664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1257664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 12050112 # Number of bytes written to this memory +system.physmem.bytes_written::total 12050112 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 43725 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 17 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 19651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 185869 # Number of read requests responded to by this memory +system.physmem.num_reads::total 249367 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 188283 # Number of write requests responded to by this memory +system.physmem.num_writes::total 188283 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 542587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 243851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2306463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3094415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 243851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 243851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2336419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2336419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2336419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 542587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 243851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2306463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5430833 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 167142 # number of replacements system.l2c.tagsinuse 37816.689690 # Cycle average of tags in use system.l2c.total_refs 3843284 # Total number of references to valid blocks. @@ -122,30 +147,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000957 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001927 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.018136 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.033077 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.882394 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.882394 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.481904 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.481904 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.000957 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.001927 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.018136 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.111631 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.071839 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.000957 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.001927 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.018136 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.111631 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.071839 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52468.724211 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52077.298075 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52201.292100 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52201.292100 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -213,33 +248,46 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000957 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.033076 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.025337 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.882394 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.882394 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.481904 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.481904 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.071838 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.071838 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47578 # number of replacements system.iocache.tagsinuse 0.166155 # Cycle average of tags in use @@ -275,13 +323,21 @@ system.iocache.demand_accesses::total 47633 # nu system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125279.224535 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 136416.955479 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 136203.474314 # average overall miss latency system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 136203.474314 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 69025534 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11269 # number of cycles access was blocked @@ -309,13 +365,21 @@ system.iocache.demand_mshr_miss_latency::total 4010524860 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 4010524860 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -635,11 +699,17 @@ system.cpu.icache.demand_accesses::total 9366799 # nu system.cpu.icache.overall_accesses::cpu.inst 9366799 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 9366799 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123115 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123115 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.123115 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123115 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.123115 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123115 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14938.055188 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14938.055188 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2912492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked @@ -669,11 +739,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 13093471492 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13093471492 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 13093471492 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115814 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115814 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115814 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12069.918282 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 10825 # number of replacements system.cpu.itb_walker_cache.tagsinuse 6.011393 # Cycle average of tags in use @@ -713,11 +789,17 @@ system.cpu.itb_walker_cache.demand_accesses::total 39097 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39097 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 39097 # number of overall (read+write) accesses system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298946 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298946 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298923 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.298923 # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298923 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.298923 # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12681.954308 # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12681.954308 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12681.954308 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,11 +823,17 @@ system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 112719500 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 112719500 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 112719500 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298946 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298946 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298923 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298923 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9644.861812 # average ReadReq mshr miss latency system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.replacements 116553 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 13.859632 # Cycle average of tags in use @@ -781,11 +869,17 @@ system.cpu.dtb_walker_cache.demand_accesses::total 253531 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253531 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 253531 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463730 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463730 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463730 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463730 # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463730 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463730 # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168 # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,11 +903,17 @@ system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1286519500 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1286519500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463730 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463730 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463730 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142 # average ReadReq mshr miss latency system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1673290 # number of replacements system.cpu.dcache.tagsinuse 511.997033 # Cycle average of tags in use @@ -857,13 +957,21 @@ system.cpu.dcache.demand_accesses::total 21751990 # nu system.cpu.dcache.overall_accesses::cpu.data 21751990 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21751990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180567 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180567 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037870 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037870 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.125479 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.125479 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.125479 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.125479 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17127.337761 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17127.337761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 25105497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3680 # number of cycles access was blocked @@ -905,16 +1013,27 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392930500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600685000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600685000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103449 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103449 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035203 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035203 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077103 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077103 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini index 78474a665..c9fc9d3a5 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -995,7 +995,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1015,7 +1015,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1185,9 +1185,8 @@ zero=false port=system.piobus.master[0] [system.piobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats index 5cc55eff8..f9683d0c4 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/21/2012 19:39:45 +Real time: Jun/04/2012 17:25:31 Profiler Stats -------------- -Elapsed_time_in_seconds: 1285 -Elapsed_time_in_minutes: 21.4167 -Elapsed_time_in_hours: 0.356944 -Elapsed_time_in_days: 0.0148727 +Elapsed_time_in_seconds: 842 +Elapsed_time_in_minutes: 14.0333 +Elapsed_time_in_hours: 0.233889 +Elapsed_time_in_days: 0.00974537 -Virtual_time_in_seconds: 1013.41 -Virtual_time_in_minutes: 16.8902 -Virtual_time_in_hours: 0.281503 -Virtual_time_in_days: 0.0117293 +Virtual_time_in_seconds: 842.03 +Virtual_time_in_minutes: 14.0338 +Virtual_time_in_hours: 0.233897 +Virtual_time_in_days: 0.00974572 Ruby_current_time: 10609379371 Ruby_start_time: 0 Ruby_cycles: 10609379371 -mbytes_resident: 269.652 -mbytes_total: 517.469 -resident_ratio: 0.521114 +mbytes_resident: 268.047 +mbytes_total: 470.199 +resident_ratio: 0.570071 ruby_cycles_executed: [ 10609379372 10609379372 ] @@ -123,13 +123,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 | Resource Usage -------------- page_size: 4096 -user_time: 1013 +user_time: 841 system_time: 0 -page_reclaims: 70791 -page_faults: 113 +page_reclaims: 69674 +page_faults: 18 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 16056 +block_outputs: 408 Network Stats ------------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index 4bb71c433..d6cb455f2 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 21 2012 19:18:11 -gem5 started May 21 2012 19:18:20 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jun 4 2012 13:44:12 +gem5 started Jun 4 2012 17:11:29 +gem5 executing on zizzer command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5304689685500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index c2f297e1d..b7d143468 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,23 +4,74 @@ sim_seconds 5.304690 # Nu sim_ticks 5304689685500 # Number of ticks simulated final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106822 # Simulator instruction rate (inst/s) -host_op_rate 218222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4128199893 # Simulator tick rate (ticks/s) -host_mem_usage 529892 # Number of bytes of host memory used -host_seconds 1284.99 # Real time elapsed on the host +host_inst_rate 163049 # Simulator instruction rate (inst/s) +host_op_rate 333085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6301127704 # Simulator tick rate (ticks/s) +host_mem_usage 481488 # Number of bytes of host memory used +host_seconds 841.86 # Real time elapsed on the host sim_insts 137264752 # Number of instructions simulated sim_ops 280412254 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1392025556 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1298120352 # Number of instructions bytes read from this memory -system.physmem.bytes_written 70902832 # Number of bytes written to this memory -system.physmem.num_reads 178001662 # Number of read requests responded to by this memory -system.physmem.num_writes 9866514 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 262414135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 244711836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13366066 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 275780201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory +system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory +system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory +system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -44,7 +95,7 @@ system.cpu0.num_func_calls 0 # nu system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls system.cpu0.num_int_insts 168469813 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 517963582 # number of times the integer registers were read +system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written @@ -68,7 +119,7 @@ system.cpu1.num_func_calls 0 # nu system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls system.cpu1.num_int_insts 89110416 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 273178552 # number of times the integer registers were read +system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index acae3dcdb..1fcee5057 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -19,7 +19,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic -memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem2 system.rom system.physmem +memories=system.partition_desc system.rom system.hypervisor_desc system.nvram system.physmem system.physmem2 num_work_ids=16 nvram=system.nvram nvram_addr=133429198848 @@ -140,9 +140,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=2 header_cycles=1 use_default_range=false @@ -151,10 +150,9 @@ master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake slave=system.bridge.master [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=2 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr index 179231b2e..61ba0c5bc 100755 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting terminal connections +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. hack: be nice to actually delete the event here diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index 3dd47139a..483f7795e 100755 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:49:20 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 15:02:47 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 714a7f4dc..80abd3d9c 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -4,67 +4,107 @@ sim_seconds 1.116889 # Nu sim_ticks 2233777512 # Number of ticks simulated final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 1707325 # Simulator instruction rate (inst/s) -host_op_rate 1707996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1711534 # Simulator tick rate (ticks/s) -host_mem_usage 511008 # Number of bytes of host memory used -host_seconds 1305.13 # Real time elapsed on the host +host_inst_rate 3140005 # Simulator instruction rate (inst/s) +host_op_rate 3141240 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3147745 # Simulator tick rate (ticks/s) +host_mem_usage 511524 # Number of bytes of host memory used +host_seconds 709.64 # Real time elapsed on the host sim_insts 2228284650 # Number of instructions simulated sim_ops 2229160714 # Number of ops (including micro ops) simulated -system.hypervisor_desc.bytes_read 16792 # Number of bytes read from this memory -system.hypervisor_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.hypervisor_desc.bytes_written 0 # Number of bytes written to this memory -system.hypervisor_desc.num_reads 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.num_writes 0 # Number of write requests responded to by this memory -system.hypervisor_desc.num_other 0 # Number of other requests responded to by this memory -system.hypervisor_desc.bw_read 15035 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_total 15035 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bytes_read 284 # Number of bytes read from this memory -system.nvram.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.nvram.bytes_written 92 # Number of bytes written to this memory -system.nvram.num_reads 284 # Number of read requests responded to by this memory -system.nvram.num_writes 92 # Number of write requests responded to by this memory -system.nvram.num_other 0 # Number of other requests responded to by this memory -system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bytes_read 4846 # Number of bytes read from this memory -system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.partition_desc.bytes_written 0 # Number of bytes written to this memory -system.partition_desc.num_reads 608 # Number of read requests responded to by this memory -system.partition_desc.num_writes 0 # Number of write requests responded to by this memory -system.partition_desc.num_other 0 # Number of other requests responded to by this memory -system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bytes_read 9813991967 # Number of bytes read from this memory -system.physmem2.bytes_inst_read 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_written 897268422 # Number of bytes written to this memory -system.physmem2.num_reads 2403489130 # Number of read requests responded to by this memory -system.physmem2.num_writes 187387796 # Number of write requests responded to by this memory -system.physmem2.num_other 5403067 # Number of other requests responded to by this memory -system.physmem2.bw_read 8786901931 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read 7447569684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_write 803364182 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_total 9590266113 # Total bandwidth to/from this memory (bytes/s) -system.rom.bytes_read 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory -system.rom.bytes_written 0 # Number of bytes written to this memory -system.rom.num_reads 195123 # Number of read requests responded to by this memory -system.rom.num_writes 0 # Number of write requests responded to by this memory -system.rom.num_other 0 # Number of other requests responded to by this memory -system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 709825348 # Number of bytes read from this memory -system.physmem.bytes_inst_read 612291324 # Number of instructions bytes read from this memory -system.physmem.bytes_written 15400223 # Number of bytes written to this memory -system.physmem.num_reads 165224885 # Number of read requests responded to by this memory -system.physmem.num_writes 1927067 # Number of write requests responded to by this memory -system.physmem.num_other 14 # Number of other requests responded to by this memory -system.physmem.bw_read 635538091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 548211557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13788502 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 649326593 # Total bandwidth to/from this memory (bytes/s) +system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory +system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory +system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory +system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory +system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s) +system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory +system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory +system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory +system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory +system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s) +system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory +system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory +system.rom.bytes_read::total 1128688 # Number of bytes read from this memory +system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory +system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory +system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory +system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory +system.rom.num_reads::total 195123 # Number of read requests responded to by this memory +system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory +system.nvram.bytes_read::total 284 # Number of bytes read from this memory +system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory +system.nvram.bytes_written::total 92 # Number of bytes written to this memory +system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory +system.nvram.num_reads::total 284 # Number of read requests responded to by this memory +system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory +system.nvram.num_writes::total 92 # Number of write requests responded to by this memory +system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory +system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory +system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory +system.physmem.num_other::total 14 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory +system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory +system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory +system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory +system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory +system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory +system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory +system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory +system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory +system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory +system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory +system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory +system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory +system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory +system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s) system.cpu.numCycles 2233777513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |