diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
| commit | 26ca8b87470912d5e593a21fc968dd2ddf0e20b2 (patch) | |
| tree | bf97df45e65f08107321f58d83688b08bbd3f675 /tests/long/fs | |
| parent | 6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6 (diff) | |
| download | gem5-26ca8b87470912d5e593a21fc968dd2ddf0e20b2.tar.xz | |
Regressions: Update stats due to O3 CPU changes
Diffstat (limited to 'tests/long/fs')
16 files changed, 3803 insertions, 3890 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 94bfc8925..46790add4 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,14 +11,14 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -104,6 +105,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -135,6 +137,7 @@ tracer=system.cpu0.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -540,6 +543,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -571,6 +575,7 @@ tracer=system.cpu1.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -932,7 +937,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -952,7 +957,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1052,7 +1057,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1081,7 +1085,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -1122,7 +1126,6 @@ pio=system.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[1] @@ -1204,7 +1207,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1221,7 +1223,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1238,7 +1239,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1255,7 +1255,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1272,7 +1271,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1289,7 +1287,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1306,7 +1303,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1323,7 +1319,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1340,7 +1335,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1357,7 +1351,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1374,7 +1367,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1391,7 +1383,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1408,7 +1399,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1425,7 +1415,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1442,7 +1431,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1459,7 +1447,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1476,7 +1463,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1493,7 +1479,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1510,7 +1495,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1526,7 +1510,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=system.tsunami system=system pio=system.iobus.port[22] @@ -1591,7 +1574,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=system.tsunami system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1602,7 +1584,6 @@ pio=system.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[2] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 35f0311de..fd99ca0d0 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 06:11:48 -gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Feb 3 2012 13:46:22 +gem5 started Feb 3 2012 13:46:34 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 106949500 -Exiting @ tick 1897465263500 because m5_exit instruction encountered +Exiting @ tick 1897464893500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index d2e784a3f..78411ca4d 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,144 +1,144 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.897465 # Number of seconds simulated -sim_ticks 1897465263500 # Number of ticks simulated -final_tick 1897465263500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1897464893500 # Number of ticks simulated +final_tick 1897464893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131690 # Simulator instruction rate (inst/s) -host_tick_rate 4451680142 # Simulator tick rate (ticks/s) -host_mem_usage 298548 # Number of bytes of host memory used -host_seconds 426.24 # Real time elapsed on the host -sim_insts 56130966 # Number of instructions simulated -system.physmem.bytes_read 30408320 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1097728 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10468544 # Number of bytes written to this memory -system.physmem.num_reads 475130 # Number of read requests responded to by this memory -system.physmem.num_writes 163571 # Number of write requests responded to by this memory +host_inst_rate 100310 # Simulator instruction rate (inst/s) +host_tick_rate 3391719918 # Simulator tick rate (ticks/s) +host_mem_usage 326488 # Number of bytes of host memory used +host_seconds 559.44 # Real time elapsed on the host +sim_insts 56117221 # Number of instructions simulated +system.physmem.bytes_read 30408512 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1099328 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10470144 # Number of bytes written to this memory +system.physmem.num_reads 475133 # Number of read requests responded to by this memory +system.physmem.num_writes 163596 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16025758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 578523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5517120 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21542879 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 397795 # number of replacements -system.l2c.tagsinuse 35116.884908 # Cycle average of tags in use -system.l2c.total_refs 2482671 # Total number of references to valid blocks. -system.l2c.sampled_refs 433561 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.726232 # Average number of references to valid blocks. +system.physmem.bw_read 16025863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 579367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5517965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 21543827 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 397850 # number of replacements +system.l2c.tagsinuse 35109.782430 # Cycle average of tags in use +system.l2c.total_refs 2482376 # Total number of references to valid blocks. +system.l2c.sampled_refs 433566 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.725486 # Average number of references to valid blocks. system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12003.983788 # Average occupied blocks per context -system.l2c.occ_blocks::1 238.395777 # Average occupied blocks per context -system.l2c.occ_blocks::2 22874.505342 # Average occupied blocks per context -system.l2c.occ_percent::0 0.183166 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.003638 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.349037 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1719678 # number of ReadReq hits -system.l2c.ReadReq_hits::1 147350 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1867028 # number of ReadReq hits -system.l2c.Writeback_hits::0 826540 # number of Writeback hits -system.l2c.Writeback_hits::total 826540 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 46 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 28 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 28 # number of SCUpgradeReq hits +system.l2c.occ_blocks::0 12005.589305 # Average occupied blocks per context +system.l2c.occ_blocks::1 237.479904 # Average occupied blocks per context +system.l2c.occ_blocks::2 22866.713220 # Average occupied blocks per context +system.l2c.occ_percent::0 0.183191 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.003624 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.348918 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1720206 # number of ReadReq hits +system.l2c.ReadReq_hits::1 147304 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1867510 # number of ReadReq hits +system.l2c.Writeback_hits::0 827202 # number of Writeback hits +system.l2c.Writeback_hits::total 827202 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 175 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 45 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 29 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 27 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 168225 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 11091 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179316 # number of ReadExReq hits -system.l2c.demand_hits::0 1887903 # number of demand (read+write) hits -system.l2c.demand_hits::1 158441 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 168180 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 11095 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179275 # number of ReadExReq hits +system.l2c.demand_hits::0 1888386 # number of demand (read+write) hits +system.l2c.demand_hits::1 158399 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2046344 # number of demand (read+write) hits -system.l2c.overall_hits::0 1887903 # number of overall hits -system.l2c.overall_hits::1 158441 # number of overall hits +system.l2c.demand_hits::total 2046785 # number of demand (read+write) hits +system.l2c.overall_hits::0 1888386 # number of overall hits +system.l2c.overall_hits::1 158399 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2046344 # number of overall hits -system.l2c.ReadReq_misses::0 305537 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4057 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309594 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2453 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 560 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3013 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 48 # number of SCUpgradeReq misses +system.l2c.overall_hits::total 2046785 # number of overall hits +system.l2c.ReadReq_misses::0 305580 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4046 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309626 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2447 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 562 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 45 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::1 84 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 132 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 113925 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 10735 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124660 # number of ReadExReq misses -system.l2c.demand_misses::0 419462 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::total 129 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 113888 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 10746 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124634 # number of ReadExReq misses +system.l2c.demand_misses::0 419468 # number of demand (read+write) misses system.l2c.demand_misses::1 14792 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 434254 # number of demand (read+write) misses -system.l2c.overall_misses::0 419462 # number of overall misses +system.l2c.demand_misses::total 434260 # number of demand (read+write) misses +system.l2c.overall_misses::0 419468 # number of overall misses system.l2c.overall_misses::1 14792 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 434254 # number of overall misses -system.l2c.ReadReq_miss_latency 16116451000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 3978500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 680500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6538718500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22655169500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22655169500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2025215 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 151407 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2176622 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 826540 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 826540 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2625 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 606 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3231 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 76 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 112 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 282150 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 21826 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 303976 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2307365 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 173233 # number of demand (read+write) accesses +system.l2c.overall_misses::total 434260 # number of overall misses +system.l2c.ReadReq_miss_latency 16117985000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 4084000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 629500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6538201500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22656186500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22656186500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2025786 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 151350 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2177136 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 827202 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 827202 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2622 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 607 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3229 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 74 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 111 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 185 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 282068 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21841 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 303909 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2307854 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 173191 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2480598 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2307365 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 173233 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2481045 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2307854 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 173191 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2480598 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.150866 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.026795 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.934476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.924092 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.631579 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.750000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.403775 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.491845 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.181793 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.085388 # miss rate for demand accesses +system.l2c.overall_accesses::total 2481045 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.150845 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.026733 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.933257 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.925865 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.608108 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.756757 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.403761 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.492010 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.181757 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.085409 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.181793 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.085388 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.181757 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.085409 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52747.951967 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3972504.560020 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52745.549447 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3983683.885319 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 1621.891561 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 7104.464286 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 1668.982427 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7266.903915 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 14177.083333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 8101.190476 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 13988.888889 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 7494.047619 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 57394.939653 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 609102.794597 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 57409.046607 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 608431.183696 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 54010.064082 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1531582.578421 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 54011.716031 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1531651.331801 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 54010.064082 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1531582.578421 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 54011.716031 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1531651.331801 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -149,56 +149,56 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 122051 # number of writebacks +system.l2c.writebacks 122076 # number of writebacks system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 309576 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3013 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 132 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 124660 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 434236 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 434236 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 309608 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3009 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 129 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124634 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 434242 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 434242 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12393243000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 120589000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 5280000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5022395000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17415638000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17415638000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 838122500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1421433998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2259556498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.152861 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.044661 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12394422500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 120428500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 5161500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5022578000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17417000500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17417000500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838122000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1420361498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2258483498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.152834 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.045643 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.147810 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.971947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.147597 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.957166 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.736842 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.178571 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.743243 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.162162 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.441822 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 5.711537 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.441858 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 5.706424 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.188196 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 2.506659 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.188158 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 2.507301 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.188196 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 2.506659 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.188158 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 2.507301 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40032.957981 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.900763 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40288.745387 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40032.629971 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.765038 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40011.627907 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40298.618355 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40108.972647 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40108.972647 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -206,13 +206,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.463240 # Cycle average of tags in use +system.iocache.tagsinuse 0.463236 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709322874000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.463240 # Average occupied blocks per context -system.iocache.occ_percent::1 0.028953 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1709322783000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.463236 # Average occupied blocks per context +system.iocache.occ_percent::1 0.028952 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -229,10 +229,10 @@ system.iocache.demand_misses::total 41729 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41729 # number of overall misses system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency 20390998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5721236806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741627804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741627804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 20391998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5720293806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5740685804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5740685804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 177 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -252,22 +252,22 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115203.378531 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115209.028249 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137688.602378 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137665.907923 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137593.227827 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137570.653598 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137593.227827 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137570.653598 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64620068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64638062 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6179.008223 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6181.319881 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -279,10 +279,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41729 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41729 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11186998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3560378000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571564998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571564998 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11187998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3559436992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3570624990 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3570624990 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -296,10 +296,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63203.378531 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85684.876781 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63209.028249 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85662.230266 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85566.991541 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85566.991541 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -320,22 +320,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9507417 # DTB read hits -system.cpu0.dtb.read_misses 35968 # DTB read misses -system.cpu0.dtb.read_acv 598 # DTB read access violations -system.cpu0.dtb.read_accesses 640032 # DTB read accesses -system.cpu0.dtb.write_hits 6191307 # DTB write hits -system.cpu0.dtb.write_misses 8160 # DTB write misses -system.cpu0.dtb.write_acv 353 # DTB write access violations -system.cpu0.dtb.write_accesses 218604 # DTB write accesses -system.cpu0.dtb.data_hits 15698724 # DTB hits -system.cpu0.dtb.data_misses 44128 # DTB misses -system.cpu0.dtb.data_acv 951 # DTB access violations -system.cpu0.dtb.data_accesses 858636 # DTB accesses -system.cpu0.itb.fetch_hits 1059111 # ITB hits -system.cpu0.itb.fetch_misses 28345 # ITB misses -system.cpu0.itb.fetch_acv 951 # ITB acv -system.cpu0.itb.fetch_accesses 1087456 # ITB accesses +system.cpu0.dtb.read_hits 9525013 # DTB read hits +system.cpu0.dtb.read_misses 35809 # DTB read misses +system.cpu0.dtb.read_acv 596 # DTB read access violations +system.cpu0.dtb.read_accesses 640960 # DTB read accesses +system.cpu0.dtb.write_hits 6193277 # DTB write hits +system.cpu0.dtb.write_misses 8191 # DTB write misses +system.cpu0.dtb.write_acv 352 # DTB write access violations +system.cpu0.dtb.write_accesses 218947 # DTB write accesses +system.cpu0.dtb.data_hits 15718290 # DTB hits +system.cpu0.dtb.data_misses 44000 # DTB misses +system.cpu0.dtb.data_acv 948 # DTB access violations +system.cpu0.dtb.data_accesses 859907 # DTB accesses +system.cpu0.itb.fetch_hits 1059968 # ITB hits +system.cpu0.itb.fetch_misses 28334 # ITB misses +system.cpu0.itb.fetch_acv 968 # ITB acv +system.cpu0.itb.fetch_accesses 1088302 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -348,276 +348,276 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112078637 # number of cpu cycles simulated +system.cpu0.numCycles 112143855 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13676513 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11471993 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 481224 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 12342117 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 6355141 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13691834 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11482212 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 486842 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 12387016 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 6381871 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 915334 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37832 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28007609 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69419364 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13676513 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 7270475 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 13464854 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2130456 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34838342 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 192876 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 330870 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8508842 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 295697 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 78241728 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.887242 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.203788 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 919331 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 37475 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28027181 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69568075 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13691834 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 7301202 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 13494473 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2151438 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34839073 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31251 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 192820 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 330609 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8536872 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 297084 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 78309049 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.888378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.203941 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64776874 82.79% 82.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 958993 1.23% 84.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1895458 2.42% 86.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 896557 1.15% 87.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2826529 3.61% 91.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 644193 0.82% 92.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 736181 0.94% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1019927 1.30% 94.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4487016 5.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64814576 82.77% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 945457 1.21% 83.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1900376 2.43% 86.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 913364 1.17% 87.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2830968 3.62% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 643425 0.82% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 763526 0.98% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1019235 1.30% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4478122 5.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 78241728 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.122026 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.619381 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29114965 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34547748 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12317154 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 921824 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1340036 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 563514 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 37992 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 67952438 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 114909 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1340036 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30246504 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12447336 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18631420 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11494424 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4082006 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64196257 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6719 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 464674 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1470831 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 42946380 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 77900777 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77469173 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 431604 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36477108 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6469264 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1576496 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238440 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11483101 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10008373 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6527102 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1185571 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 771360 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56320474 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2007436 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54875963 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 110266 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7429207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3754226 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1369428 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 78241728 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.701364 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.347589 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 78309049 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.122092 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.620347 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29152885 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34531702 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12346249 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 922431 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1355781 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 563186 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 37995 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 68107436 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 115019 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1355781 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30289459 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12441617 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18623001 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11519994 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4079195 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64318914 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6762 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 463310 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1470134 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 43045469 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 78042276 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77610485 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 431791 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36467151 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6578318 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1575666 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238414 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11470150 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10031617 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6527341 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1189503 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 776121 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56398484 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2006474 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54915556 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 111021 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7522313 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3811151 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1368811 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 78309049 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.701267 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.347671 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54100520 69.15% 69.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10639232 13.60% 82.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5191485 6.64% 89.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3321136 4.24% 93.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2520069 3.22% 96.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1468713 1.88% 98.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 637402 0.81% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 263268 0.34% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 99903 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54156181 69.16% 69.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10641057 13.59% 82.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5191025 6.63% 89.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3329795 4.25% 93.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2517318 3.21% 96.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1471186 1.88% 98.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 638979 0.82% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 264076 0.34% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 99432 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 78241728 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 78309049 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 61581 8.74% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 342929 48.66% 57.40% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 300261 42.60% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 63169 8.93% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 344330 48.66% 57.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 300145 42.41% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3329 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37711302 68.72% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60327 0.11% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9937545 18.11% 86.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6268980 11.42% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 877144 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3325 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37729557 68.70% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60298 0.11% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9958587 18.13% 86.99% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6269977 11.42% 98.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 876476 1.60% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54875963 # Type of FU issued -system.cpu0.iq.rate 0.489620 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 704772 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012843 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 188187092 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65472775 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53463452 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 621599 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 297101 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294471 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55250754 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326652 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 544032 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54915556 # Type of FU issued +system.cpu0.iq.rate 0.489688 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 707644 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012886 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 188337006 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65642365 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53492231 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 621820 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 297359 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 294491 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55293187 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 326688 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 545095 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1411765 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 14119 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13054 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 526523 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1437170 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 14653 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12768 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 528040 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 19033 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 166880 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18971 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 166861 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1340036 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8692237 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 606269 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61830785 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 830784 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10008373 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6527102 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1772467 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 482817 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10549 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13054 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 346528 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 358003 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 704531 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54241616 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9570533 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 634346 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1355781 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8686714 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 606542 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61919404 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 833136 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10031617 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6527341 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1771520 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 483474 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10610 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12768 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 354996 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 356258 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 711254 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54276592 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9587869 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 638964 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3502875 # number of nop insts executed -system.cpu0.iew.exec_refs 15784325 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8657029 # Number of branches executed -system.cpu0.iew.exec_stores 6213792 # Number of stores executed -system.cpu0.iew.exec_rate 0.483960 # Inst execution rate -system.cpu0.iew.wb_sent 53872827 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53757923 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26542591 # num instructions producing a value -system.cpu0.iew.wb_consumers 35724968 # num instructions consuming a value +system.cpu0.iew.exec_nop 3514446 # number of nop insts executed +system.cpu0.iew.exec_refs 15803723 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8658040 # Number of branches executed +system.cpu0.iew.exec_stores 6215854 # Number of stores executed +system.cpu0.iew.exec_rate 0.483991 # Inst execution rate +system.cpu0.iew.wb_sent 53903758 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53786722 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26555285 # num instructions producing a value +system.cpu0.iew.wb_consumers 35742632 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.479645 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742970 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.479623 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742958 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 53656716 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 8078010 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638008 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 642783 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76901692 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.697731 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.609209 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 53643051 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 8183882 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 637663 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 648245 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76953268 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.697086 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608248 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56673915 73.70% 73.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8488315 11.04% 84.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4528829 5.89% 90.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2497024 3.25% 93.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1465718 1.91% 95.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 614414 0.80% 96.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 447034 0.58% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 489019 0.64% 97.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1697424 2.21% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56721555 73.71% 73.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8492436 11.04% 84.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4533561 5.89% 90.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2497224 3.25% 93.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1462149 1.90% 95.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 614089 0.80% 96.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 448311 0.58% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 488630 0.63% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1695313 2.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76901692 # Number of insts commited each cycle -system.cpu0.commit.count 53656716 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 76953268 # Number of insts commited each cycle +system.cpu0.commit.count 53643051 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14597187 # Number of memory references committed -system.cpu0.commit.loads 8596608 # Number of loads committed -system.cpu0.commit.membars 217615 # Number of memory barriers committed -system.cpu0.commit.branches 8092300 # Number of branches committed +system.cpu0.commit.refs 14593748 # Number of memory references committed +system.cpu0.commit.loads 8594447 # Number of loads committed +system.cpu0.commit.membars 217509 # Number of memory barriers committed +system.cpu0.commit.branches 8090596 # Number of branches committed system.cpu0.commit.fp_insts 291990 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49637924 # Number of committed integer instructions. -system.cpu0.commit.function_calls 704482 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1697424 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 49625357 # Number of committed integer instructions. +system.cpu0.commit.function_calls 704226 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1695313 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 136748495 # The number of ROB reads -system.cpu0.rob.rob_writes 124811050 # The number of ROB writes -system.cpu0.timesIdled 1231942 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33836909 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3682845519 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50542242 # Number of Instructions Simulated -system.cpu0.committedInsts_total 50542242 # Number of Instructions Simulated -system.cpu0.cpi 2.217524 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.217524 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.450953 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.450953 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71124780 # number of integer regfile reads -system.cpu0.int_regfile_writes 38876207 # number of integer regfile writes -system.cpu0.fp_regfile_reads 143910 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146325 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1863327 # number of misc regfile reads -system.cpu0.misc_regfile_writes 888204 # number of misc regfile writes +system.cpu0.rob.rob_reads 136894487 # The number of ROB reads +system.cpu0.rob.rob_writes 125011331 # The number of ROB writes +system.cpu0.timesIdled 1231743 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33834806 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3682779567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 50529139 # Number of Instructions Simulated +system.cpu0.committedInsts_total 50529139 # Number of Instructions Simulated +system.cpu0.cpi 2.219390 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.219390 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.450574 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.450574 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71166140 # number of integer regfile reads +system.cpu0.int_regfile_writes 38904534 # number of integer regfile writes +system.cpu0.fp_regfile_reads 143931 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146323 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1862401 # number of misc regfile reads +system.cpu0.misc_regfile_writes 887781 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -649,233 +649,233 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 970482 # number of replacements -system.cpu0.icache.tagsinuse 510.008508 # Cycle average of tags in use -system.cpu0.icache.total_refs 7483994 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 970994 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.707559 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23358720000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 510.008508 # Average occupied blocks per context +system.cpu0.icache.replacements 970410 # number of replacements +system.cpu0.icache.tagsinuse 510.008513 # Cycle average of tags in use +system.cpu0.icache.total_refs 7511566 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 970922 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.736529 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23358767000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 510.008513 # Average occupied blocks per context system.cpu0.icache.occ_percent::0 0.996110 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 7483994 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7483994 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 7483994 # number of demand (read+write) hits +system.cpu0.icache.ReadReq_hits::0 7511566 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7511566 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 7511566 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7483994 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 7483994 # number of overall hits +system.cpu0.icache.demand_hits::total 7511566 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 7511566 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 7483994 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 1024848 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1024848 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 1024848 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 7511566 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 1025306 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1025306 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 1025306 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1024848 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 1024848 # number of overall misses +system.cpu0.icache.demand_misses::total 1025306 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 1025306 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 1024848 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 15319794498 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 15319794498 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 15319794498 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 8508842 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8508842 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 8508842 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 1025306 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 15323045497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 15323045497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 15323045497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 8536872 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8536872 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 8536872 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8508842 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 8508842 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 8536872 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 8536872 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8508842 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.120445 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.120445 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 8536872 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.120103 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.120103 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.120445 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.120103 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14948.357706 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14944.851095 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14948.357706 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14944.851095 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14948.357706 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14944.851095 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1225998 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1297498 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 103 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 107 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11902.893204 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12126.149533 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 218 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 53716 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 53716 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 53716 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 971132 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 971132 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 971132 # number of overall MSHR misses +system.cpu0.icache.writebacks 220 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 54249 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 54249 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 54249 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 971057 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 971057 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 971057 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 11617050998 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 11617050998 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 11617050998 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 11617533498 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 11617533498 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 11617533498 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.114132 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113749 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.114132 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.113749 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.114132 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.113749 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11962.381013 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11963.801814 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11963.801814 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11963.801814 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1339905 # number of replacements -system.cpu0.dcache.tagsinuse 503.729057 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11343106 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1340416 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.462377 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1340651 # number of replacements +system.cpu0.dcache.tagsinuse 503.872538 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11358067 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1341162 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.468826 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 504.729057 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 504.872538 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.985799 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::0 0.986079 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 6978274 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6978274 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 3967577 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3967577 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 182488 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 182488 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 208558 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208558 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 10945851 # number of demand (read+write) hits +system.cpu0.dcache.ReadReq_hits::0 6993872 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6993872 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 3966970 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3966970 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 182544 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 182544 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 208490 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208490 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 10960842 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10945851 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 10945851 # number of overall hits +system.cpu0.dcache.demand_hits::total 10960842 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 10960842 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10945851 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 1696520 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1696520 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1808915 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1808915 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 21731 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21731 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 693 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 693 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 3505435 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 10960842 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 1697480 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1697480 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1808304 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1808304 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 21693 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21693 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 688 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 3505784 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3505435 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 3505435 # number of overall misses +system.cpu0.dcache.demand_misses::total 3505784 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 3505784 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 3505435 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 37036233000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 55166183811 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 327139500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 6516000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 92202416811 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 92202416811 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8674794 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8674794 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5776492 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5776492 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 204219 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 204219 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 209251 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209251 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14451286 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 3505784 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 37053025000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 55161743853 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 326351000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 6342500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 92214768853 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 92214768853 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8691352 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8691352 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 5775274 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5775274 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 204237 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 204237 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 209178 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 209178 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14466626 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14451286 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14451286 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14466626 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14466626 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14451286 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.195569 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.313151 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106410 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003312 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.242569 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14466626 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.195307 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.313111 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106215 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003289 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.242336 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.242569 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.242336 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 21830.708156 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 21828.254236 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 30496.835844 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 30504.684972 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15054.047214 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15044.069516 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9402.597403 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9218.750000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 26302.703320 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 26303.608224 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 26302.703320 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 26303.608224 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 886352311 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 100011 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8862.548230 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 23388.888889 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 888039305 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 98700 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8997.358713 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 790429 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 651194 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1524352 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 4898 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 2175546 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 2175546 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 1045326 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 284563 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16833 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 693 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1329889 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1329889 # number of overall MSHR misses +system.cpu0.dcache.writebacks 791009 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 651385 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1523767 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 4864 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 2175152 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 2175152 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 1046095 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 284537 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 688 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 1330632 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 1330632 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 24217800500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 8294565311 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 195726500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4430000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 32512365811 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 32512365811 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 916795000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1253240498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 2170035498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120502 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 24225951000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 8293520304 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 195490000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4269500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 32519471304 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 32519471304 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 916801000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1252089998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 2168890998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120360 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049262 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049268 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082426 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082399 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003312 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003289 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.092026 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.091979 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.092026 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.091979 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23167.701272 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29148.432196 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11627.547080 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6392.496392 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23158.461708 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29147.423021 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11616.257650 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6205.668605 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 24439.117129 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 24439.117129 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -886,22 +886,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1326048 # DTB read hits -system.cpu1.dtb.read_misses 10245 # DTB read misses -system.cpu1.dtb.read_acv 4 # DTB read access violations -system.cpu1.dtb.read_accesses 331667 # DTB read accesses -system.cpu1.dtb.write_hits 775032 # DTB write hits -system.cpu1.dtb.write_misses 3356 # DTB write misses -system.cpu1.dtb.write_acv 50 # DTB write access violations -system.cpu1.dtb.write_accesses 128144 # DTB write accesses -system.cpu1.dtb.data_hits 2101080 # DTB hits -system.cpu1.dtb.data_misses 13601 # DTB misses -system.cpu1.dtb.data_acv 54 # DTB access violations -system.cpu1.dtb.data_accesses 459811 # DTB accesses -system.cpu1.itb.fetch_hits 367550 # ITB hits -system.cpu1.itb.fetch_misses 7752 # ITB misses -system.cpu1.itb.fetch_acv 129 # ITB acv -system.cpu1.itb.fetch_accesses 375302 # ITB accesses +system.cpu1.dtb.read_hits 1327892 # DTB read hits +system.cpu1.dtb.read_misses 10318 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 331425 # DTB read accesses +system.cpu1.dtb.write_hits 775217 # DTB write hits +system.cpu1.dtb.write_misses 3380 # DTB write misses +system.cpu1.dtb.write_acv 51 # DTB write access violations +system.cpu1.dtb.write_accesses 128049 # DTB write accesses +system.cpu1.dtb.data_hits 2103109 # DTB hits +system.cpu1.dtb.data_misses 13698 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 459474 # DTB accesses +system.cpu1.itb.fetch_hits 367800 # ITB hits +system.cpu1.itb.fetch_misses 7781 # ITB misses +system.cpu1.itb.fetch_acv 134 # ITB acv +system.cpu1.itb.fetch_accesses 375581 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -914,501 +914,501 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 9966962 # number of cpu cycles simulated +system.cpu1.numCycles 9964881 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1746608 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1443175 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 66232 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1579747 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 700902 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1747552 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1443569 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 66414 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1567726 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 697812 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 120007 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5197 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3352188 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8389538 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1746608 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 820909 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1600088 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 340649 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3953742 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24318 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65300 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48169 # Number of stall cycles due to pending quiesce instructions +system.cpu1.BPredUnit.usedRAS 120159 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5219 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3352807 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8393265 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1747552 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 817971 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1599998 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 341231 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3951622 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24365 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48200 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1052111 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 37387 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9268453 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.905171 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.248228 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 1053319 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 37675 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9267506 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.905666 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.249416 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 7668365 82.74% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 115994 1.25% 83.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 231226 2.49% 86.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 132329 1.43% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 251751 2.72% 90.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 85931 0.93% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 105894 1.14% 92.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 73622 0.79% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 603341 6.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 7667508 82.74% 82.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 116348 1.26% 83.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 230890 2.49% 86.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 132710 1.43% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 250243 2.70% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 85158 0.92% 91.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 106718 1.15% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 73511 0.79% 93.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 604420 6.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9268453 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.175240 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.841735 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3426888 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4059985 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1487039 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 74425 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 220115 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 74752 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4586 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8123817 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13801 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 220115 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3563676 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 426586 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3211249 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1411283 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 435542 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7548530 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 46052 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 92764 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5048861 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9245845 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9192898 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52947 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4017246 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1031615 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 305905 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22528 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1292369 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1416426 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 841512 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 141179 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 90021 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6602199 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 325316 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6284355 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22621 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1273450 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 716539 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 249793 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9268453 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.678037 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.328780 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9267506 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.175371 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.842285 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3427974 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4057837 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1486886 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 74257 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 220551 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 74813 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4599 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8126768 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13850 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 220551 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3564378 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 427759 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3208421 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1411256 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 435139 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7552023 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 45897 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 92610 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 5051424 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9247695 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9194844 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52851 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 4016877 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1034547 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 305973 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22549 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1293822 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1418447 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 841500 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 143535 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 89440 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6603642 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 325438 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6286957 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22758 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1275148 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 714507 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 249945 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9267506 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.678387 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.328894 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 6498051 70.11% 70.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1227525 13.24% 83.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 582679 6.29% 89.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 391581 4.22% 93.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 294983 3.18% 97.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 158395 1.71% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 72456 0.78% 99.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 32178 0.35% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10605 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 6496050 70.09% 70.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1227596 13.25% 83.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 583666 6.30% 89.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 391304 4.22% 93.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 294316 3.18% 97.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 159029 1.72% 98.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 73572 0.79% 99.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 31508 0.34% 99.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10465 0.11% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9268453 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9267506 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2859 1.97% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 82047 56.45% 58.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60446 41.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2850 1.96% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 81883 56.36% 58.33% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 60541 41.67% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3978 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3890788 61.91% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10226 0.16% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1381194 21.98% 84.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 794695 12.65% 96.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 191415 3.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3977 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3891249 61.89% 61.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10225 0.16% 62.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1383111 22.00% 84.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 794977 12.64% 96.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 191359 3.04% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6284355 # Type of FU issued -system.cpu1.iq.rate 0.630519 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 145352 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023129 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 21926150 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8163461 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6082297 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 78986 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 39141 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37853 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6384800 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40929 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 61528 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6286957 # Type of FU issued +system.cpu1.iq.rate 0.630911 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 145274 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023107 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 21930562 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8166757 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6084651 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 78890 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 39096 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 37806 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6387378 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 40876 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 61877 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 262809 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1750 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 113415 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 265041 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6645 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1728 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 113419 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 366 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 22210 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 368 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 22536 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 220115 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 309272 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 12037 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7192077 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 99271 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1416426 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 841512 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 303434 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 3996 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4977 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1750 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 48213 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 60062 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 108275 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6205529 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1339876 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 78826 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 220551 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 309881 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 12131 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7193888 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 99371 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1418447 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 841500 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 303567 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4003 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 5102 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1728 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 48086 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 60250 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 108336 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6208556 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1341795 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 78401 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 264562 # number of nop insts executed -system.cpu1.iew.exec_refs 2121617 # number of memory reference insts executed -system.cpu1.iew.exec_branches 906286 # Number of branches executed -system.cpu1.iew.exec_stores 781741 # Number of stores executed -system.cpu1.iew.exec_rate 0.622610 # Inst execution rate -system.cpu1.iew.wb_sent 6147670 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6120150 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2958458 # num instructions producing a value -system.cpu1.iew.wb_consumers 4045224 # num instructions consuming a value +system.cpu1.iew.exec_nop 264808 # number of nop insts executed +system.cpu1.iew.exec_refs 2123746 # number of memory reference insts executed +system.cpu1.iew.exec_branches 906293 # Number of branches executed +system.cpu1.iew.exec_stores 781951 # Number of stores executed +system.cpu1.iew.exec_rate 0.623044 # Inst execution rate +system.cpu1.iew.wb_sent 6150217 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6122457 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2959215 # num instructions producing a value +system.cpu1.iew.wb_consumers 4044738 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614044 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.731346 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614403 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.731621 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5812223 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1307029 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 75523 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 100285 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9048338 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642353 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.547343 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5811574 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1309607 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 75493 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 100450 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9046955 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.642379 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.547455 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6777327 74.90% 74.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1099919 12.16% 87.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 394591 4.36% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 244546 2.70% 94.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 155405 1.72% 95.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 74689 0.83% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76341 0.84% 97.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 67787 0.75% 98.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 157733 1.74% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6775881 74.90% 74.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1100597 12.17% 87.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 394396 4.36% 91.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 244103 2.70% 94.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 155347 1.72% 95.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 74536 0.82% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 76677 0.85% 97.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 67598 0.75% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 157820 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9048338 # Number of insts commited each cycle -system.cpu1.commit.count 5812223 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 9046955 # Number of insts commited each cycle +system.cpu1.commit.count 5811574 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1881714 # Number of memory references committed -system.cpu1.commit.loads 1153617 # Number of loads committed -system.cpu1.commit.membars 20508 # Number of memory barriers committed -system.cpu1.commit.branches 821256 # Number of branches committed +system.cpu1.commit.refs 1881487 # Number of memory references committed +system.cpu1.commit.loads 1153406 # Number of loads committed +system.cpu1.commit.membars 20496 # Number of memory barriers committed +system.cpu1.commit.branches 821024 # Number of branches committed system.cpu1.commit.fp_insts 36401 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5437919 # Number of committed integer instructions. -system.cpu1.commit.function_calls 89388 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 157733 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 5437311 # Number of committed integer instructions. +system.cpu1.commit.function_calls 89377 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 157820 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 15919184 # The number of ROB reads -system.cpu1.rob.rob_writes 14457399 # The number of ROB writes -system.cpu1.timesIdled 81947 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 698509 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3784960163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5588724 # Number of Instructions Simulated -system.cpu1.committedInsts_total 5588724 # Number of Instructions Simulated -system.cpu1.cpi 1.783406 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.783406 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.560725 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.560725 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8091693 # number of integer regfile reads -system.cpu1.int_regfile_writes 4410635 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24636 # number of floating regfile reads -system.cpu1.fp_regfile_writes 23087 # number of floating regfile writes -system.cpu1.misc_regfile_reads 284786 # number of misc regfile reads -system.cpu1.misc_regfile_writes 134830 # number of misc regfile writes -system.cpu1.icache.replacements 110610 # number of replacements -system.cpu1.icache.tagsinuse 452.934793 # Cycle average of tags in use -system.cpu1.icache.total_refs 935676 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 111121 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.420335 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874818206000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 452.934793 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.884638 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 935676 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 935676 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 935676 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 15919643 # The number of ROB reads +system.cpu1.rob.rob_writes 14461697 # The number of ROB writes +system.cpu1.timesIdled 81901 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 697375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3784961926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5588082 # Number of Instructions Simulated +system.cpu1.committedInsts_total 5588082 # Number of Instructions Simulated +system.cpu1.cpi 1.783238 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.783238 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.560778 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.560778 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8095217 # number of integer regfile reads +system.cpu1.int_regfile_writes 4412873 # number of integer regfile writes +system.cpu1.fp_regfile_reads 24584 # number of floating regfile reads +system.cpu1.fp_regfile_writes 23091 # number of floating regfile writes +system.cpu1.misc_regfile_reads 284668 # number of misc regfile reads +system.cpu1.misc_regfile_writes 134791 # number of misc regfile writes +system.cpu1.icache.replacements 110606 # number of replacements +system.cpu1.icache.tagsinuse 453.435417 # Cycle average of tags in use +system.cpu1.icache.total_refs 936898 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 111117 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.431635 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874818624000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 453.435417 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.885616 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 936898 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 936898 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 936898 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 935676 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 935676 # number of overall hits +system.cpu1.icache.demand_hits::total 936898 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 936898 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 935676 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 116435 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 116435 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 116435 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 936898 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 116421 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 116421 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 116421 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 116435 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 116435 # number of overall misses +system.cpu1.icache.demand_misses::total 116421 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 116421 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 116435 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 1751730499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 1751730499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 1751730499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 1052111 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1052111 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 1052111 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 116421 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 1750783999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 1750783999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 1750783999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 1053319 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1053319 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 1053319 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1052111 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 1052111 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 1053319 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 1053319 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1052111 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.110668 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.110668 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 1053319 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.110528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.110528 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.110668 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.110528 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.707339 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 15038.386537 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 15044.707339 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 15038.386537 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 15044.707339 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 15038.386537 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 93999 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 96999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7230.692308 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6928.500000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks 37 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 5243 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 5243 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 5243 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 111192 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 111192 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 111192 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits 5236 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 5236 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 5236 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 111185 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 111185 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 111185 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1333669999 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 1333669999 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 1333669999 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 1333353499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 1333353499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 1333353499 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.105685 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.105557 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.105685 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.105557 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.105685 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.105557 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11994.298142 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11992.206674 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11992.206674 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11992.206674 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62429 # number of replacements -system.cpu1.dcache.tagsinuse 392.995073 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1698421 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62755 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 27.064314 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1874613639500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 392.995073 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.767569 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1125916 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1125916 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 549554 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 549554 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 16796 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16796 # number of LoadLockedReq hits +system.cpu1.dcache.replacements 62388 # number of replacements +system.cpu1.dcache.tagsinuse 392.324021 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1699992 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62715 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 27.106625 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1874614053500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 392.324021 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.766258 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 1127254 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1127254 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 549515 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 549515 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 16791 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16791 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::0 14923 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 14923 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 1675470 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::0 1676769 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1675470 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 1675470 # number of overall hits +system.cpu1.dcache.demand_hits::total 1676769 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 1676769 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 1675470 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 106694 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 106694 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 157811 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 157811 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 1480 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1480 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 700 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 700 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 264505 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 1676769 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 106582 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 106582 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 157839 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 157839 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 1481 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1481 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 695 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 695 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 264421 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 264505 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 264505 # number of overall misses +system.cpu1.dcache.demand_misses::total 264421 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 264421 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 264505 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 1790096000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 5171682833 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 19414000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 8395500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 6961778833 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 6961778833 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 1232610 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1232610 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 707365 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 707365 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 18276 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18276 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 15623 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15623 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 1939975 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 264421 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 1787903500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 5181152780 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 19396000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 8380000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 6969056280 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 6969056280 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 1233836 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1233836 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 707354 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 707354 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 18272 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 18272 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 15618 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15618 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 1941190 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1939975 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 1939975 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1941190 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 1941190 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1939975 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.086559 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.223097 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.080981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044806 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.136345 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 1941190 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.086383 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.223140 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.081053 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044500 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.136216 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.136345 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.136216 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 16777.850676 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 16774.910398 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 32771.371026 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 32825.555028 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13117.567568 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13096.556381 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11993.571429 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12057.553957 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 26320.027345 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 26355.910764 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 26320.027345 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 26355.910764 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 86579997 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 86281997 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6823 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6886 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12689.432361 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12530.060558 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 35856 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 62883 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 134026 # number of WriteReq MSHR hits +system.cpu1.dcache.writebacks 35937 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 62835 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 134042 # number of WriteReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits 295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 196909 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 196909 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 43811 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 23785 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1185 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 699 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 67596 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 67596 # number of overall MSHR misses +system.cpu1.dcache.demand_mshr_hits 196877 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 196877 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 43747 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 23797 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1186 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 695 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 67544 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 67544 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 556154000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 752491985 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11636500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6289000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 1308645985 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 1308645985 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 19117500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 320801000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 339918500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035543 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 555340000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 753314485 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6287000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 1308654485 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 1308654485 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 19116500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 320800500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 339917000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035456 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033625 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033642 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064908 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044742 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044500 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.034844 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.034795 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.034844 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.034795 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.391819 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31637.249737 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9819.831224 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8997.138770 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.356184 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31655.859352 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9807.757167 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9046.043165 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19374.844324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19374.844324 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1416,31 +1416,31 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6372 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199307 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71537 40.62% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.13% 40.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1922 1.09% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102421 58.15% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 176125 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70172 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1922 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 199147 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71494 40.63% 40.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 238 0.14% 40.76% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1915 1.09% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102317 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 175972 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70129 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 238 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1915 1.34% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70164 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142503 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1858853057000 97.97% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90805500 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 391568500 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4023000 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38125490000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897464944000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980919 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 70122 49.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142412 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1858860218500 97.97% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90821000 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 390050500 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4014000 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38119760000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897464864000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980907 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685055 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685341 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed @@ -1477,54 +1477,54 @@ system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # nu system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::swpctx 3840 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.16% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169189 91.54% 93.71% # number of callpals executed -system.cpu0.kern.callpal::rdps 6337 3.43% 97.14% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169050 91.54% 93.71% # number of callpals executed +system.cpu0.kern.callpal::rdps 6330 3.43% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rti 4768 2.58% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4761 2.58% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184818 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7264 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1248 # number of protection mode switches +system.cpu0.kern.callpal::total 184665 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7257 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1249 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1247 -system.cpu0.kern.mode_good::user 1248 +system.cpu0.kern.mode_good::kernel 1248 +system.cpu0.kern.mode_good::user 1249 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.171669 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.171972 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895604498000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1860438000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1895601847000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1863009000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3841 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2274 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38564 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10256 33.36% 33.36% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 38551 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10250 33.36% 33.36% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1920 6.25% 39.61% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 105 0.34% 39.95% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18460 60.05% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30741 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10244 45.72% 45.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 8.57% 54.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 105 0.47% 54.75% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10139 45.25% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22408 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871092276500 98.61% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343292500 0.02% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 42130500 0.00% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25986985000 1.37% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897464684500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998830 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_count::31 18453 60.05% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30728 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10238 45.71% 45.71% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 8.57% 54.29% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.47% 54.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10133 45.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22396 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871094081500 98.61% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343283500 0.02% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 42013500 0.00% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25985147000 1.37% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897464525500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998829 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.549242 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.549125 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed @@ -1547,29 +1547,29 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal::swpctx 393 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.30% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26187 82.50% 83.80% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26174 82.49% 83.79% # number of callpals executed system.cpu1.kern.callpal::rdps 2413 7.60% 91.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.41% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.40% # number of callpals executed system.cpu1.kern.callpal::wrusp 5 0.02% 91.42% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 91.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2528 7.96% 99.40% # number of callpals executed +system.cpu1.kern.callpal::rti 2528 7.97% 99.39% # number of callpals executed system.cpu1.kern.callpal::callsys 146 0.46% 99.86% # number of callpals executed system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31743 # number of callpals executed +system.cpu1.kern.callpal::total 31730 # number of callpals executed system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches -system.cpu1.kern.mode_switch::user 492 # number of protection mode switches +system.cpu1.kern.mode_switch::user 491 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 522 -system.cpu1.kern.mode_good::user 492 +system.cpu1.kern.mode_good::kernel 521 +system.cpu1.kern.mode_good::user 491 system.cpu1.kern.mode_good::idle 30 -system.cpu1.kern.mode_switch_good::kernel 0.600690 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.014606 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.615296 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2061638000 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 848590000 0.04% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893876047000 99.85% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 1.614145 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2062444500 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 847773000 0.04% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893876331500 99.85% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 394 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index b0a37466e..c884dc482 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,14 +11,14 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -104,6 +105,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -135,6 +137,7 @@ tracer=system.cpu.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -496,7 +499,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -516,7 +519,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -616,7 +619,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -645,7 +647,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -686,7 +688,6 @@ pio=system.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[1] @@ -768,7 +769,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -785,7 +785,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -802,7 +801,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -819,7 +817,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -836,7 +833,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -853,7 +849,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -870,7 +865,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -887,7 +881,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -904,7 +897,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -921,7 +913,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -938,7 +929,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -955,7 +945,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -972,7 +961,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -989,7 +977,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1006,7 +993,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1023,7 +1009,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1040,7 +1025,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1057,7 +1041,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1074,7 +1057,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1090,7 +1072,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=system.tsunami system=system pio=system.iobus.port[22] @@ -1155,7 +1136,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=system.tsunami system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1166,7 +1146,6 @@ pio=system.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[2] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 2911b29fc..0ab209212 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 06:11:15 -gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Feb 3 2012 13:46:22 +gem5 started Feb 3 2012 13:46:34 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858873594500 because m5_exit instruction encountered +Exiting @ tick 1859850554500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index de8941321..44b3ca581 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858874 # Number of seconds simulated -sim_ticks 1858873594500 # Number of ticks simulated -final_tick 1858873594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859851 # Number of seconds simulated +sim_ticks 1859850554500 # Number of ticks simulated +final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134152 # Simulator instruction rate (inst/s) -host_tick_rate 4696460042 # Simulator tick rate (ticks/s) -host_mem_usage 295432 # Number of bytes of host memory used -host_seconds 395.80 # Real time elapsed on the host -sim_insts 53097697 # Number of instructions simulated -system.physmem.bytes_read 29819840 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1062784 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10193408 # Number of bytes written to this memory -system.physmem.num_reads 465935 # Number of read requests responded to by this memory -system.physmem.num_writes 159272 # Number of write requests responded to by this memory +host_inst_rate 100457 # Simulator instruction rate (inst/s) +host_tick_rate 3519496587 # Simulator tick rate (ticks/s) +host_mem_usage 323652 # Number of bytes of host memory used +host_seconds 528.44 # Real time elapsed on the host +sim_insts 53085804 # Number of instructions simulated +system.physmem.bytes_read 29820864 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10193536 # Number of bytes written to this memory +system.physmem.num_reads 465951 # Number of read requests responded to by this memory +system.physmem.num_writes 159274 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16041887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 571735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5483648 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21525535 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 391354 # number of replacements -system.l2c.tagsinuse 34898.086140 # Cycle average of tags in use -system.l2c.total_refs 2410581 # Total number of references to valid blocks. -system.l2c.sampled_refs 424231 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.682237 # Average number of references to valid blocks. +system.physmem.bw_read 16034011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 572089 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5480836 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 21514847 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 391353 # number of replacements +system.l2c.tagsinuse 34925.820021 # Cycle average of tags in use +system.l2c.total_refs 2406767 # Total number of references to valid blocks. +system.l2c.sampled_refs 424249 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.673006 # Average number of references to valid blocks. system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12293.296692 # Average occupied blocks per context -system.l2c.occ_blocks::1 22604.789448 # Average occupied blocks per context -system.l2c.occ_percent::0 0.187581 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.344922 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1801188 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1801188 # number of ReadReq hits -system.l2c.Writeback_hits::0 835090 # number of Writeback hits -system.l2c.Writeback_hits::total 835090 # number of Writeback hits +system.l2c.occ_blocks::0 12305.465353 # Average occupied blocks per context +system.l2c.occ_blocks::1 22620.354669 # Average occupied blocks per context +system.l2c.occ_percent::0 0.187767 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.345159 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1800764 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits +system.l2c.Writeback_hits::0 835189 # number of Writeback hits +system.l2c.Writeback_hits::total 835189 # number of Writeback hits system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183163 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183163 # number of ReadExReq hits -system.l2c.demand_hits::0 1984351 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 183241 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits +system.l2c.demand_hits::0 1984005 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1984351 # number of demand (read+write) hits -system.l2c.overall_hits::0 1984351 # number of overall hits +system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits +system.l2c.overall_hits::0 1984005 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1984351 # number of overall hits -system.l2c.ReadReq_misses::0 308072 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308072 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 33 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 33 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116926 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116926 # number of ReadExReq misses -system.l2c.demand_misses::0 424998 # number of demand (read+write) misses +system.l2c.overall_hits::total 1984005 # number of overall hits +system.l2c.ReadReq_misses::0 308137 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 35 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116889 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses +system.l2c.demand_misses::0 425026 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424998 # number of demand (read+write) misses -system.l2c.overall_misses::0 424998 # number of overall misses +system.l2c.demand_misses::total 425026 # number of demand (read+write) misses +system.l2c.overall_misses::0 425026 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424998 # number of overall misses -system.l2c.ReadReq_miss_latency 16035098000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6133668000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22168766000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22168766000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2109260 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109260 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 835090 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835090 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 49 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::total 425026 # number of overall misses +system.l2c.ReadReq_miss_latency 16037812500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 424500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6132457500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22170270000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22170270000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2108901 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 835189 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 51 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300089 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300089 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2409349 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::0 300130 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2409031 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2409349 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2409349 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2409031 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2409349 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146057 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.673469 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389638 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176395 # miss rate for demand accesses +system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146113 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.686275 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389461 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176430 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176395 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.176430 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52049.838999 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52047.668732 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 12878.787879 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 12128.571429 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52457.691189 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52463.940148 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52162.047821 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52162.150080 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52162.047821 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52162.150080 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -110,43 +110,43 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117760 # number of writebacks +system.l2c.writebacks 117762 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308072 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116926 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 424998 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 424998 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 308137 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116889 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 425026 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 425026 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12331827500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1380000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4711722000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17043549500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17043549500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 810479000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1115452498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1925931498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146057 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12334071500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1460000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4711233500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17045305000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17045305000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 809589500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1114928998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1924518498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146113 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.673469 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.686275 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389638 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389461 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.176430 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.176430 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40029.043535 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41818.181818 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40296.614953 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40027.882078 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41714.285714 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40305.191250 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -154,13 +154,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.268274 # Cycle average of tags in use +system.iocache.tagsinuse 1.276011 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338694000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.268274 # Average occupied blocks per context -system.iocache.occ_percent::1 0.079267 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.276011 # Average occupied blocks per context +system.iocache.occ_percent::1 0.079751 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -177,10 +177,10 @@ system.iocache.demand_misses::total 41725 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722643806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742583804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742583804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5721891806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741829804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741829804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -200,22 +200,22 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137722.463564 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137704.365759 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137629.330234 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137611.259533 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137629.330234 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137611.259533 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64634068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6174.442874 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -227,10 +227,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561790996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572734994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572734994 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561041984 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571983982 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571983982 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -244,10 +244,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85718.882268 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85700.856373 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -268,22 +268,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10138302 # DTB read hits -system.cpu.dtb.read_misses 46569 # DTB read misses -system.cpu.dtb.read_acv 588 # DTB read access violations -system.cpu.dtb.read_accesses 971478 # DTB read accesses -system.cpu.dtb.write_hits 6627002 # DTB write hits -system.cpu.dtb.write_misses 12216 # DTB write misses -system.cpu.dtb.write_acv 416 # DTB write access violations -system.cpu.dtb.write_accesses 347261 # DTB write accesses -system.cpu.dtb.data_hits 16765304 # DTB hits -system.cpu.dtb.data_misses 58785 # DTB misses -system.cpu.dtb.data_acv 1004 # DTB access violations -system.cpu.dtb.data_accesses 1318739 # DTB accesses -system.cpu.itb.fetch_hits 1327158 # ITB hits -system.cpu.itb.fetch_misses 39816 # ITB misses -system.cpu.itb.fetch_acv 1096 # ITB acv -system.cpu.itb.fetch_accesses 1366974 # ITB accesses +system.cpu.dtb.read_hits 10136178 # DTB read hits +system.cpu.dtb.read_misses 46729 # DTB read misses +system.cpu.dtb.read_acv 584 # DTB read access violations +system.cpu.dtb.read_accesses 970980 # DTB read accesses +system.cpu.dtb.write_hits 6626287 # DTB write hits +system.cpu.dtb.write_misses 12218 # DTB write misses +system.cpu.dtb.write_acv 419 # DTB write access violations +system.cpu.dtb.write_accesses 347267 # DTB write accesses +system.cpu.dtb.data_hits 16762465 # DTB hits +system.cpu.dtb.data_misses 58947 # DTB misses +system.cpu.dtb.data_acv 1003 # DTB access violations +system.cpu.dtb.data_accesses 1318247 # DTB accesses +system.cpu.itb.fetch_hits 1326719 # ITB hits +system.cpu.itb.fetch_misses 39613 # ITB misses +system.cpu.itb.fetch_acv 1063 # ITB acv +system.cpu.itb.fetch_accesses 1366332 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -296,276 +296,276 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 116293341 # number of cpu cycles simulated +system.cpu.numCycles 116271514 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14403200 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12045652 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 530716 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12993662 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6702662 # Number of BTB hits +system.cpu.BPredUnit.lookups 14404381 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12049368 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 531407 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13004312 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6709840 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 972407 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45058 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29094387 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 73505774 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14403200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7675069 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14268794 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2359863 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36645005 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31889 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259043 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335706 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9051868 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 321893 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 82174946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.894503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211429 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 971693 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45037 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29087793 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 73522129 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14404381 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7681533 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14275065 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2363223 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36625670 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 258943 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335385 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 155 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9051216 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 322280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 82158877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.894877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211744 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67906152 82.64% 82.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1023009 1.24% 83.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2022244 2.46% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 965640 1.18% 87.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2953506 3.59% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 686113 0.83% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 790817 0.96% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1067854 1.30% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4759611 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67883812 82.63% 82.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1025449 1.25% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2024221 2.46% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 965546 1.18% 87.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2955118 3.60% 91.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 688428 0.84% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 786197 0.96% 92.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069042 1.30% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4761064 5.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 82174946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123852 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632072 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30353273 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36299982 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13051372 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 972104 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1498214 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 610003 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42096 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 71896046 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128197 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1498214 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31555942 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12820674 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19773044 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12199083 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4327987 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 67967172 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7022 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 504365 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1538985 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 45476353 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 82567749 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 82088652 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479097 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38265070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7211275 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700634 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251496 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12093975 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10722948 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6992313 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1255970 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 835280 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 59689379 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2116105 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57965210 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118570 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8314088 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4277616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1448303 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 82174946 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705388 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.352124 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 82158877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123886 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632331 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30342810 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36285765 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13055396 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 974232 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1500673 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 609120 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42110 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 71910719 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128198 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1500673 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31545269 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12820046 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19759905 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12205401 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4327581 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 67985937 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6903 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504868 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1537776 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 45488593 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 82604485 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 82125154 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479331 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38256265 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7232320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1700161 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251408 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12102195 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10719689 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6992362 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1255856 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 835149 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 59697251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2115237 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57966423 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118182 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8327603 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4293139 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1447692 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 82158877 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.352283 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56717955 69.02% 69.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11192734 13.62% 82.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5489796 6.68% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3501881 4.26% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2637968 3.21% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1562716 1.90% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 689256 0.84% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 274867 0.33% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 107773 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56706238 69.02% 69.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11186331 13.62% 82.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5491014 6.68% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3497852 4.26% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2643618 3.22% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1562284 1.90% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 690020 0.84% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 273664 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 107856 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 82174946 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 82158877 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 67060 8.71% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 379426 49.28% 57.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323507 42.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66675 8.67% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 379311 49.30% 57.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323479 42.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39583689 68.29% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62189 0.11% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10615864 18.31% 86.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6714571 11.58% 98.36% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952373 1.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39589342 68.30% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62143 0.11% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10612322 18.31% 86.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6714161 11.58% 98.36% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 951931 1.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57965210 # Type of FU issued -system.cpu.iq.rate 0.498440 # Inst issue rate -system.cpu.iq.fu_busy_cnt 769993 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013284 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 198301844 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 69800593 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56410393 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692084 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 332994 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328299 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58364794 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363128 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 575597 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57966423 # Type of FU issued +system.cpu.iq.rate 0.498544 # Inst issue rate +system.cpu.iq.fu_busy_cnt 769465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013274 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 198287117 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 69820873 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56409682 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692252 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 333301 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328338 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58365379 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363228 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 574200 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1608607 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14401 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 599018 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1607370 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13516 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14481 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 600235 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18904 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 170936 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 173076 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1498214 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8974617 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 617389 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 65429620 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 865390 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10722948 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6992313 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1869565 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 485054 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15735 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14401 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 385242 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 382803 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 768045 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57270091 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10215279 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 695118 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1500673 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8975371 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 617328 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 65437961 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 865160 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10719689 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6992362 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1868933 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 485175 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15743 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14481 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 386643 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 382870 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 769513 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57271021 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10213321 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 695401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3624136 # number of nop insts executed -system.cpu.iew.exec_refs 16869985 # number of memory reference insts executed -system.cpu.iew.exec_branches 9097351 # Number of branches executed -system.cpu.iew.exec_stores 6654706 # Number of stores executed -system.cpu.iew.exec_rate 0.492462 # Inst execution rate -system.cpu.iew.wb_sent 56872608 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56738692 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28028831 # num instructions producing a value -system.cpu.iew.wb_consumers 37767423 # num instructions consuming a value +system.cpu.iew.exec_nop 3625473 # number of nop insts executed +system.cpu.iew.exec_refs 16867223 # number of memory reference insts executed +system.cpu.iew.exec_branches 9097936 # Number of branches executed +system.cpu.iew.exec_stores 6653902 # Number of stores executed +system.cpu.iew.exec_rate 0.492563 # Inst execution rate +system.cpu.iew.wb_sent 56871872 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56738020 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28030988 # num instructions producing a value +system.cpu.iew.wb_consumers 37770905 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.487893 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742143 # average fanout of values written-back +system.cpu.iew.wb_rate 0.487979 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56292492 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9013620 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667802 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 700532 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80676732 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.697754 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.611305 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80658204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.697762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.611283 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59494729 73.74% 73.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8894659 11.03% 84.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4715834 5.85% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2613071 3.24% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1534221 1.90% 95.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 644957 0.80% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475888 0.59% 97.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 517029 0.64% 97.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1786344 2.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59481462 73.75% 73.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8887876 11.02% 84.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4721135 5.85% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2612091 3.24% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1531941 1.90% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 645193 0.80% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475603 0.59% 97.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 516794 0.64% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1786109 2.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80676732 # Number of insts commited each cycle -system.cpu.commit.count 56292492 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle +system.cpu.commit.count 56280196 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15507636 # Number of memory references committed -system.cpu.commit.loads 9114341 # Number of loads committed -system.cpu.commit.membars 227905 # Number of memory barriers committed -system.cpu.commit.branches 8463183 # Number of branches committed +system.cpu.commit.refs 15504446 # Number of memory references committed +system.cpu.commit.loads 9112319 # Number of loads committed +system.cpu.commit.membars 227818 # Number of memory barriers committed +system.cpu.commit.branches 8461284 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52130666 # Number of committed integer instructions. -system.cpu.commit.function_calls 744656 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1786344 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52119152 # Number of committed integer instructions. +system.cpu.commit.function_calls 744404 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1786109 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 143945413 # The number of ROB reads -system.cpu.rob.rob_writes 132113260 # The number of ROB writes -system.cpu.timesIdled 1256827 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34118395 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3601447413 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53097697 # Number of Instructions Simulated -system.cpu.committedInsts_total 53097697 # Number of Instructions Simulated -system.cpu.cpi 2.190177 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.190177 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456584 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456584 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75078413 # number of integer regfile reads -system.cpu.int_regfile_writes 40965985 # number of integer regfile writes -system.cpu.fp_regfile_reads 166494 # number of floating regfile reads +system.cpu.rob.rob_reads 143937484 # The number of ROB reads +system.cpu.rob.rob_writes 132136289 # The number of ROB writes +system.cpu.timesIdled 1255783 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53085804 # Number of Instructions Simulated +system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated +system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456568 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456568 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75080091 # number of integer regfile reads +system.cpu.int_regfile_writes 40965330 # number of integer regfile writes +system.cpu.fp_regfile_reads 166532 # number of floating regfile reads system.cpu.fp_regfile_writes 167403 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996876 # number of misc regfile reads -system.cpu.misc_regfile_writes 949968 # number of misc regfile writes +system.cpu.misc_regfile_reads 1996306 # number of misc regfile reads +system.cpu.misc_regfile_writes 949674 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -597,231 +597,231 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1004954 # number of replacements -system.cpu.icache.tagsinuse 509.962774 # Cycle average of tags in use -system.cpu.icache.total_refs 7985922 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005463 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.942532 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23358245000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.962774 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.996021 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 7985923 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7985923 # number of ReadReq hits -system.cpu.icache.demand_hits::0 7985923 # number of demand (read+write) hits +system.cpu.icache.replacements 1004588 # number of replacements +system.cpu.icache.tagsinuse 509.963959 # Cycle average of tags in use +system.cpu.icache.total_refs 7985769 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.963959 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.996023 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 7985770 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits +system.cpu.icache.demand_hits::0 7985770 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7985923 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 7985923 # number of overall hits +system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 7985770 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7985923 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1065945 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065945 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1065945 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 7985770 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1065446 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1065446 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065945 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1065945 # number of overall misses +system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1065446 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1065945 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15930410995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15930410995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15930410995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9051868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9051868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9051868 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1065446 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15927822494 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15927822494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15927822494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9051216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9051216 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9051868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9051868 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9051216 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9051868 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.117760 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.117760 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.117713 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.117713 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.117760 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.117713 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14944.871447 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14949.441355 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14944.871447 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14949.441355 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14944.871447 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14949.441355 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1290996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10581.934426 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 235 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 60269 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 60269 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 60269 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005676 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005676 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005676 # number of overall MSHR misses +system.cpu.icache.writebacks 234 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 60134 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 60134 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 60134 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005312 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005312 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005312 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12050431496 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12050431496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12050431496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12047333996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12047333996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12047333996 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111101 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111069 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.111101 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.111069 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.111101 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.111069 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.419284 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.676705 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1403374 # number of replacements -system.cpu.dcache.tagsinuse 511.996006 # Cycle average of tags in use -system.cpu.dcache.total_refs 12090411 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403886 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.612103 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1403406 # number of replacements +system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use +system.cpu.dcache.total_refs 12086534 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.996006 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.996008 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7456106 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7456106 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4221921 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4221921 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192075 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192075 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220104 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220104 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11678027 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 7453772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4220462 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192050 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220033 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11674234 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11678027 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11678027 # number of overall hits +system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11674234 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11678027 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1809770 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1809770 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1936125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1936125 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 22580 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22580 # number of LoadLockedReq misses +system.cpu.dcache.overall_hits::total 11674234 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1809182 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1936475 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 22599 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3745895 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3745657 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3745895 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3745895 # number of overall misses +system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3745657 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3745895 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38933932500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57800126852 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 338100500 # number of LoadLockedReq miss cycles +system.cpu.dcache.overall_misses::total 3745657 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38930236000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57815325976 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 338636000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 96734059352 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 96734059352 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9265876 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9265876 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6158046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6158046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 214655 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214655 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220106 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220106 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15423922 # number of demand (read+write) accesses +system.cpu.dcache.demand_miss_latency 96745561976 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 96745561976 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9262954 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6156937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 214649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220035 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15419891 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15423922 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15423922 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15419891 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15423922 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.195316 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.314406 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105192 # miss rate for LoadLockedReq accesses +system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.195314 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.314519 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105284 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.242863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.242911 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.242863 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.242911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21513.193665 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 21518.142453 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29853.509898 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.963013 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14973.449956 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14984.556839 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25824.017852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25828.729640 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25824.017852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25828.729640 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 917367309 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 193500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 103073 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8900.170840 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24187.500000 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834855 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 722036 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1637277 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5104 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2359313 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2359313 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087734 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298848 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17476 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks 834955 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 721461 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1637588 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5103 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2359049 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2359049 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1087721 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298887 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17496 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386582 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386582 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1386608 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1386608 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24802725500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8508331309 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206132500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24804888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8509686826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206420500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33311056809 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33311056809 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905005000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234795498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2139800498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117391 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency 33314575326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33314575326 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904009500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234178998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2138188498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117427 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048530 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048545 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081414 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081510 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089898 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089923 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089898 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089923 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22802.197504 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28470.430818 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11795.176242 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22804.458588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28471.251095 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.153864 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -829,27 +829,27 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211595 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74877 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 245 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105819 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182823 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73510 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 245 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73514 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149151 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820223133000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94250000 0.01% 97.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 384615500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38170735500 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858872734000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211491 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74854 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.13% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105750 57.87% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182723 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73487 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73489 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149095 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1821211214000 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 93652500 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 383616500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38161211000 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859849694000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981738 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694715 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694931 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -888,29 +888,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175482 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175394 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5217 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5211 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192442 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5953 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.callpal::total 192344 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320343 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320948 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401064 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29154617000 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2680769000 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827037340000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401708 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29148036500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2681917500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1828019732000 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 6f9417ef5..631ad091d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,14 +9,13 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -62,7 +62,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -126,6 +126,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -157,6 +158,7 @@ tracer=system.cpu0.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -580,6 +582,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -611,6 +614,7 @@ tracer=system.cpu1.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -1069,7 +1073,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1111,7 +1114,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -1121,7 +1123,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -1191,7 +1192,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -1203,7 +1203,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -1213,7 +1212,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1242,7 +1240,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -1252,7 +1249,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -1262,7 +1258,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -1275,7 +1270,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -1289,7 +1283,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -1300,7 +1293,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1319,7 +1311,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -1329,7 +1320,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -1338,7 +1328,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -1350,7 +1339,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -1360,7 +1348,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -1370,7 +1357,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -1380,7 +1366,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -1390,7 +1375,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -1404,7 +1388,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -1418,7 +1401,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -1441,7 +1423,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -1451,7 +1432,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -1461,7 +1441,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -1471,7 +1450,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 04178bb32..523f8a126 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -13,6 +13,7 @@ warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 28da0bb31..6780ea1b9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 09:54:17 -gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Feb 3 2012 14:00:40 +gem5 started Feb 3 2012 14:01:00 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582494395500 because m5_exit instruction encountered +Exiting @ tick 2582494330500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 11b3b4098..d8f37781a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.582494 # Number of seconds simulated -sim_ticks 2582494395500 # Number of ticks simulated -final_tick 2582494395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2582494330500 # Number of ticks simulated +final_tick 2582494330500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77486 # Simulator instruction rate (inst/s) -host_tick_rate 2505663009 # Simulator tick rate (ticks/s) -host_mem_usage 386072 # Number of bytes of host memory used -host_seconds 1030.66 # Real time elapsed on the host -sim_insts 79862069 # Number of instructions simulated +host_inst_rate 58235 # Simulator instruction rate (inst/s) +host_tick_rate 1883208568 # Simulator tick rate (ticks/s) +host_mem_usage 413296 # Number of bytes of host memory used +host_seconds 1371.33 # Real time elapsed on the host +sim_insts 79859495 # Number of instructions simulated system.nvmem.bytes_read 384 # Number of bytes read from this memory system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -18,143 +18,143 @@ system.nvmem.num_other 0 # Nu system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 131490980 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1177856 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10251344 # Number of bytes written to this memory -system.physmem.num_reads 15129077 # Number of read requests responded to by this memory -system.physmem.num_writes 870131 # Number of write requests responded to by this memory +system.physmem.bytes_read 131499364 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1184000 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10236688 # Number of bytes written to this memory +system.physmem.num_reads 15129208 # Number of read requests responded to by this memory +system.physmem.num_writes 869902 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 50916269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 456092 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3969551 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 54885821 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 132200 # number of replacements -system.l2c.tagsinuse 27582.989225 # Cycle average of tags in use -system.l2c.total_refs 1817822 # Total number of references to valid blocks. -system.l2c.sampled_refs 162144 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.211158 # Average number of references to valid blocks. +system.physmem.bw_read 50919517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 458471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3963876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 54883393 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 132156 # number of replacements +system.l2c.tagsinuse 27576.843805 # Cycle average of tags in use +system.l2c.total_refs 1820044 # Total number of references to valid blocks. +system.l2c.sampled_refs 162190 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.221678 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 5000.897751 # Average occupied blocks per context -system.l2c.occ_blocks::1 7176.831699 # Average occupied blocks per context -system.l2c.occ_blocks::2 15405.259775 # Average occupied blocks per context -system.l2c.occ_percent::0 0.076308 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.109510 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.235066 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 738573 # number of ReadReq hits -system.l2c.ReadReq_hits::1 628212 # number of ReadReq hits -system.l2c.ReadReq_hits::2 178875 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1545660 # number of ReadReq hits -system.l2c.Writeback_hits::0 598786 # number of Writeback hits -system.l2c.Writeback_hits::total 598786 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 1039 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 1048 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2087 # number of UpgradeReq hits +system.l2c.occ_blocks::0 4997.961622 # Average occupied blocks per context +system.l2c.occ_blocks::1 7175.690427 # Average occupied blocks per context +system.l2c.occ_blocks::2 15403.191755 # Average occupied blocks per context +system.l2c.occ_percent::0 0.076263 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.109492 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.235034 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 739066 # number of ReadReq hits +system.l2c.ReadReq_hits::1 627724 # number of ReadReq hits +system.l2c.ReadReq_hits::2 184257 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1551047 # number of ReadReq hits +system.l2c.Writeback_hits::0 599046 # number of Writeback hits +system.l2c.Writeback_hits::total 599046 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 992 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 1000 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1992 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 175 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 451 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 626 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 58347 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 39083 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 97430 # number of ReadExReq hits -system.l2c.demand_hits::0 796920 # number of demand (read+write) hits -system.l2c.demand_hits::1 667295 # number of demand (read+write) hits -system.l2c.demand_hits::2 178875 # number of demand (read+write) hits -system.l2c.demand_hits::total 1643090 # number of demand (read+write) hits -system.l2c.overall_hits::0 796920 # number of overall hits -system.l2c.overall_hits::1 667295 # number of overall hits -system.l2c.overall_hits::2 178875 # number of overall hits -system.l2c.overall_hits::total 1643090 # number of overall hits -system.l2c.ReadReq_misses::0 19694 # number of ReadReq misses -system.l2c.ReadReq_misses::1 20569 # number of ReadReq misses -system.l2c.ReadReq_misses::2 168 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40431 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 7390 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 3840 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11230 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 864 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 454 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1318 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 97999 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 50217 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148216 # number of ReadExReq misses -system.l2c.demand_misses::0 117693 # number of demand (read+write) misses -system.l2c.demand_misses::1 70786 # number of demand (read+write) misses -system.l2c.demand_misses::2 168 # number of demand (read+write) misses -system.l2c.demand_misses::total 188647 # number of demand (read+write) misses -system.l2c.overall_misses::0 117693 # number of overall misses -system.l2c.overall_misses::1 70786 # number of overall misses -system.l2c.overall_misses::2 168 # number of overall misses -system.l2c.overall_misses::total 188647 # number of overall misses -system.l2c.ReadReq_miss_latency 2112279500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 61500500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 8037000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7780237999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9892517499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9892517499 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 758267 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 648781 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 179043 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1586091 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 598786 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 598786 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 8429 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4888 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13317 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 1039 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 905 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1944 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 156346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 89300 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245646 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 914613 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 738081 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 179043 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1831737 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 914613 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 738081 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 179043 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1831737 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025972 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.031704 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.000938 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.058615 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.876735 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.785597 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.831569 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.501657 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.626808 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.562340 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.128681 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.095905 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.000938 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.225524 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.128681 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.095905 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.000938 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.225524 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 107254.976135 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 102692.376878 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 12573092.261905 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12783039.614917 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8322.124493 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 16015.755208 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_hits::1 443 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 618 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 58603 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 38925 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 97528 # number of ReadExReq hits +system.l2c.demand_hits::0 797669 # number of demand (read+write) hits +system.l2c.demand_hits::1 666649 # number of demand (read+write) hits +system.l2c.demand_hits::2 184257 # number of demand (read+write) hits +system.l2c.demand_hits::total 1648575 # number of demand (read+write) hits +system.l2c.overall_hits::0 797669 # number of overall hits +system.l2c.overall_hits::1 666649 # number of overall hits +system.l2c.overall_hits::2 184257 # number of overall hits +system.l2c.overall_hits::total 1648575 # number of overall hits +system.l2c.ReadReq_misses::0 19787 # number of ReadReq misses +system.l2c.ReadReq_misses::1 20563 # number of ReadReq misses +system.l2c.ReadReq_misses::2 170 # number of ReadReq misses +system.l2c.ReadReq_misses::total 40520 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 7351 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 3816 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11167 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 849 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 448 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1297 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 97885 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 50394 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 148279 # number of ReadExReq misses +system.l2c.demand_misses::0 117672 # number of demand (read+write) misses +system.l2c.demand_misses::1 70957 # number of demand (read+write) misses +system.l2c.demand_misses::2 170 # number of demand (read+write) misses +system.l2c.demand_misses::total 188799 # number of demand (read+write) misses +system.l2c.overall_misses::0 117672 # number of overall misses +system.l2c.overall_misses::1 70957 # number of overall misses +system.l2c.overall_misses::2 170 # number of overall misses +system.l2c.overall_misses::total 188799 # number of overall misses +system.l2c.ReadReq_miss_latency 2117109000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 60330000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 7673500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7779101999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9896210999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9896210999 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 758853 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 648287 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 184427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1591567 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 599046 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 599046 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 8343 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4816 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13159 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 1024 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 891 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1915 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 156488 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 89319 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245807 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 915341 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 737606 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 184427 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1837374 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 915341 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 737606 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 184427 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1837374 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026075 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.031719 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.000922 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.058716 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.881098 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.792359 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.829102 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.502806 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.625511 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.564202 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.128555 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.096199 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.000922 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.225676 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.128555 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.096199 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.000922 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.225676 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 106994.946177 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 102957.204688 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 12453582.352941 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12663534.503806 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 8207.046660 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 15809.748428 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 9302.083333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 17702.643172 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 9038.280330 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 17128.348214 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 79390.993775 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 154932.353566 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 79471.849609 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 154365.638747 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 84053.575820 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 139752.458099 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 58884032.732143 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 59107838.766062 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 84053.575820 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 139752.458099 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 58884032.732143 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 59107838.766062 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 84099.964299 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 139467.719873 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 58213005.876471 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 58436573.560642 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 84099.964299 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 139467.719873 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 58213005.876471 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 58436573.560642 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -163,56 +163,56 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 112847 # number of writebacks -system.l2c.ReadReq_mshr_hits 98 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 98 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 98 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 40333 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 11230 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1318 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 148216 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 188549 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 188549 # number of overall MSHR misses +system.l2c.writebacks 112618 # number of writebacks +system.l2c.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 97 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 97 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 40423 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 11167 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 1297 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 148279 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 188702 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 188702 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1616144000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 449664000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 52753500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5939088499 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7555232499 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7555232499 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131965191500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32542078084 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164507269584 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.053191 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.062167 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 0.225270 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.340628 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.332305 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.297463 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1619864500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 446963000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 51939000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5941339999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7561204499 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7561204499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131964916000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32535008680 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164499924680 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.053269 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.062354 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.219182 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.334804 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.338487 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.318729 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.268527 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.456354 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.266602 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.455668 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.948000 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 1.659754 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.947542 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 1.660106 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.206152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.255458 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.053093 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.514703 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.206152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.255458 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.053093 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.514703 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40070.017108 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40041.317898 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40025.417299 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40070.495082 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.206155 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.255830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.023180 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.485165 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.206155 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.255830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.023180 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.485165 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40072.842194 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40025.342527 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40045.489591 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40068.654354 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40069.551457 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40069.551457 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -227,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 42404013 # DTB read hits -system.cpu0.dtb.read_misses 55271 # DTB read misses -system.cpu0.dtb.write_hits 6896316 # DTB write hits -system.cpu0.dtb.write_misses 11117 # DTB write misses +system.cpu0.dtb.read_hits 42410626 # DTB read hits +system.cpu0.dtb.read_misses 55840 # DTB read misses +system.cpu0.dtb.write_hits 6900244 # DTB write hits +system.cpu0.dtb.write_misses 11203 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 2702 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 10190 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 580 # Number of TLB faults due to prefetch +system.cpu0.dtb.align_faults 9414 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 598 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 1489 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 42459284 # DTB read accesses -system.cpu0.dtb.write_accesses 6907433 # DTB write accesses +system.cpu0.dtb.perms_faults 1544 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 42466466 # DTB read accesses +system.cpu0.dtb.write_accesses 6911447 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 49300329 # DTB hits -system.cpu0.dtb.misses 66388 # DTB misses -system.cpu0.dtb.accesses 49366717 # DTB accesses -system.cpu0.itb.inst_hits 6430047 # ITB inst hits -system.cpu0.itb.inst_misses 17344 # ITB inst misses +system.cpu0.dtb.hits 49310870 # DTB hits +system.cpu0.dtb.misses 67043 # DTB misses +system.cpu0.dtb.accesses 49377913 # DTB accesses +system.cpu0.itb.inst_hits 6428492 # ITB inst hits +system.cpu0.itb.inst_misses 17283 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -256,121 +256,121 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1577 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1596 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 5810 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 5840 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6447391 # ITB inst accesses -system.cpu0.itb.hits 6430047 # DTB hits -system.cpu0.itb.misses 17344 # DTB misses -system.cpu0.itb.accesses 6447391 # DTB accesses -system.cpu0.numCycles 352464224 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6445775 # ITB inst accesses +system.cpu0.itb.hits 6428492 # DTB hits +system.cpu0.itb.misses 17283 # DTB misses +system.cpu0.itb.accesses 6445775 # DTB accesses +system.cpu0.numCycles 352483912 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 8639262 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 6396113 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 634960 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 7354016 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5046946 # Number of BTB hits +system.cpu0.BPredUnit.lookups 8645116 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 6399988 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 634817 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7331445 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5034787 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 806008 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 135144 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16864575 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45911459 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 8639262 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5852954 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11507352 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2656909 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 105092 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 79183942 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 2005 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 114543 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 115021 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6424056 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 290090 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 8736 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 109741052 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.540842 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.794710 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 805074 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 135243 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 16860833 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45928818 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 8645116 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5839861 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11494054 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2657796 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 106861 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 79215676 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 7529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 114865 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 114660 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6422476 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 290012 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 8748 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 109764102 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.540930 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.795930 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 98251365 89.53% 89.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 1141553 1.04% 90.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1483062 1.35% 91.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1305311 1.19% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1111109 1.01% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 877492 0.80% 94.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 783730 0.71% 95.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 504789 0.46% 96.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4282641 3.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98288129 89.54% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 1143186 1.04% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1488169 1.36% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1267497 1.15% 93.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1112191 1.01% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 871683 0.79% 94.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 797932 0.73% 95.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 504639 0.46% 96.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4290676 3.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 109741052 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.024511 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.130258 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18015904 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78867966 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10351735 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 744902 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1760545 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1349765 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89024 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56859019 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 296865 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1760545 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 19077781 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 33324855 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 41068350 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10047301 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4462220 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54490886 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1483 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 580883 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 3149232 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 205 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54779837 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 247536349 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 247487579 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48770 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 41441157 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13338679 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 828868 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 763855 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8500592 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 11770384 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7686805 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1443183 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1570137 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50961905 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1297752 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 80276174 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 137636 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9888896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22816025 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 253324 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 109741052 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.731505 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.440076 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 109764102 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.024526 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.130300 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18029022 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78891581 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10335231 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 746808 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1761460 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1349167 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89318 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56878279 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 297096 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1761460 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 19090042 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 33342572 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 41068842 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10032499 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4468687 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54513639 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1476 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 586863 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 3152149 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 190 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 54798998 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 247626093 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 247578647 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47446 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 41436679 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13362318 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 827066 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 763098 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8512546 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 11778849 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7693096 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1451709 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1599658 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50981510 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1297142 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 80275629 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 138322 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9920481 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22908706 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 252718 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 109764102 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.731347 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.440423 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 80125799 73.01% 73.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10111373 9.21% 82.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4133530 3.77% 85.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3177611 2.90% 88.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 9954078 9.07% 97.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1265279 1.15% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 670333 0.61% 99.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224189 0.20% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 78860 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 80151995 73.02% 73.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10117120 9.22% 82.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4139720 3.77% 86.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3156304 2.88% 88.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 9950540 9.07% 97.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1264670 1.15% 99.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 681180 0.62% 99.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 223017 0.20% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 79556 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 109741052 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 109764102 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 37808 0.47% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 38058 0.47% 0.47% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 626 0.01% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available @@ -399,374 +399,378 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 7704393 95.96% 96.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 285533 3.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 7704046 95.93% 96.41% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 287948 3.59% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 88461 0.11% 0.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29731481 37.04% 37.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 62351 0.08% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 4 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1694 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 43135014 53.73% 90.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 7257159 9.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 88478 0.11% 0.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29722864 37.03% 37.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 62274 0.08% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 3 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1682 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 43138789 53.74% 90.95% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 7261531 9.05% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 80276174 # Type of FU issued -system.cpu0.iq.rate 0.227757 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 8028360 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.100009 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 278513864 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62161443 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 46668615 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11568 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6980 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5172 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 88210042 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6031 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 399886 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 80275629 # Type of FU issued +system.cpu0.iq.rate 0.227743 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8030678 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.100039 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 278539843 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62212125 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 46665965 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11176 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6795 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5030 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 88212004 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5825 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 398434 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2526229 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 5188 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20554 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 993550 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2535542 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 5119 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20483 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1000305 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 32220160 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 13300 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 32220121 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 13276 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1760545 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 25952608 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 355602 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 52433539 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 243567 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 11770384 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7686805 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 865740 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 62160 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5553 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20554 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 507509 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 136100 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 643609 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 79551295 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 42843907 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 724879 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1761460 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 25970226 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 355776 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 52452605 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 244534 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 11778849 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7693096 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 864933 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 62296 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5639 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20483 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 506934 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 135852 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 642786 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 79552569 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 42849690 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 723060 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 173882 # number of nop insts executed -system.cpu0.iew.exec_refs 50011427 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6433542 # Number of branches executed -system.cpu0.iew.exec_stores 7167520 # Number of stores executed -system.cpu0.iew.exec_rate 0.225700 # Inst execution rate -system.cpu0.iew.wb_sent 79133797 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 46673787 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24793926 # num instructions producing a value -system.cpu0.iew.wb_consumers 46078393 # num instructions consuming a value +system.cpu0.iew.exec_nop 173953 # number of nop insts executed +system.cpu0.iew.exec_refs 50020846 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6431362 # Number of branches executed +system.cpu0.iew.exec_stores 7171156 # Number of stores executed +system.cpu0.iew.exec_rate 0.225691 # Inst execution rate +system.cpu0.iew.wb_sent 79131384 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 46670995 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24791862 # num instructions producing a value +system.cpu0.iew.wb_consumers 46093474 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.132421 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.538081 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.132406 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.537861 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 41927345 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 10365163 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1044428 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 567784 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 108024119 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.388129 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.248779 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 41923639 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 10377261 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1044424 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 567428 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 108046246 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.388016 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.248887 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 90994296 84.24% 84.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 9318293 8.63% 92.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2453548 2.27% 95.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1344047 1.24% 96.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1036100 0.96% 97.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 648919 0.60% 97.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 654404 0.61% 98.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 241700 0.22% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1332812 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 91022248 84.24% 84.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 9317978 8.62% 92.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2446901 2.26% 95.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1345942 1.25% 96.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1037116 0.96% 97.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 636722 0.59% 97.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 665653 0.62% 98.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 241447 0.22% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1332239 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 108024119 # Number of insts commited each cycle -system.cpu0.commit.count 41927345 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 108046246 # Number of insts commited each cycle +system.cpu0.commit.count 41923639 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 15937410 # Number of memory references committed -system.cpu0.commit.loads 9244155 # Number of loads committed -system.cpu0.commit.membars 288635 # Number of memory barriers committed -system.cpu0.commit.branches 5542672 # Number of branches committed -system.cpu0.commit.fp_insts 4916 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37173454 # Number of committed integer instructions. -system.cpu0.commit.function_calls 620264 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1332812 # number cycles where commit BW limit reached +system.cpu0.commit.refs 15936098 # Number of memory references committed +system.cpu0.commit.loads 9243307 # Number of loads committed +system.cpu0.commit.membars 288653 # Number of memory barriers committed +system.cpu0.commit.branches 5542289 # Number of branches committed +system.cpu0.commit.fp_insts 4852 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 37169940 # Number of committed integer instructions. +system.cpu0.commit.function_calls 620184 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1332239 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 157900366 # The number of ROB reads -system.cpu0.rob.rob_writes 106355397 # The number of ROB writes -system.cpu0.timesIdled 1453890 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 242723172 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 4812468828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41801518 # Number of Instructions Simulated -system.cpu0.committedInsts_total 41801518 # Number of Instructions Simulated -system.cpu0.cpi 8.431852 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.431852 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.118598 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.118598 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 354175079 # number of integer regfile reads -system.cpu0.int_regfile_writes 46137251 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4205 # number of floating regfile reads -system.cpu0.fp_regfile_writes 1348 # number of floating regfile writes -system.cpu0.misc_regfile_reads 65629786 # number of misc regfile reads -system.cpu0.misc_regfile_writes 635954 # number of misc regfile writes -system.cpu0.icache.replacements 539173 # number of replacements -system.cpu0.icache.tagsinuse 511.623608 # Cycle average of tags in use -system.cpu0.icache.total_refs 5839899 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 539685 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.820940 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 16020223000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.623608 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.999265 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 5839899 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5839899 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 5839899 # number of demand (read+write) hits +system.cpu0.rob.rob_reads 157931724 # The number of ROB reads +system.cpu0.rob.rob_writes 106372981 # The number of ROB writes +system.cpu0.timesIdled 1454145 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 242719810 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 4812449027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41797812 # Number of Instructions Simulated +system.cpu0.committedInsts_total 41797812 # Number of Instructions Simulated +system.cpu0.cpi 8.433071 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.433071 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.118581 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.118581 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 354190813 # number of integer regfile reads +system.cpu0.int_regfile_writes 46128461 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3999 # number of floating regfile reads +system.cpu0.fp_regfile_writes 1336 # number of floating regfile writes +system.cpu0.misc_regfile_reads 65704114 # number of misc regfile reads +system.cpu0.misc_regfile_writes 635920 # number of misc regfile writes +system.cpu0.icache.replacements 538787 # number of replacements +system.cpu0.icache.tagsinuse 511.612990 # Cycle average of tags in use +system.cpu0.icache.total_refs 5838964 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 539299 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 10.826951 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 16020224000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 511.612990 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.999244 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 5838964 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5838964 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 5838964 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5839899 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 5839899 # number of overall hits +system.cpu0.icache.demand_hits::total 5838964 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 5838964 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 5839899 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 584029 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 584029 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 584029 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 5838964 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 583385 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 583385 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 583385 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 584029 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 584029 # number of overall misses +system.cpu0.icache.demand_misses::total 583385 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 583385 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 584029 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 8742056490 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 8742056490 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 8742056490 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 6423928 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6423928 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 6423928 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 583385 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 8740145988 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 8740145988 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 8740145988 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 6422349 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6422349 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 6422349 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6423928 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 6423928 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 6422349 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 6422349 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6423928 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.090915 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.090915 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 6422349 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.090837 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.090837 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.090915 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.090837 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14968.531511 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14981.780450 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14968.531511 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14981.780450 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14968.531511 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14981.780450 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1586493 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1633991 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 210 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 240 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7554.728571 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 6808.295833 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 29902 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 44323 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 44323 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 44323 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 539706 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 539706 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 539706 # number of overall MSHR misses +system.cpu0.icache.writebacks 29665 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 44065 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 44065 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 44065 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 539320 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 539320 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 539320 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 6552393493 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 6552393493 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 6552393493 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 6552239991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 6552239991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 6552239991 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.084015 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.083976 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.084015 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.083976 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.084015 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.083976 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12140.671945 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12140.671945 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12140.671945 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12149.076598 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 372215 # number of replacements -system.cpu0.dcache.tagsinuse 487.071305 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12774859 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 372727 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.274037 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 372182 # number of replacements +system.cpu0.dcache.tagsinuse 487.975562 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12779920 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 372694 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.290651 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 487.071305 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.951311 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7959466 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7959466 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 4347928 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4347928 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 221270 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 221270 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 199751 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199751 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12307394 # number of demand (read+write) hits +system.cpu0.dcache.occ_blocks::0 487.992960 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -0.017397 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.953111 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::1 -0.000034 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::0 7966835 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7966835 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 4346487 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4346487 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 221211 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 221211 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 199868 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199868 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 12313322 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12307394 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12307394 # number of overall hits +system.cpu0.dcache.demand_hits::total 12313322 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 12313322 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 12307394 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 462880 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 462880 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1863380 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1863380 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 9956 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9956 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 7770 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7770 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 2326260 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 12313322 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 463412 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 463412 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1864293 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1864293 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 10042 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10042 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 7686 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7686 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 2327705 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2326260 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 2326260 # number of overall misses +system.cpu0.dcache.demand_misses::total 2327705 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 2327705 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2326260 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 6451753000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 70471171342 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 120838000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 88450500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 76922924342 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 76922924342 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8422346 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8422346 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 6211308 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6211308 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 231226 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 231226 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 207521 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 207521 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14633654 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 2327705 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 6478995500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 70420524827 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 122158000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 87202500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 76899520327 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 76899520327 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8430247 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8430247 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 6210780 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6210780 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 231253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 231253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 207554 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 207554 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14641027 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14633654 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14633654 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14641027 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14641027 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14633654 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.054959 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.299998 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043057 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037442 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.158966 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14641027 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.054970 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.300171 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043424 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037031 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.158985 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.158966 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.158985 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 13938.284221 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 13981.069761 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 37819.001675 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 37773.313973 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12137.203696 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12164.708225 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11383.590734 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11345.628415 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 33067.208456 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 33036.626345 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 33067.208456 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 33036.626345 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6759989 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1802000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 868 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 123 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7788.005760 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 14650.406504 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 6780486 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1857500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 854 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7939.679157 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 14511.718750 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 326934 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 223096 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1684995 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 326 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1908091 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1908091 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 239784 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 178385 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9630 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 7769 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 418169 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 418169 # number of overall MSHR misses +system.cpu0.dcache.writebacks 327766 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 223882 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1685987 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 318 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1909869 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1909869 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 239530 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 178306 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9724 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 7685 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 417836 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 417836 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2937322500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6377417488 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 86877000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 65112500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 9314739988 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 9314739988 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959379000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038732984 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 139998111984 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028470 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 2943060000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6370530485 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 87975000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 64109000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 9313590485 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 9313590485 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138958680000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038766498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 139997446498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028413 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028719 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028709 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041648 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.042049 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037437 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.028576 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.028539 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.028576 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.028539 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12249.868632 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35750.861833 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9021.495327 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8381.065774 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12286.811673 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35728.076930 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9047.202797 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8342.094990 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -775,27 +779,27 @@ system.cpu0.dcache.soft_prefetch_mshr_full 0 # system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10573739 # DTB read hits -system.cpu1.dtb.read_misses 42015 # DTB read misses -system.cpu1.dtb.write_hits 5529871 # DTB write hits -system.cpu1.dtb.write_misses 15191 # DTB write misses +system.cpu1.dtb.read_hits 10576968 # DTB read hits +system.cpu1.dtb.read_misses 41875 # DTB read misses +system.cpu1.dtb.write_hits 5530754 # DTB write hits +system.cpu1.dtb.write_misses 15302 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1927 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3403 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1929 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3229 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10615754 # DTB read accesses -system.cpu1.dtb.write_accesses 5545062 # DTB write accesses +system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10618843 # DTB read accesses +system.cpu1.dtb.write_accesses 5546056 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16103610 # DTB hits -system.cpu1.dtb.misses 57206 # DTB misses -system.cpu1.dtb.accesses 16160816 # DTB accesses -system.cpu1.itb.inst_hits 8206065 # ITB inst hits -system.cpu1.itb.inst_misses 3031 # ITB inst misses +system.cpu1.dtb.hits 16107722 # DTB hits +system.cpu1.dtb.misses 57177 # DTB misses +system.cpu1.dtb.accesses 16164899 # DTB accesses +system.cpu1.itb.inst_hits 8214514 # ITB inst hits +system.cpu1.itb.inst_misses 3039 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -804,517 +808,517 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1367 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1364 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2156 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2090 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8209096 # ITB inst accesses -system.cpu1.itb.hits 8206065 # DTB hits -system.cpu1.itb.misses 3031 # DTB misses -system.cpu1.itb.accesses 8209096 # DTB accesses -system.cpu1.numCycles 69056369 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8217553 # ITB inst accesses +system.cpu1.itb.hits 8214514 # DTB hits +system.cpu1.itb.misses 3039 # DTB misses +system.cpu1.itb.accesses 8217553 # DTB accesses +system.cpu1.numCycles 69079827 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 8325282 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 6737041 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 502555 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7261407 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5699060 # Number of BTB hits +system.cpu1.BPredUnit.lookups 8333886 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 6743827 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 503378 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7264644 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5697386 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 682916 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 107380 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 17608500 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62544782 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8325282 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6381976 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13909998 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4633998 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 45331 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 15806576 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 3075 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 32937 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 125179 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8203545 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 759342 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1683 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 50660963 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.494360 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.745003 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 681249 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 107003 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 17615974 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 62597753 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8333886 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6378635 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13915716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4638538 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 47230 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 15838358 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 6458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 32444 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 124703 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8212062 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 760593 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1708 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 50714542 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.493810 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.745034 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 36758800 72.56% 72.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 702781 1.39% 73.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1220162 2.41% 76.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2515175 4.96% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1141377 2.25% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 650709 1.28% 84.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1886656 3.72% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 404310 0.80% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5380993 10.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 36806671 72.58% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 703817 1.39% 73.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1220981 2.41% 76.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2510265 4.95% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1144946 2.26% 83.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 645263 1.27% 84.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1889491 3.73% 88.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 406577 0.80% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5386531 10.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 50660963 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.120558 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.905706 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 18651451 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16071797 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12503703 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 383683 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3050329 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1080503 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 80301 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69737045 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 259727 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3050329 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 19796555 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3624603 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 10867059 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11733074 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1589343 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 63809564 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2981 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 320281 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 864112 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 38202 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 68239803 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 296124940 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 296072200 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52740 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39106608 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 29133195 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 434621 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 382462 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4203927 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11080202 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7013216 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 634211 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 885799 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 56015216 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 652114 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 50333331 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 120412 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18201885 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52559759 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 132486 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 50660963 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.993533 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.617126 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 50714542 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.120641 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.906165 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18659331 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16106637 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12510231 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 383783 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3054560 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1080138 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 80287 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69798471 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 258266 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3054560 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 19806381 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3656042 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 10855578 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11745212 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1596769 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 63854983 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3125 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 323865 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 877546 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 38196 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 68287616 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 296328670 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 296276198 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52472 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39108035 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 29179581 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 433573 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 381926 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4171821 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 11087265 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7018828 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 641698 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 916656 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 56054776 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 651703 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 50356280 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 119136 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18241893 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52675305 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 132202 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 50714542 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.992936 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.616562 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 32144545 63.45% 63.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5530112 10.92% 74.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3775848 7.45% 81.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3605586 7.12% 88.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2986827 5.90% 94.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1557942 3.08% 97.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 784538 1.55% 99.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 214001 0.42% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61564 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 32179059 63.45% 63.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5535325 10.91% 74.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3792419 7.48% 81.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3611748 7.12% 88.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2992147 5.90% 94.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1532229 3.02% 97.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 792020 1.56% 99.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 217740 0.43% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61855 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 50660963 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 50714542 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 15475 1.52% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1190 0.12% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 748820 73.38% 75.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 254917 24.98% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 15740 1.54% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1188 0.12% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 747449 73.17% 74.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 257163 25.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 32741822 65.05% 65.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 50334 0.10% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11609954 23.07% 88.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5911828 11.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32754833 65.05% 65.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 50290 0.10% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 11616605 23.07% 88.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5915163 11.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 50333331 # Type of FU issued -system.cpu1.iq.rate 0.728873 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1020402 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020273 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 152512648 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 74873900 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 44249478 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12744 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7082 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5800 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 51328452 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6659 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 264599 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 50356280 # Type of FU issued +system.cpu1.iq.rate 0.728958 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1021540 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020286 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 152611934 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 74953147 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 44267008 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12764 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7028 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5816 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 51352530 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6668 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 264404 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3968304 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7379 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 12210 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1474293 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3974504 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7309 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 12272 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1480206 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 1850149 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1139663 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 1850099 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1138705 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3050329 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2505738 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 70750 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 56718238 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 255272 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11080202 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7013216 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 408861 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28043 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3317 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 12210 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 383709 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 125709 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 509418 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 47546383 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10844490 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2786948 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3054560 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2510034 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 71099 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 56757065 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 253770 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 11087265 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7018828 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 408322 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 28335 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3451 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 12272 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 384395 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 124639 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 509034 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 47564456 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10848097 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2791824 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 50908 # number of nop insts executed -system.cpu1.iew.exec_refs 16665607 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5805305 # Number of branches executed -system.cpu1.iew.exec_stores 5821117 # Number of stores executed -system.cpu1.iew.exec_rate 0.688516 # Inst execution rate -system.cpu1.iew.wb_sent 46287732 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 44255278 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24264943 # num instructions producing a value -system.cpu1.iew.wb_consumers 44435618 # num instructions consuming a value +system.cpu1.iew.exec_nop 50586 # number of nop insts executed +system.cpu1.iew.exec_refs 16669887 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5808702 # Number of branches executed +system.cpu1.iew.exec_stores 5821790 # Number of stores executed +system.cpu1.iew.exec_rate 0.688543 # Inst execution rate +system.cpu1.iew.wb_sent 46305936 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 44272824 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24255669 # num instructions producing a value +system.cpu1.iew.wb_consumers 44425528 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.640857 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.546070 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.640894 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545985 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38085105 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18540440 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 519628 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 449695 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 47651856 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.799237 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.835547 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38086237 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 18573771 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 519501 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 450480 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 47701192 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.798434 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.833708 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 34686600 72.79% 72.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6094128 12.79% 85.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1835097 3.85% 89.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 960943 2.02% 91.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 825753 1.73% 93.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 740854 1.55% 94.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 593786 1.25% 95.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 449604 0.94% 96.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1465091 3.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 34720154 72.79% 72.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6104752 12.80% 85.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1842443 3.86% 89.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 962149 2.02% 91.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 825618 1.73% 93.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 737310 1.55% 94.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 600667 1.26% 96.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 447664 0.94% 96.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1460435 3.06% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 47651856 # Number of insts commited each cycle -system.cpu1.commit.count 38085105 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 47701192 # Number of insts commited each cycle +system.cpu1.commit.count 38086237 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 12650821 # Number of memory references committed -system.cpu1.commit.loads 7111898 # Number of loads committed -system.cpu1.commit.membars 148710 # Number of memory barriers committed -system.cpu1.commit.branches 4804442 # Number of branches committed +system.cpu1.commit.refs 12651383 # Number of memory references committed +system.cpu1.commit.loads 7112761 # Number of loads committed +system.cpu1.commit.membars 148646 # Number of memory barriers committed +system.cpu1.commit.branches 4805168 # Number of branches committed system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34027730 # Number of committed integer instructions. -system.cpu1.commit.function_calls 433273 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1465091 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 34028190 # Number of committed integer instructions. +system.cpu1.commit.function_calls 433251 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1460435 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 102053926 # The number of ROB reads -system.cpu1.rob.rob_writes 116420763 # The number of ROB writes -system.cpu1.timesIdled 449905 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18395406 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5095165422 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38060551 # Number of Instructions Simulated -system.cpu1.committedInsts_total 38060551 # Number of Instructions Simulated -system.cpu1.cpi 1.814382 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.814382 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.551152 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.551152 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 222777169 # number of integer regfile reads -system.cpu1.int_regfile_writes 47147395 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4225 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1812 # number of floating regfile writes -system.cpu1.misc_regfile_reads 77230796 # number of misc regfile reads -system.cpu1.misc_regfile_writes 323252 # number of misc regfile writes -system.cpu1.icache.replacements 485904 # number of replacements -system.cpu1.icache.tagsinuse 498.788757 # Cycle average of tags in use -system.cpu1.icache.total_refs 7675789 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 486416 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 15.780297 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74237229000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.788757 # Average occupied blocks per context +system.cpu1.rob.rob_reads 102142645 # The number of ROB reads +system.cpu1.rob.rob_writes 116493771 # The number of ROB writes +system.cpu1.timesIdled 450197 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18365285 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5095139417 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38061683 # Number of Instructions Simulated +system.cpu1.committedInsts_total 38061683 # Number of Instructions Simulated +system.cpu1.cpi 1.814944 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.814944 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550981 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550981 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 222861231 # number of integer regfile reads +system.cpu1.int_regfile_writes 47167724 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4217 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes +system.cpu1.misc_regfile_reads 77318861 # number of misc regfile reads +system.cpu1.misc_regfile_writes 323177 # number of misc regfile writes +system.cpu1.icache.replacements 485586 # number of replacements +system.cpu1.icache.tagsinuse 498.788681 # Cycle average of tags in use +system.cpu1.icache.total_refs 7684975 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 486098 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 15.809518 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74234723000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 498.788681 # Average occupied blocks per context system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 7675789 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7675789 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 7675789 # number of demand (read+write) hits +system.cpu1.icache.ReadReq_hits::0 7684975 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7684975 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 7684975 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7675789 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 7675789 # number of overall hits +system.cpu1.icache.demand_hits::total 7684975 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 7684975 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 7675789 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 527703 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 527703 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 527703 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 7684975 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 527035 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 527035 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 527035 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 527703 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 527703 # number of overall misses +system.cpu1.icache.demand_misses::total 527035 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 527035 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 527703 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7760328997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7760328997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7760328997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 8203492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8203492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 8203492 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 527035 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7752735997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7752735997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7752735997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 8212010 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8212010 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 8212010 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8203492 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 8203492 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 8212010 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 8212010 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8203492 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.064327 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.064327 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 8212010 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.064179 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.064179 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.064327 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.064179 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14705.864846 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 14710.097047 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14705.864846 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 14710.097047 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14705.864846 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 14710.097047 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1243497 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 1321997 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 170 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7446.089820 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7776.452941 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 18536 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 41257 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 41257 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 41257 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 486446 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 486446 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 486446 # number of overall MSHR misses +system.cpu1.icache.writebacks 18538 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 40914 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 40914 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 40914 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 486121 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 486121 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 486121 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5802515997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5802515997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5802515997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5799471497 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5799471497 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5799471497 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059297 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059196 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.059297 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.059196 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.059297 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.059196 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11928.386701 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11930.098673 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 272184 # number of replacements -system.cpu1.dcache.tagsinuse 444.922817 # Cycle average of tags in use -system.cpu1.dcache.total_refs 10410516 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 272526 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 38.200084 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 66749899000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 444.922817 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.868990 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 7080702 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7080702 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 3139041 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3139041 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 75297 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 75297 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 72589 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72589 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 10219743 # number of demand (read+write) hits +system.cpu1.dcache.replacements 272200 # number of replacements +system.cpu1.dcache.tagsinuse 447.953212 # Cycle average of tags in use +system.cpu1.dcache.total_refs 10416163 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 272587 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 38.212252 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 66688833000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 447.953212 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.874909 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 7085363 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7085363 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 3139669 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3139669 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 75360 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 75360 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 72622 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72622 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 10225032 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10219743 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 10219743 # number of overall hits +system.cpu1.dcache.demand_hits::total 10225032 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 10225032 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 10219743 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 323641 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 323641 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 1274421 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1274421 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 12692 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12692 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 11088 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 11088 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 1598062 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 10225032 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 323287 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 323287 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 1273508 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1273508 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 12669 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 12669 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 11046 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 11046 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 1596795 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1598062 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 1598062 # number of overall misses +system.cpu1.dcache.demand_misses::total 1596795 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 1596795 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 1598062 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 5056918000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 46262292366 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 147873000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 87994000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 51319210366 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 51319210366 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 7404343 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7404343 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 4413462 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4413462 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 87989 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87989 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 83677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 11817805 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 1596795 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 5044696500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 46343696337 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 148164500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 87512500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 51388392837 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 51388392837 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 7408650 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7408650 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 4413177 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4413177 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 88029 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 88029 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 83668 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83668 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 11821827 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11817805 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 11817805 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11821827 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 11821827 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11817805 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.043710 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.288758 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.144245 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132510 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.135225 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 11821827 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.043636 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.288569 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.143918 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132022 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.135072 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.135225 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.135072 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15625.084584 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15604.390217 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 36300.635635 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 36390.581243 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11650.882446 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11695.043018 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7935.966811 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7922.551150 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 32113.403839 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 32182.210514 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 32113.403839 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 32182.210514 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 13353050 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5461500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3087 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4325.574992 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 34134.375000 # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 13033547 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5494000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3077 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4235.796880 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32898.203593 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 223414 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 134188 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 1158095 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 989 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 1292283 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 1292283 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 189453 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 116326 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 11703 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 11087 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 305779 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 305779 # number of overall MSHR misses +system.cpu1.dcache.writebacks 223077 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 133946 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 1157260 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 1008 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 1291206 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 1291206 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 189341 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 116248 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 11661 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 11046 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 305589 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 305589 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2493574500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3446976050 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 98971000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54655500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5940550550 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5940550550 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455171000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41503599517 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 49958770517 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025587 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 2489937000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 3452864547 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 99179500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54297000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 5942801547 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 5942801547 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455613500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41497603581 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 49953217081 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025557 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026357 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026341 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.133005 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.132468 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132498 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132022 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.025874 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.025850 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.025874 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.025850 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13161.968932 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29632.034541 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8456.891395 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4929.692433 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13150.543200 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29702.571631 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8505.231112 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4915.535035 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1375,8 +1379,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308164258694 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308164258694 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1308174844926 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1308174844926 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -1391,8 +1395,8 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 55740 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 55723 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 41953 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 41930 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index c84a9ea85..f906b4862 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,14 +9,13 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -62,7 +62,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -126,6 +126,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -157,6 +158,7 @@ tracer=system.cpu.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -615,7 +617,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -657,7 +658,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -667,7 +667,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -737,7 +736,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -749,7 +747,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -759,7 +756,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -788,7 +784,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -798,7 +793,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -808,7 +802,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -821,7 +814,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -835,7 +827,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -846,7 +837,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -865,7 +855,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -875,7 +864,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -884,7 +872,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -896,7 +883,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -906,7 +892,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -916,7 +901,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -926,7 +910,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -936,7 +919,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -950,7 +932,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -964,7 +945,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -987,7 +967,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -997,7 +976,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -1007,7 +985,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -1017,7 +994,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 231dec8b1..46d2cdea6 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 09:54:06 -gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Feb 3 2012 14:00:40 +gem5 started Feb 3 2012 14:01:01 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503566110500 because m5_exit instruction encountered +Exiting @ tick 2503580880500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index ad6b1630f..b494abcbb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503566 # Number of seconds simulated -sim_ticks 2503566110500 # Number of ticks simulated -final_tick 2503566110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503581 # Number of seconds simulated +sim_ticks 2503580880500 # Number of ticks simulated +final_tick 2503580880500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76624 # Simulator instruction rate (inst/s) -host_tick_rate 2498140220 # Simulator tick rate (ticks/s) -host_mem_usage 386188 # Number of bytes of host memory used -host_seconds 1002.17 # Real time elapsed on the host -sim_insts 76790007 # Number of instructions simulated +host_inst_rate 56444 # Simulator instruction rate (inst/s) +host_tick_rate 1840259079 # Simulator tick rate (ticks/s) +host_mem_usage 413160 # Number of bytes of host memory used +host_seconds 1360.45 # Real time elapsed on the host +sim_insts 76789886 # Number of instructions simulated system.nvmem.bytes_read 64 # Number of bytes read from this memory system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -18,107 +18,107 @@ system.nvmem.num_other 0 # Nu system.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130731152 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1101568 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585992 # Number of bytes written to this memory -system.physmem.num_reads 15117140 # Number of read requests responded to by this memory -system.physmem.num_writes 856673 # Number of write requests responded to by this memory +system.physmem.bytes_read 130729872 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1100224 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9585224 # Number of bytes written to this memory +system.physmem.num_reads 15117120 # Number of read requests responded to by this memory +system.physmem.num_writes 856661 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52217975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 440000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3828935 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56046910 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119509 # number of replacements -system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use -system.l2c.total_refs 1795434 # Total number of references to valid blocks. -system.l2c.sampled_refs 150343 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.942252 # Average number of references to valid blocks. +system.physmem.bw_read 52217155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 439460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3828606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56045761 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119505 # number of replacements +system.l2c.tagsinuse 25834.929390 # Cycle average of tags in use +system.l2c.total_refs 1795685 # Total number of references to valid blocks. +system.l2c.sampled_refs 150314 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.946226 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11551.232252 # Average occupied blocks per context -system.l2c.occ_blocks::1 14378.665001 # Average occupied blocks per context -system.l2c.occ_percent::0 0.176258 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.219401 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1350292 # number of ReadReq hits -system.l2c.ReadReq_hits::1 153003 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1503295 # number of ReadReq hits -system.l2c.Writeback_hits::0 629881 # number of Writeback hits -system.l2c.Writeback_hits::total 629881 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 105934 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105934 # number of ReadExReq hits -system.l2c.demand_hits::0 1456226 # number of demand (read+write) hits -system.l2c.demand_hits::1 153003 # number of demand (read+write) hits -system.l2c.demand_hits::total 1609229 # number of demand (read+write) hits -system.l2c.overall_hits::0 1456226 # number of overall hits -system.l2c.overall_hits::1 153003 # number of overall hits -system.l2c.overall_hits::total 1609229 # number of overall hits -system.l2c.ReadReq_misses::0 36080 # number of ReadReq misses -system.l2c.ReadReq_misses::1 144 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36224 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3255 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3255 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 140433 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140433 # number of ReadExReq misses -system.l2c.demand_misses::0 176513 # number of demand (read+write) misses -system.l2c.demand_misses::1 144 # number of demand (read+write) misses -system.l2c.demand_misses::total 176657 # number of demand (read+write) misses -system.l2c.overall_misses::0 176513 # number of overall misses -system.l2c.overall_misses::1 144 # number of overall misses -system.l2c.overall_misses::total 176657 # number of overall misses -system.l2c.ReadReq_miss_latency 1894696500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 1006500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7384268500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9278965000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9278965000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1386372 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 153147 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1539519 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 629881 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 629881 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3293 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3293 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 18 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.occ_blocks::0 11478.014025 # Average occupied blocks per context +system.l2c.occ_blocks::1 14356.915365 # Average occupied blocks per context +system.l2c.occ_percent::0 0.175141 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.219069 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1349535 # number of ReadReq hits +system.l2c.ReadReq_hits::1 153277 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1502812 # number of ReadReq hits +system.l2c.Writeback_hits::0 630148 # number of Writeback hits +system.l2c.Writeback_hits::total 630148 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 47 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 105970 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105970 # number of ReadExReq hits +system.l2c.demand_hits::0 1455505 # number of demand (read+write) hits +system.l2c.demand_hits::1 153277 # number of demand (read+write) hits +system.l2c.demand_hits::total 1608782 # number of demand (read+write) hits +system.l2c.overall_hits::0 1455505 # number of overall hits +system.l2c.overall_hits::1 153277 # number of overall hits +system.l2c.overall_hits::total 1608782 # number of overall hits +system.l2c.ReadReq_misses::0 36088 # number of ReadReq misses +system.l2c.ReadReq_misses::1 150 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36238 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3252 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3252 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 4 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 140397 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140397 # number of ReadExReq misses +system.l2c.demand_misses::0 176485 # number of demand (read+write) misses +system.l2c.demand_misses::1 150 # number of demand (read+write) misses +system.l2c.demand_misses::total 176635 # number of demand (read+write) misses +system.l2c.overall_misses::0 176485 # number of overall misses +system.l2c.overall_misses::1 150 # number of overall misses +system.l2c.overall_misses::total 176635 # number of overall misses +system.l2c.ReadReq_miss_latency 1895542500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 1059500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7383005500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9278548000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9278548000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1385623 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 153427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1539050 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 630148 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 630148 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 3299 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3299 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 21 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1632739 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 153147 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1785886 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1632739 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 153147 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1785886 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026025 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000940 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026965 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.988460 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.111111 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.570015 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.108109 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000940 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.109049 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.108109 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000940 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.109049 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52513.761086 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 13157614.583333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 13210128.344420 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 309.216590 # average UpgradeReq miss latency +system.l2c.demand_accesses::0 1631990 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 153427 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1785417 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1631990 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 153427 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1785417 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026045 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.027022 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.985753 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.190476 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.569869 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.108141 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000978 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109119 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.108141 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000978 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109119 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52525.562514 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 12636950 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12689475.562514 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 325.799508 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52582.145934 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52586.632905 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52568.167784 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 64437256.944444 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64489825.112228 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52568.167784 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 64437256.944444 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 64489825.112228 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52574.145111 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 61856986.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 61909560.811778 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52574.145111 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 61856986.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 61909560.811778 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -127,50 +127,50 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102655 # number of writebacks +system.l2c.writebacks 102643 # number of writebacks system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 94 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 36130 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3255 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140433 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 176563 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 176563 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 36144 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3252 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 4 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 140397 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 176541 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 176541 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1449837500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 131527500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 80000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5640075000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7089912500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7089912500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131769527500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32342636570 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164112164070 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026061 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.235917 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.261978 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.988460 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1450468000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 131324500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 160000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5639183500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7089651500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7089651500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131770082500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32364127897 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164134210397 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026085 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.235578 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.261663 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.985753 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.111111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.190476 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.570015 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.569869 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.108139 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.152899 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.261038 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.108139 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.152899 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.261038 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40128.355937 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40407.834101 # average UpgradeReq mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.108175 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.150651 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.258827 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.108175 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.150651 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.258827 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40130.256751 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40382.687577 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40162.034565 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40165.982891 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -185,27 +185,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52217329 # DTB read hits -system.cpu.dtb.read_misses 90306 # DTB read misses -system.cpu.dtb.write_hits 11974176 # DTB write hits -system.cpu.dtb.write_misses 25588 # DTB write misses +system.cpu.dtb.read_hits 52219999 # DTB read hits +system.cpu.dtb.read_misses 90279 # DTB read misses +system.cpu.dtb.write_hits 11976179 # DTB write hits +system.cpu.dtb.write_misses 25577 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5563 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 685 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4346 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 6089 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 654 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2233 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52307635 # DTB read accesses -system.cpu.dtb.write_accesses 11999764 # DTB write accesses +system.cpu.dtb.perms_faults 2193 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52310278 # DTB read accesses +system.cpu.dtb.write_accesses 12001756 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64191505 # DTB hits -system.cpu.dtb.misses 115894 # DTB misses -system.cpu.dtb.accesses 64307399 # DTB accesses -system.cpu.itb.inst_hits 14124795 # ITB inst hits -system.cpu.itb.inst_misses 9853 # ITB inst misses +system.cpu.dtb.hits 64196178 # DTB hits +system.cpu.dtb.misses 115856 # DTB misses +system.cpu.dtb.accesses 64312034 # DTB accesses +system.cpu.itb.inst_hits 14123674 # ITB inst hits +system.cpu.itb.inst_misses 9885 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -214,517 +214,517 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2606 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2599 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 7868 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 7902 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 14134648 # ITB inst accesses -system.cpu.itb.hits 14124795 # DTB hits -system.cpu.itb.misses 9853 # DTB misses -system.cpu.itb.accesses 14134648 # DTB accesses -system.cpu.numCycles 415912091 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 14133559 # ITB inst accesses +system.cpu.itb.hits 14123674 # DTB hits +system.cpu.itb.misses 9885 # DTB misses +system.cpu.itb.accesses 14133559 # DTB accesses +system.cpu.numCycles 415943429 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16206323 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12554772 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1108177 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13916811 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10226428 # Number of BTB hits +system.cpu.BPredUnit.lookups 16201364 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12549421 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1109380 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13917593 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 10243002 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1423283 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 227054 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32931583 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 104747250 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16206323 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11649711 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24460631 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7066944 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 130925 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92852979 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 144764 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 217141 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14116150 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1044696 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4826 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155542524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.838034 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.183637 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1423675 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 227604 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32912368 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 104836271 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16201364 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11666677 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24487466 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7079059 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131458 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 92859775 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145565 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217503 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14115008 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1041610 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4861 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155569254 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.838536 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.184070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131107701 84.29% 84.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1736645 1.12% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2606210 1.68% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3650547 2.35% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2167045 1.39% 90.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1435515 0.92% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2626627 1.69% 93.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 854151 0.55% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9358083 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131107551 84.28% 84.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1739904 1.12% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2616632 1.68% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3657999 2.35% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2164577 1.39% 90.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1434404 0.92% 91.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2630326 1.69% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 851935 0.55% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9365926 6.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155542524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038966 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.251849 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35137982 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92713675 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21969277 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1093477 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4628113 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2313056 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 177631 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 122001156 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 574106 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4628113 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37294552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36817406 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49929047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20901153 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5972253 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 113826701 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4400 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 914485 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3979731 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 42252 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 118358543 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 523323093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 523225639 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 97454 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77492718 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 40865824 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1204637 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1098724 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12304657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21982315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14168730 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1896802 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2281380 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102860211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1874616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126873316 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 252471 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26973483 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 72956952 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 374923 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155542524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.815683 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505358 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155569254 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.038951 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.252045 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35134284 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92713878 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21991115 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1092987 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4636990 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2313958 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 177730 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 122065816 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 573184 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4636990 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37283411 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36813700 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49928995 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20929371 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5976787 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 113968448 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 915244 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3983499 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 42655 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 118524115 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 524000264 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 523903687 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 96577 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77492548 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 41031566 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1204512 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1098851 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12310506 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21988549 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14164932 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1902928 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2266136 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 102902284 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1875395 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126904684 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 253228 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27017748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 72978464 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 375688 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155569254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.815744 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.505343 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108919716 70.03% 70.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15115277 9.72% 79.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7538109 4.85% 84.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6517896 4.19% 88.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12766129 8.21% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2735746 1.76% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1395145 0.90% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 422031 0.27% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132475 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108923700 70.02% 70.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15131938 9.73% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7543329 4.85% 84.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6524442 4.19% 88.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12759852 8.20% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2730334 1.76% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1400610 0.90% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 422368 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132681 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155542524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155569254 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45891 0.52% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8417784 94.58% 95.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 436630 4.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45526 0.51% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8417505 94.61% 95.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 433723 4.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60069482 47.35% 47.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96615 0.08% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 8 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2251 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53942685 42.52% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12655733 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60099266 47.36% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 96421 0.08% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 5 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2248 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53941927 42.51% 90.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12658279 9.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126873316 # Type of FU issued -system.cpu.iq.rate 0.305048 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8900311 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070151 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 418533128 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131726191 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87292108 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24017 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13690 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10446 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135654305 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12792 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 614767 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126904684 # Type of FU issued +system.cpu.iq.rate 0.305101 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8896761 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070106 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 418619840 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131813494 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87332577 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23940 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13540 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10418 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 135682181 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12734 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 614286 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6301517 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11128 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32657 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2389653 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6307786 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32675 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2385852 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34061869 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1153605 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34061916 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1151020 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4628113 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28345943 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 419499 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 104949442 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 473979 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21982315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14168730 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1228031 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 85187 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7556 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32657 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 850397 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 257130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1107527 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123429779 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52914304 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3443537 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4636990 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28345844 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 418518 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 104992332 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 473238 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21988549 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14164932 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1227782 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 84296 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7341 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32675 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 852505 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 256815 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1109320 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123469909 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52917262 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3434775 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 214615 # number of nop insts executed -system.cpu.iew.exec_refs 65401525 # number of memory reference insts executed -system.cpu.iew.exec_branches 11705842 # Number of branches executed -system.cpu.iew.exec_stores 12487221 # Number of stores executed -system.cpu.iew.exec_rate 0.296769 # Inst execution rate -system.cpu.iew.wb_sent 121771133 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87302554 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47043389 # num instructions producing a value -system.cpu.iew.wb_consumers 86638668 # num instructions consuming a value +system.cpu.iew.exec_nop 214653 # number of nop insts executed +system.cpu.iew.exec_refs 65406640 # number of memory reference insts executed +system.cpu.iew.exec_branches 11708135 # Number of branches executed +system.cpu.iew.exec_stores 12489378 # Number of stores executed +system.cpu.iew.exec_rate 0.296843 # Inst execution rate +system.cpu.iew.wb_sent 121811310 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87342995 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47060292 # num instructions producing a value +system.cpu.iew.wb_consumers 86666260 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.209906 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.542984 # average fanout of values written-back +system.cpu.iew.wb_rate 0.209988 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.543006 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 76940388 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27793277 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499693 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 977065 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 150996763 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.509550 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459324 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 76940267 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 27835988 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499707 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 978113 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151014616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.509489 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459114 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122144480 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14839804 9.83% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4110999 2.72% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2181780 1.44% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1788910 1.18% 96.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1360879 0.90% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1262027 0.84% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 662023 0.44% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2645861 1.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122165210 80.90% 80.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14833013 9.82% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4110348 2.72% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2186082 1.45% 94.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1788351 1.18% 96.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1361296 0.90% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1264343 0.84% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 665414 0.44% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2640559 1.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 150996763 # Number of insts commited each cycle -system.cpu.commit.count 76940388 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 151014616 # Number of insts commited each cycle +system.cpu.commit.count 76940267 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27459875 # Number of memory references committed -system.cpu.commit.loads 15680798 # Number of loads committed -system.cpu.commit.membars 413062 # Number of memory barriers committed -system.cpu.commit.branches 9891038 # Number of branches committed +system.cpu.commit.refs 27459843 # Number of memory references committed +system.cpu.commit.loads 15680763 # Number of loads committed +system.cpu.commit.membars 413065 # Number of memory barriers committed +system.cpu.commit.branches 9891047 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68493475 # Number of committed integer instructions. -system.cpu.commit.function_calls 995603 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2645861 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68493330 # Number of committed integer instructions. +system.cpu.commit.function_calls 995601 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2640559 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 251328068 # The number of ROB reads -system.cpu.rob.rob_writes 214226863 # The number of ROB writes -system.cpu.timesIdled 1877486 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260369567 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591132146 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 76790007 # Number of Instructions Simulated -system.cpu.committedInsts_total 76790007 # Number of Instructions Simulated -system.cpu.cpi 5.416227 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.416227 # CPI: Total CPI of All Threads -system.cpu.ipc 0.184630 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184630 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 559625786 # number of integer regfile reads -system.cpu.int_regfile_writes 89694789 # number of integer regfile writes -system.cpu.fp_regfile_reads 8322 # number of floating regfile reads -system.cpu.fp_regfile_writes 2832 # number of floating regfile writes -system.cpu.misc_regfile_reads 137256850 # number of misc regfile reads -system.cpu.misc_regfile_writes 912282 # number of misc regfile writes -system.cpu.icache.replacements 991618 # number of replacements -system.cpu.icache.tagsinuse 511.615309 # Cycle average of tags in use -system.cpu.icache.total_refs 13036767 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992130 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.140180 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 251393815 # The number of ROB reads +system.cpu.rob.rob_writes 214319630 # The number of ROB writes +system.cpu.timesIdled 1877181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260374175 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591130340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 76789886 # Number of Instructions Simulated +system.cpu.committedInsts_total 76789886 # Number of Instructions Simulated +system.cpu.cpi 5.416643 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.416643 # CPI: Total CPI of All Threads +system.cpu.ipc 0.184616 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184616 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 559798057 # number of integer regfile reads +system.cpu.int_regfile_writes 89741069 # number of integer regfile writes +system.cpu.fp_regfile_reads 8257 # number of floating regfile reads +system.cpu.fp_regfile_writes 2814 # number of floating regfile writes +system.cpu.misc_regfile_reads 137366935 # number of misc regfile reads +system.cpu.misc_regfile_writes 912292 # number of misc regfile writes +system.cpu.icache.replacements 991177 # number of replacements +system.cpu.icache.tagsinuse 511.615293 # Cycle average of tags in use +system.cpu.icache.total_refs 13035657 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991689 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13.144904 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.615309 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 511.615293 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 13036767 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13036767 # number of ReadReq hits -system.cpu.icache.demand_hits::0 13036767 # number of demand (read+write) hits +system.cpu.icache.ReadReq_hits::0 13035657 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13035657 # number of ReadReq hits +system.cpu.icache.demand_hits::0 13035657 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13036767 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 13036767 # number of overall hits +system.cpu.icache.demand_hits::total 13035657 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 13035657 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 13036767 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1079261 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079261 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1079261 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 13035657 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1079227 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079227 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1079227 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079261 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1079261 # number of overall misses +system.cpu.icache.demand_misses::total 1079227 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1079227 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1079261 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15910722989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15910722989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15910722989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 14116028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14116028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 14116028 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1079227 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15906225491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15906225491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15906225491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 14114884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14114884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 14114884 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14116028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 14116028 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 14114884 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 14114884 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14116028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.076456 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.076456 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 14114884 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.076460 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.076460 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.076456 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.076460 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14742.238429 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14738.535536 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14742.238429 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14738.535536 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14742.238429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14738.535536 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2475992 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2390996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 368 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6728.239130 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7011.718475 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 57161 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 87101 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 87101 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 87101 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 992160 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 992160 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 992160 # number of overall MSHR misses +system.cpu.icache.writebacks 57255 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 87505 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 87505 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 87505 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 991722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 991722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 991722 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11856676492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11856676492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11856676492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11850340996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11850340996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11850340996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070286 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070261 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.070286 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.070261 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.070286 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.070261 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11950.367372 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11949.256945 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643915 # number of replacements +system.cpu.dcache.replacements 643728 # number of replacements system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use -system.cpu.dcache.total_refs 22265831 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644427 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.551363 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 22270301 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644240 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.568330 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 14412375 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14412375 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 7264610 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7264610 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 299966 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 299966 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 285484 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285484 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 21676985 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 14416609 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14416609 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 7264899 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7264899 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 299899 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 299899 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 285488 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285488 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 21681508 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21676985 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 21676985 # number of overall hits +system.cpu.dcache.demand_hits::total 21681508 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 21681508 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 21676985 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 724119 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 724119 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2966647 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966647 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 13487 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13487 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 18 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3690766 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 21681508 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 722544 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 722544 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2966373 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2966373 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 13502 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13502 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 21 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 3688917 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3690766 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3690766 # number of overall misses +system.cpu.dcache.demand_misses::total 3688917 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3688917 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3690766 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 10885048500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110351571736 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 219032000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 343000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 121236620236 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121236620236 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 15136494 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 15136494 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10231257 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10231257 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 313453 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 313453 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 285502 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285502 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 25367751 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 3688917 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 10864923000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110367485740 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 219139000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 467500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 121232408740 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 121232408740 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 15139153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 15139153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 10231272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 313401 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 313401 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 285509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 25370425 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25367751 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 25367751 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 25370425 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 25370425 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25367751 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.047839 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.289959 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043027 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000063 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.145490 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 25370425 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.047727 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.289932 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043082 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000074 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.145402 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.145490 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.145402 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15032.126626 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15037.039959 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 37197.405602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 37206.206280 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16240.231334 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16230.114057 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 19055.555556 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 22261.904762 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 32848.633654 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 32863.956749 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 32848.633654 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 32863.956749 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16787932 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7490000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2999 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 273 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5597.843281 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27435.897436 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 16658435 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7526500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2975 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5599.473950 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 572720 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 338008 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2717083 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3055091 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3055091 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 386111 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249564 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 12045 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 18 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 635675 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 635675 # number of overall MSHR misses +system.cpu.dcache.writebacks 572893 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 336628 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 2716799 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 3053427 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3053427 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 385916 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249574 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 12049 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 21 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 635490 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 635490 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5247540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8926098932 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161654000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 282500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 14173639432 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 14173639432 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258178710 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 189416927710 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025509 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 5245615500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8926036935 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161663500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 398500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 14171652435 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 14171652435 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147159299000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42287348315 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 189446647315 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025491 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038427 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038446 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000063 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000074 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.025058 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.025048 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.025058 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.025048 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13590.756285 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.772980 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13420.838522 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15694.444444 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13592.635444 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.091456 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13417.171550 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 18976.190476 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -785,8 +785,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1307898920918 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1307898920918 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1307927966543 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1307927966543 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -801,6 +801,6 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87993 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 9b8aaf5dd..ea30d17bb 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -9,7 +10,6 @@ time_sync_spin_threshold=100000000 type=LinuxX86System children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus acpi_description_table_pointer=system.acpi_description_table_pointer -boot_cpu_frequency=500 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 e820_table=system.e820_table init_param=0 @@ -154,6 +154,7 @@ tracer=system.cpu.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -532,7 +533,6 @@ type=X86LocalApic int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 -platform=system.pc system=system int_port=system.membus.port[7] pio=system.membus.port[6] @@ -1050,7 +1050,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1073,7 +1072,6 @@ fake_mem=false pio_addr=9223372036854779128 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1114,7 +1112,6 @@ fake_mem=false pio_addr=9223372036854776568 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1131,7 +1128,6 @@ fake_mem=false pio_addr=9223372036854776808 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1148,7 +1144,6 @@ fake_mem=false pio_addr=9223372036854776552 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1165,7 +1160,6 @@ fake_mem=false pio_addr=9223372036854776818 pio_latency=1000 pio_size=2 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1182,7 +1176,6 @@ fake_mem=false pio_addr=9223372036854775936 pio_latency=1000 pio_size=1 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1222,7 +1215,6 @@ children=int_pin int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=1000 -platform=system.pc system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.port[2] @@ -1234,7 +1226,6 @@ type=X86IntSourcePin type=I8237 pio_addr=9223372036854775808 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[3] @@ -1419,7 +1410,6 @@ external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 pio_latency=1000 -platform=system.pc system=system int_port=system.iobus.port[13] pio=system.iobus.port[12] @@ -1433,7 +1423,6 @@ keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[7] @@ -1450,7 +1439,6 @@ mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 pio_latency=1000 -platform=system.pc slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.port[8] @@ -1465,7 +1453,6 @@ mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 pio_latency=1000 -platform=system.pc slave=Null system=system pio=system.iobus.port[9] @@ -1479,7 +1466,6 @@ children=int_pin int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[10] @@ -1491,7 +1477,6 @@ type=PcSpeaker i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[11] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 9036859eb..647f02ab1 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,15 +1,15 @@ -Redirecting stdout to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simout -Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simerr +Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 28 2012 16:24:13 -gem5 started Jan 28 2012 16:29:18 +gem5 compiled Feb 3 2012 12:36:19 +gem5 started Feb 3 2012 12:37:07 gem5 executing on ribera.cs.wisc.edu -command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5164643202500 because m5_exit instruction encountered +Exiting @ tick 5163317092500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 9cc68e765..9bce828a3 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.164643 # Number of seconds simulated -sim_ticks 5164643202500 # Number of ticks simulated -final_tick 5164643202500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.163317 # Number of seconds simulated +sim_ticks 5163317092500 # Number of ticks simulated +final_tick 5163317092500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 258156 # Simulator instruction rate (inst/s) -host_tick_rate 1586008699 # Simulator tick rate (ticks/s) -host_mem_usage 390600 # Number of bytes of host memory used -host_seconds 3256.38 # Real time elapsed on the host -sim_insts 840653382 # Number of instructions simulated -system.physmem.bytes_read 15885120 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1235904 # Number of instructions bytes read from this memory -system.physmem.bytes_written 12075328 # Number of bytes written to this memory -system.physmem.num_reads 248205 # Number of read requests responded to by this memory -system.physmem.num_writes 188677 # Number of write requests responded to by this memory +host_inst_rate 210982 # Simulator instruction rate (inst/s) +host_tick_rate 1295931182 # Simulator tick rate (ticks/s) +host_mem_usage 391560 # Number of bytes of host memory used +host_seconds 3984.25 # Real time elapsed on the host +sim_insts 840604148 # Number of instructions simulated +system.physmem.bytes_read 15861056 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1233408 # Number of instructions bytes read from this memory +system.physmem.bytes_written 12134976 # Number of bytes written to this memory +system.physmem.num_reads 247829 # Number of read requests responded to by this memory +system.physmem.num_writes 189609 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3075744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 239301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2338076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5413820 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 166524 # number of replacements -system.l2c.tagsinuse 37860.019471 # Cycle average of tags in use -system.l2c.total_refs 3791499 # Total number of references to valid blocks. -system.l2c.sampled_refs 201257 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.839091 # Average number of references to valid blocks. +system.physmem.bw_read 3071873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 238879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 2350229 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 5422102 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 168510 # number of replacements +system.l2c.tagsinuse 37865.450237 # Cycle average of tags in use +system.l2c.total_refs 3777661 # Total number of references to valid blocks. +system.l2c.sampled_refs 200841 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.809212 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11072.402172 # Average occupied blocks per context -system.l2c.occ_blocks::1 26787.617299 # Average occupied blocks per context -system.l2c.occ_percent::0 0.168951 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.408747 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2329446 # number of ReadReq hits -system.l2c.ReadReq_hits::1 146092 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2475538 # number of ReadReq hits -system.l2c.Writeback_hits::0 1599025 # number of Writeback hits -system.l2c.Writeback_hits::total 1599025 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 316 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 316 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 151571 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151571 # number of ReadExReq hits -system.l2c.demand_hits::0 2481017 # number of demand (read+write) hits -system.l2c.demand_hits::1 146092 # number of demand (read+write) hits -system.l2c.demand_hits::total 2627109 # number of demand (read+write) hits -system.l2c.overall_hits::0 2481017 # number of overall hits -system.l2c.overall_hits::1 146092 # number of overall hits -system.l2c.overall_hits::total 2627109 # number of overall hits -system.l2c.ReadReq_misses::0 64214 # number of ReadReq misses -system.l2c.ReadReq_misses::1 107 # number of ReadReq misses -system.l2c.ReadReq_misses::total 64321 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 5085 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 5085 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 141328 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141328 # number of ReadExReq misses -system.l2c.demand_misses::0 205542 # number of demand (read+write) misses -system.l2c.demand_misses::1 107 # number of demand (read+write) misses -system.l2c.demand_misses::total 205649 # number of demand (read+write) misses -system.l2c.overall_misses::0 205542 # number of overall misses -system.l2c.overall_misses::1 107 # number of overall misses -system.l2c.overall_misses::total 205649 # number of overall misses -system.l2c.ReadReq_miss_latency 3375006500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 39785500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7360156500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 10735163000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 10735163000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2393660 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 146199 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2539859 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1599025 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1599025 # number of Writeback accesses(hits+misses) +system.l2c.occ_blocks::0 11087.594784 # Average occupied blocks per context +system.l2c.occ_blocks::1 26777.855453 # Average occupied blocks per context +system.l2c.occ_percent::0 0.169183 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.408598 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2326799 # number of ReadReq hits +system.l2c.ReadReq_hits::1 141457 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2468256 # number of ReadReq hits +system.l2c.Writeback_hits::0 1603120 # number of Writeback hits +system.l2c.Writeback_hits::total 1603120 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 322 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 322 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 150704 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 150704 # number of ReadExReq hits +system.l2c.demand_hits::0 2477503 # number of demand (read+write) hits +system.l2c.demand_hits::1 141457 # number of demand (read+write) hits +system.l2c.demand_hits::total 2618960 # number of demand (read+write) hits +system.l2c.overall_hits::0 2477503 # number of overall hits +system.l2c.overall_hits::1 141457 # number of overall hits +system.l2c.overall_hits::total 2618960 # number of overall hits +system.l2c.ReadReq_misses::0 64223 # number of ReadReq misses +system.l2c.ReadReq_misses::1 92 # number of ReadReq misses +system.l2c.ReadReq_misses::total 64315 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 5079 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 5079 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 141389 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 141389 # number of ReadExReq misses +system.l2c.demand_misses::0 205612 # number of demand (read+write) misses +system.l2c.demand_misses::1 92 # number of demand (read+write) misses +system.l2c.demand_misses::total 205704 # number of demand (read+write) misses +system.l2c.overall_misses::0 205612 # number of overall misses +system.l2c.overall_misses::1 92 # number of overall misses +system.l2c.overall_misses::total 205704 # number of overall misses +system.l2c.ReadReq_miss_latency 3374675500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 37477500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7363267000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 10737942500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 10737942500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2391022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 141549 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2532571 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1603120 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1603120 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::0 5401 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5401 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292899 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292899 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2686559 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 146199 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2832758 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2686559 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 146199 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2832758 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026827 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000732 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.027559 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.941492 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.482514 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.076508 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000732 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.077239 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.076508 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000732 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.077239 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52558.733298 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 31542116.822430 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 31594675.555728 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 7824.090462 # average UpgradeReq miss latency +system.l2c.ReadExReq_accesses::0 292093 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292093 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2683115 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 141549 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2824664 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2683115 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 141549 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2824664 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026860 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000650 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.027510 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.940381 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.484055 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.076632 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000650 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.077282 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.076632 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000650 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.077282 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52546.213973 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 36681255.434783 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 36733801.648756 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 7378.913172 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52078.544238 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52078.075381 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52228.561559 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 100328626.168224 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 100380854.729784 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52228.561559 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 100328626.168224 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 100380854.729784 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52224.298679 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 116716766.304348 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 116768990.603027 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52224.298679 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 116716766.304348 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 116768990.603027 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -111,88 +111,88 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142010 # number of writebacks +system.l2c.writebacks 142942 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 64319 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 5085 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 141328 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 205647 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 205647 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 64313 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 5079 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 141389 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 205702 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 205702 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2589128000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 203766500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5654353000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8243481000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8243481000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 59975261500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1228545000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 61203806500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026871 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.439941 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.466812 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.941492 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2588909500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 203533000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5656832000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8245741500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8245741500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 59975483500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1228994000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 61204477500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026898 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.454351 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.481249 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.940381 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.482514 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.484055 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.076547 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.406624 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.483170 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.076547 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.406624 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.483170 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40254.481568 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40072.074730 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40008.724386 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40085.588411 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40085.588411 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.076665 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.453221 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.529887 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.076665 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.453221 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.529887 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40254.839613 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40073.439653 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40008.996457 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40085.859642 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40085.859642 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47574 # number of replacements -system.iocache.tagsinuse 0.187855 # Cycle average of tags in use +system.iocache.replacements 47580 # number of replacements +system.iocache.tagsinuse 0.183883 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47596 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996389374000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.187855 # Average occupied blocks per context -system.iocache.occ_percent::1 0.011741 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4996389534000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.183883 # Average occupied blocks per context +system.iocache.occ_percent::1 0.011493 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.ReadReq_misses::1 915 # number of ReadReq misses +system.iocache.ReadReq_misses::total 915 # number of ReadReq misses system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.demand_misses::1 47635 # number of demand (read+write) misses +system.iocache.demand_misses::total 47635 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency 113959932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6369072160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6483032092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6483032092 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.overall_misses::1 47635 # number of overall misses +system.iocache.overall_misses::total 47635 # number of overall misses +system.iocache.ReadReq_miss_latency 114575932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6365614160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6480190092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6480190092 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 915 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47635 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47635 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47635 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47635 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -202,37 +202,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125368.462046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125219.597814 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136324.318493 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136250.303082 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136115.225850 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136038.419062 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136115.225850 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136038.419062 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68773500 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68485452 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11260 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11259 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6107.770870 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6082.729550 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks 46667 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 915 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47629 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47629 # number of overall MSHR misses +system.iocache.demand_mshr_misses 47635 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 47635 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66668982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3939322842 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4005991824 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4005991824 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 66972982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3935855798 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4002828780 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4002828780 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -246,10 +246,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73343.214521 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84317.697817 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84108.249680 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84108.249680 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73194.515847 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84243.488827 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84031.253910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84031.253910 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -266,140 +266,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 462648122 # number of cpu cycles simulated +system.cpu.numCycles 462460674 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91002231 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91002231 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1246819 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89740071 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83586488 # Number of BTB hits +system.cpu.BPredUnit.lookups 91001984 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 91001984 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1246670 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 89740974 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83587498 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29047716 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449719579 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91002231 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83586488 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171232175 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5868826 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 136581 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 101975708 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37095 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37068 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 258 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9677008 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 518282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3472 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 307050159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.882718 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.377693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28956413 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449639850 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91001984 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83587498 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 171222727 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5870168 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 127753 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 101915873 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 38952 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9672092 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 512695 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3312 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 306883426 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.884320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.377751 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136328655 44.40% 44.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1837704 0.60% 45.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72797609 23.71% 68.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1414382 0.46% 69.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1803500 0.59% 69.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3975077 1.29% 71.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1554877 0.51% 71.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1662423 0.54% 72.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85675932 27.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136151197 44.37% 44.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1833476 0.60% 44.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72801112 23.72% 68.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1413943 0.46% 69.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1812929 0.59% 69.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3984448 1.30% 71.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1563806 0.51% 71.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1664583 0.54% 72.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85657932 27.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 307050159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.196699 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.972055 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34173588 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98204152 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165547565 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4541296 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4583558 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 881331819 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 622 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4583558 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38558977 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 67835236 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11414000 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165163218 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19495170 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 877018517 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10722 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12485969 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3867736 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 878675009 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1719931818 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1719931354 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 464 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843258778 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35416224 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 488329 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 492601 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46069220 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19448734 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10510676 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1191191 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 913743 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 869530177 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1725186 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866447166 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 122007 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 29731249 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42741048 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 205599 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 307050159 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.821842 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.403845 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 306883426 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.196778 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.972277 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34101035 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98103338 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165554285 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4539875 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4584893 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 881320225 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 609 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4584893 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38485909 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 67729275 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11421097 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165177226 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 19485026 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 876989303 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10814 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12483638 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3869558 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 878639289 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1719877661 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1719877141 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843209199 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35430083 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 491480 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 496551 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 46051608 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19446241 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10506071 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1193626 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 915732 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 869497074 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1725725 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 866404799 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 123854 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 29753009 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42786279 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 206033 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 306883426 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.823238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.403588 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 100227598 32.64% 32.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25342786 8.25% 40.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 13946244 4.54% 45.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9645579 3.14% 48.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79515480 25.90% 74.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4843126 1.58% 76.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72836741 23.72% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 563681 0.18% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128924 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 100067522 32.61% 32.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25349299 8.26% 40.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 13936726 4.54% 45.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9650933 3.14% 48.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79503599 25.91% 74.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4853866 1.58% 76.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72832557 23.73% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 561211 0.18% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127713 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 307050159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 306883426 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 189288 8.89% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1772779 83.25% 92.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 167484 7.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 188296 8.84% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1773429 83.29% 92.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 167520 7.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 305473 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 831218521 95.93% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 304337 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 831186392 95.94% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued @@ -428,253 +429,253 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25430215 2.93% 98.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9492957 1.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25424398 2.93% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9489672 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866447166 # Type of FU issued -system.cpu.iq.rate 1.872799 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2129551 # FU busy when requested +system.cpu.iq.FU_type_0::total 866404799 # Type of FU issued +system.cpu.iq.rate 1.873467 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2129245 # FU busy when requested system.cpu.iq.fu_busy_rate 0.002458 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2042346945 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 900997029 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855808882 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868271157 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1634079 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 2042097119 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 900986111 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 855761606 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 229 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 868229599 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1634850 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4122999 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16974 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11449 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2081373 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4122229 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17231 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11383 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2082513 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821312 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4401 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821289 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4333 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4583558 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45537576 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6145383 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 871255363 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 286386 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19448734 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10510706 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 890989 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5371019 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12371 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11449 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 894854 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 527277 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1422131 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864388820 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24990007 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2058345 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4584893 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45441721 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6142722 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 871222799 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 285751 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19446241 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10506071 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 891740 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5368443 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12385 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11383 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 896223 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 525625 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1421848 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 864338156 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24982156 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2066642 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34246643 # number of memory reference insts executed -system.cpu.iew.exec_branches 86674452 # Number of branches executed -system.cpu.iew.exec_stores 9256636 # Number of stores executed -system.cpu.iew.exec_rate 1.868350 # Inst execution rate -system.cpu.iew.wb_sent 863858871 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855808933 # cumulative count of insts written-back -system.cpu.iew.wb_producers 670117555 # num instructions producing a value -system.cpu.iew.wb_consumers 1169388275 # num instructions consuming a value +system.cpu.iew.exec_refs 34234409 # number of memory reference insts executed +system.cpu.iew.exec_branches 86668621 # Number of branches executed +system.cpu.iew.exec_stores 9252253 # Number of stores executed +system.cpu.iew.exec_rate 1.868998 # Inst execution rate +system.cpu.iew.wb_sent 863811947 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 855761668 # cumulative count of insts written-back +system.cpu.iew.wb_producers 670084242 # num instructions producing a value +system.cpu.iew.wb_consumers 1169301773 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.849805 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.573050 # average fanout of values written-back +system.cpu.iew.wb_rate 1.850453 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.573064 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 840653382 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 30493739 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1519585 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1250852 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 302482532 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.779180 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.862928 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 840604148 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 30510484 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1519690 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1250933 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 302314482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.780562 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.862970 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121705322 40.24% 40.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14450311 4.78% 45.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4296632 1.42% 46.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76653351 25.34% 71.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3954227 1.31% 73.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1803566 0.60% 73.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1076627 0.36% 74.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71984714 23.80% 97.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6557782 2.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121547491 40.21% 40.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14447999 4.78% 44.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4300765 1.42% 46.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76650469 25.35% 71.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3947228 1.31% 73.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1803648 0.60% 73.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1077125 0.36% 74.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71984746 23.81% 97.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6555011 2.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 302482532 # Number of insts commited each cycle -system.cpu.commit.count 840653382 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 302314482 # Number of insts commited each cycle +system.cpu.commit.count 840604148 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23755065 # Number of memory references committed -system.cpu.commit.loads 15325732 # Number of loads committed -system.cpu.commit.membars 781571 # Number of memory barriers committed -system.cpu.commit.branches 85522464 # Number of branches committed +system.cpu.commit.refs 23747567 # Number of memory references committed +system.cpu.commit.loads 15324009 # Number of loads committed +system.cpu.commit.membars 781567 # Number of memory barriers committed +system.cpu.commit.branches 85515141 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768481836 # Number of committed integer instructions. +system.cpu.commit.int_insts 768433298 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6557782 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6555011 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1166989570 # The number of ROB reads -system.cpu.rob.rob_writes 1746890100 # The number of ROB writes -system.cpu.timesIdled 2859611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155597963 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9866635724 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 840653382 # Number of Instructions Simulated -system.cpu.committedInsts_total 840653382 # Number of Instructions Simulated -system.cpu.cpi 0.550343 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.550343 # CPI: Total CPI of All Threads -system.cpu.ipc 1.817047 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.817047 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1406419580 # number of integer regfile reads -system.cpu.int_regfile_writes 857121538 # number of integer regfile writes -system.cpu.fp_regfile_reads 51 # number of floating regfile reads -system.cpu.misc_regfile_reads 282006262 # number of misc regfile reads -system.cpu.misc_regfile_writes 409317 # number of misc regfile writes -system.cpu.icache.replacements 1024030 # number of replacements -system.cpu.icache.tagsinuse 510.509684 # Cycle average of tags in use -system.cpu.icache.total_refs 8586920 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1024542 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.381228 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56648663000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.509684 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997089 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8586920 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8586920 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8586920 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1166791668 # The number of ROB reads +system.cpu.rob.rob_writes 1746826364 # The number of ROB writes +system.cpu.timesIdled 2858532 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155577248 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9864170951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 840604148 # Number of Instructions Simulated +system.cpu.committedInsts_total 840604148 # Number of Instructions Simulated +system.cpu.cpi 0.550153 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.550153 # CPI: Total CPI of All Threads +system.cpu.ipc 1.817677 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.817677 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1406313694 # number of integer regfile reads +system.cpu.int_regfile_writes 857070459 # number of integer regfile writes +system.cpu.fp_regfile_reads 62 # number of floating regfile reads +system.cpu.misc_regfile_reads 281985005 # number of misc regfile reads +system.cpu.misc_regfile_writes 409504 # number of misc regfile writes +system.cpu.icache.replacements 1020153 # number of replacements +system.cpu.icache.tagsinuse 509.928344 # Cycle average of tags in use +system.cpu.icache.total_refs 8587640 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1020665 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.413769 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56648796000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.928344 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.995954 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8587640 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8587640 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8587640 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8586920 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8586920 # number of overall hits +system.cpu.icache.demand_hits::total 8587640 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8587640 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8586920 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1090085 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1090085 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1090085 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8587640 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1084449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1084449 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1084449 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1090085 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1090085 # number of overall misses +system.cpu.icache.demand_misses::total 1084449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1084449 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1090085 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16354144492 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16354144492 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16354144492 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9677005 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9677005 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9677005 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1084449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16282601991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16282601991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16282601991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9672089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9672089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9672089 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9677005 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9677005 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9672089 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9672089 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9677005 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.112647 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.112647 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9672089 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.112121 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.112121 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.112647 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.112121 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 15002.632356 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 15014.631385 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 15002.632356 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 15014.631385 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 15002.632356 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 15014.631385 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2751493 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2694492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 271 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 263 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10153.110701 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10245.216730 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 1551 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 61895 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 61895 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 61895 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1028190 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1028190 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1028190 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 60108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 60108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 60108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1024341 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1024341 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1024341 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12436535493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12436535493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12436535493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12392610492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12392610492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12392610492 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.106251 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.105907 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.106251 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.105907 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.106251 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.105907 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12095.561611 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12095.561611 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12095.561611 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12098.129912 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12098.129912 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12098.129912 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9946 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.010746 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 24573 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9958 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.467664 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5129655075000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 6.010746 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.375672 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 24609 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 24609 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 8553 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.010935 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 26637 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 8564 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 3.110346 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5140402124000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 6.010935 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.375683 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::1 26742 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26742 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 24612 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 24612 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 26745 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26745 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 24612 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 24612 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 10808 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10808 # number of ReadReq misses +system.cpu.itb_walker_cache.overall_hits::1 26745 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26745 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 9424 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9424 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 10808 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10808 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 9424 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9424 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 10808 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10808 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 135307500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 135307500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 135307500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 35417 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 35417 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 9424 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9424 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 120935500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 120935500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 120935500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 36166 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36166 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 35420 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 35420 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 36169 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36169 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 35420 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 35420 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.305164 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 36169 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36169 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.260576 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.305138 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.260555 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.305138 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.260555 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12519.198742 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12832.714346 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12519.198742 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12832.714346 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12519.198742 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12832.714346 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -684,83 +685,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 1317 # number of writebacks +system.cpu.itb_walker_cache.writebacks 1616 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 10808 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 10808 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 10808 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 9424 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 9424 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 9424 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 102536000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 102536000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 102536000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 92324000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 92324000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 92324000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.305164 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.260576 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.305138 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.260555 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.305138 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.260555 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9487.046632 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9487.046632 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9487.046632 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9796.689304 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9796.689304 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9796.689304 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 147569 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.856334 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 141316 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 147583 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 0.957536 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108660928000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.856334 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.866021 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 141317 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 141317 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 140574 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.858803 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 148049 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 140589 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.053062 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5108661869000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.858803 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.866175 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 148058 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 148058 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 141317 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 141317 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 148058 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 148058 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 141317 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 141317 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 148425 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 148425 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 148058 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 148058 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 141571 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 141571 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 148425 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 148425 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 141571 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 141571 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 148425 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 148425 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 2057871000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 2057871000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 2057871000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 289742 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 289742 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 141571 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 141571 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 1989434500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 1989434500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 1989434500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 289629 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 289629 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 289742 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 289742 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 289629 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 289629 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 289742 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 289742 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.512266 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 289629 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 289629 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.488801 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.512266 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.488801 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.512266 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.488801 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13864.719555 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 14052.556668 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13864.719555 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 14052.556668 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13864.719555 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 14052.556668 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -770,136 +771,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 45859 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 49457 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 148425 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 148425 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 148425 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 141571 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 141571 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 141571 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1608796000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1608796000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1608796000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1560743500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1560743500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1560743500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.512266 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.488801 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.512266 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.488801 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.512266 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.488801 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10839.117399 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10839.117399 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10839.117399 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 11024.457693 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 11024.457693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 11024.457693 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1662019 # number of replacements -system.cpu.dcache.tagsinuse 511.997109 # Cycle average of tags in use -system.cpu.dcache.total_refs 19289790 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1662531 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.602665 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 34336000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.997109 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11184512 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11184512 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 8099002 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8099002 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 19283514 # number of demand (read+write) hits +system.cpu.dcache.replacements 1662584 # number of replacements +system.cpu.dcache.tagsinuse 511.995323 # Cycle average of tags in use +system.cpu.dcache.total_refs 19274168 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1663096 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.589330 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 34335000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.995323 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 11173849 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11173849 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 8093995 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8093995 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 19267844 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19283514 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 19283514 # number of overall hits +system.cpu.dcache.demand_hits::total 19267844 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 19267844 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 19283514 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2387566 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2387566 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 320977 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 320977 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 2708543 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 19267844 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2389581 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2389581 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 320205 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 320205 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 2709786 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2708543 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 2708543 # number of overall misses +system.cpu.dcache.demand_misses::total 2709786 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 2709786 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2708543 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 35727347000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10720598495 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 46447945495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 46447945495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13572078 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13572078 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8419979 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8419979 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 21992057 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 2709786 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 35746262500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10712131492 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 46458393992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 46458393992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13563430 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563430 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8414200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8414200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 21977630 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21992057 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 21992057 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 21977630 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 21977630 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21992057 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.175917 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.038121 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.123160 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 21977630 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.176178 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.038055 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.123297 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.123160 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.123297 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 14963.920160 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 14959.217746 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33399.896239 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33453.979457 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 17148.683072 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 17144.672676 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 17148.683072 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 17144.672676 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28980495 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 27702492 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5023 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4792 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5769.559028 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5780.987479 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1550298 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1017351 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 22830 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1040181 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1040181 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1370215 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298147 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1668362 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1668362 # number of overall MSHR misses +system.cpu.dcache.writebacks 1550496 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1018010 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 22803 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1040813 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1040813 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1371571 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 297402 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1668973 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1668973 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 17997979500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9490426995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27488406495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27488406495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85207522500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1392017000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 86599539500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.100958 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18013626000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9484899492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27498525492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27498525492 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85207760000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1392508500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 86600268500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.101123 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035409 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035345 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.075862 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.075940 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.075862 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.075940 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13135.149958 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31831.368402 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16476.284221 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16476.284221 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13133.571649 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31892.520871 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16476.315370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16476.315370 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency |