diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
| commit | 9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch) | |
| tree | fab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/long/fs | |
| parent | 009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff) | |
| download | gem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz | |
stats: update stats for previous changes.
Diffstat (limited to 'tests/long/fs')
27 files changed, 4580 insertions, 4672 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 158e17e5b..aca491b43 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -12,14 +12,15 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/projects/pd/randd/dist/binaries/console +console=/gem5/dist/binaries/console init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux +kernel=/gem5/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing +mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/projects/pd/randd/dist/binaries/ts_osfpal +pal=/gem5/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -71,7 +72,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -131,6 +131,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu0.tracer trapLatency=13 @@ -147,21 +148,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -441,21 +437,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -502,7 +493,6 @@ cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -562,6 +552,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu1.tracer trapLatency=13 @@ -578,21 +569,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -872,21 +858,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -922,7 +903,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -942,7 +923,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/gem5/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -962,30 +943,25 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=BaseCache -addr_ranges=0:8589934591 +addr_ranges=0:134217727 assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[29] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c] type=BaseCache @@ -994,25 +970,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[1] [system.membus] type=CoherentBus @@ -1024,7 +995,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1077,7 +1048,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -1164,7 +1135,7 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 -clock=0 +clock=2000 config_latency=20000 dma_data_free=false dma_desc_free=false diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 200b08796..f4163d49e 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:02:14 -gem5 started Oct 30 2012 13:40:49 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:09:21 +gem5 started Jan 4 2013 21:41:13 +gem5 executing on u200540 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux +info: kernel located at: /gem5/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 107840000 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 59d7770e6..4908ce50e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.897858 # Nu sim_ticks 1897857556000 # Number of ticks simulated final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131170 # Simulator instruction rate (inst/s) -host_op_rate 131170 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4437782045 # Simulator tick rate (ticks/s) -host_mem_usage 332328 # Number of bytes of host memory used -host_seconds 427.66 # Real time elapsed on the host +host_inst_rate 54087 # Simulator instruction rate (inst/s) +host_op_rate 54087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1829896991 # Simulator tick rate (ticks/s) +host_mem_usage 335972 # Number of bytes of host memory used +host_seconds 1037.14 # Real time elapsed on the host sim_insts 56096024 # Number of instructions simulated sim_ops 56096024 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory @@ -913,8 +913,8 @@ system.cpu0.int_regfile_reads 60234005 # nu system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads -system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes +system.cpu0.misc_regfile_reads 1567878 # number of misc regfile reads +system.cpu0.misc_regfile_writes 765605 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1065,16 +1065,16 @@ system.cpu0.dcache.overall_misses::cpu0.data 3066244 system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591366614 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 67591366614 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591367114 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 67591367114 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4104500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4104500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263614 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 98980263614 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263614 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 98980263614 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses) @@ -1101,16 +1101,16 @@ system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251872 system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32280.621866 # average overall miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6107.886905 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6107.886905 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked @@ -1145,16 +1145,16 @@ system.cpu0.dcache.overall_mshr_misses::cpu0.data 1116427 system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225787 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225787 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2760500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275729287 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 29275729287 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275729287 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29275729287 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles @@ -1175,16 +1175,16 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4107.886905 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4107.886905 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1236,27 +1236,27 @@ system.cpu1.BPredUnit.BTBCorrect 0 # Nu system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions. system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed +system.cpu1.fetch.Insts 17895150 # Number of instructions fetch has processed system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.Cycles 3257695 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked +system.cpu1.fetch.BlockedCycles 9888414 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.CacheLines 2125845 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 78173 # Number of outstanding Icache misses that were squashed system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 18634783 85.12% 85.12% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 494264 2.26% 91.27% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total) @@ -1277,21 +1277,21 @@ system.cpu1.decode.BranchMispred 11788 # Nu system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running +system.cpu1.rename.IdleCycles 8509918 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2827280 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6300792 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2835388 # Number of cycles rename is running system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename +system.cpu1.rename.RenamedInsts 16406070 # Number of instructions processed by rename system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups +system.cpu1.rename.RenamedOperands 10874634 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 19629751 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 19484062 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing +system.cpu1.rename.UndoneMaps 1710462 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer @@ -1415,10 +1415,10 @@ system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking +system.cpu1.iew.iewBlockCycles 2193721 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispSquashedInsts 185761 # Number of squashed instructions skipped by dispatch system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions @@ -1493,23 +1493,23 @@ system.cpu1.int_regfile_reads 17892474 # nu system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes -system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads -system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes +system.cpu1.misc_regfile_reads 592079 # number of misc regfile reads +system.cpu1.misc_regfile_writes 255780 # number of misc regfile writes system.cpu1.icache.replacements 297472 # number of replacements system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use -system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks. +system.cpu1.icache.total_refs 1814153 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 6.088089 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit. system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits -system.cpu1.icache.overall_hits::total 1814154 # number of overall hits +system.cpu1.icache.ReadReq_hits::cpu1.inst 1814153 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1814153 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1814153 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1814153 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1814153 # number of overall hits +system.cpu1.icache.overall_hits::total 1814153 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses @@ -1522,12 +1522,12 @@ system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125845 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2125845 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2125845 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2125845 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2125845 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2125845 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses @@ -1606,32 +1606,32 @@ system.cpu1.dcache.WriteReq_misses::cpu1.data 341345 system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 718 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 718 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses system.cpu1.dcache.overall_misses::total 774607 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736455500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6736455500 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 20256376174 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 20256376174 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 20256376174 # number of overall miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 20256380174 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 20256380174 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 20256380174 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 20256380174 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 2469035 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 2469035 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 1516715 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 1516715 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 47099 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 47099 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43242 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 43242 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43241 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 43241 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 3985750 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 3985750 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 3985750 # number of overall (read+write) accesses @@ -1642,24 +1642,24 @@ system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225055 system.cpu1.dcache.WriteReq_miss_rate::total 0.225055 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016605 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016605 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7059.805285 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7059.805285 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26150.520424 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 26150.520424 # average overall miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7069.637883 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7069.637883 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26150.525588 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26150.525588 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 473544 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 3 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 7013 # number of cycles access was blocked @@ -1692,18 +1692,18 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123299000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123299000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152411304 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5152411304 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152411304 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5152411304 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles @@ -1716,24 +1716,24 @@ system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016605 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016605 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 4e3852a72..ebcbd1b8c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -12,14 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/projects/pd/randd/dist/binaries/console +console=/gem5/dist/binaries/console init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux +kernel=/gem5/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing +mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/projects/pd/randd/dist/binaries/ts_osfpal +pal=/gem5/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -71,7 +72,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -131,6 +131,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -147,21 +148,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -441,21 +437,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -478,25 +469,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus @@ -528,7 +514,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -548,7 +534,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/gem5/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -568,30 +554,25 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=BaseCache -addr_ranges=0:8589934591 +addr_ranges=0:134217727 assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[29] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.membus] type=CoherentBus @@ -603,7 +584,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port -slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side +slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -656,7 +637,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -733,7 +714,7 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 -clock=0 +clock=2000 config_latency=20000 dma_data_free=false dma_desc_free=false diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 6a7037f2d..5e5126f62 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:02:14 -gem5 started Oct 30 2012 13:34:06 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:09:21 +gem5 started Jan 4 2013 21:39:46 +gem5 executing on u200540 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux +info: kernel located at: /gem5/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1854349611000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index cbfa90061..37f4b3f46 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.854350 # Nu sim_ticks 1854349611000 # Number of ticks simulated final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135035 # Simulator instruction rate (inst/s) -host_op_rate 135035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4724741522 # Simulator tick rate (ticks/s) -host_mem_usage 327760 # Number of bytes of host memory used -host_seconds 392.48 # Real time elapsed on the host +host_inst_rate 55480 # Simulator instruction rate (inst/s) +host_op_rate 55480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1941178876 # Simulator tick rate (ticks/s) +host_mem_usage 331452 # Number of bytes of host memory used +host_seconds 955.27 # Real time elapsed on the host sim_insts 52998188 # Number of instructions simulated sim_ops 52998188 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory @@ -601,7 +601,7 @@ system.cpu.int_regfile_reads 73962724 # nu system.cpu.int_regfile_writes 40347354 # number of integer regfile writes system.cpu.fp_regfile_reads 166024 # number of floating regfile reads system.cpu.fp_regfile_writes 167429 # number of floating regfile writes -system.cpu.misc_regfile_reads 1993125 # number of misc regfile reads +system.cpu.misc_regfile_reads 1994989 # number of misc regfile reads system.cpu.misc_regfile_writes 947074 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index e4ef93067..4bccec155 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing +mem_ranges=0:134217727 memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,12 +65,12 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu] type=DerivO3CPU -children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer +children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -96,7 +96,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -118,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -155,6 +155,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -166,11 +167,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.checker] type=O3Checker -children=dtb itb tracer +children=dtb isa itb tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -179,6 +179,7 @@ exitOnError=false function_trace=false function_trace_start=0 interrupts=Null +isa=system.cpu.checker.isa itb=system.cpu.checker.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -187,6 +188,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.checker.tracer updateOnError=true @@ -206,6 +208,23 @@ num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] +[system.cpu.checker.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.checker.itb] type=ArmTLB children=walker @@ -229,21 +248,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -532,21 +546,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -555,6 +564,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -575,25 +601,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus @@ -624,30 +645,25 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache -addr_ranges=0:268435455 +addr_ranges=0:134217727 assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.membus] type=CoherentBus @@ -659,7 +675,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side +slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -789,11 +805,12 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=41667 +clock=1000 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 +pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 2082cdfd9..548ddf727 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,27 +10,23 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 5946987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 -warn: 5954355500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5963229500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5999905500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6015449500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 5947838000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 5955222500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5964126500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 6000836500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6016396500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 warn: LCD dual screen mode not supported -warn: 51801575500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: 51807341500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2473940227500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2487729164500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2488940395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2503139484500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 -warn: 2510001697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2510516362000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2516240346500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2516753495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2517315503000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2517316610000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2517867351500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 +warn: 2473965329500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2487749656500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2488961741500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2510016165000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2510533208500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2516263747000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2516773890500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2517336143500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2517337246000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2517887293500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index a3de8bb34..4c167b3ad 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 1 2012 15:18:10 -gem5 started Nov 2 2012 01:09:00 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 01:50:21 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2523500318000 because m5_exit instruction encountered +Exiting @ tick 2523517846500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 1c087a72b..9fdc8420f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523500 # Number of seconds simulated -sim_ticks 2523500318000 # Number of ticks simulated -final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523518 # Number of seconds simulated +sim_ticks 2523517846500 # Number of ticks simulated +final_tick 2523517846500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64209 # Simulator instruction rate (inst/s) -host_op_rate 82591 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2673913922 # Simulator tick rate (ticks/s) -host_mem_usage 441476 # Number of bytes of host memory used -host_seconds 943.75 # Real time elapsed on the host -sim_insts 60596849 # Number of instructions simulated -sim_ops 77944928 # Number of ops (including micro ops) simulated +host_inst_rate 18924 # Simulator instruction rate (inst/s) +host_op_rate 24341 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 788054860 # Simulator tick rate (ticks/s) +host_mem_usage 403628 # Number of bytes of host memory used +host_seconds 3202.21 # Real time elapsed on the host +sim_insts 60597240 # Number of instructions simulated +sim_ops 77945362 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 798272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799176 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096842 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813129 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1040 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51290337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499139 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1040 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096860 # Total number of read requests seen -system.physmem.writeReqs 813144 # Total number of write requests seen -system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966199040 # Total number of bytes read from memory -system.physmem.bytesWritten 52041216 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 316333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53984661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096842 # Total number of read requests seen +system.physmem.writeReqs 813129 # Total number of write requests seen +system.physmem.cpureqs 218393 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966197888 # Total number of bytes read from memory +system.physmem.bytesWritten 52040256 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129432080 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799176 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 355 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943949 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943429 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943294 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943633 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankRdReqs::13 943617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943223 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50104 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51125 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51177 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523499110500 # Total gap between requests +system.physmem.numWrRetry 1183132 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523516727500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154616 # Categorize read packet sizes +system.physmem.readPktSize::6 154598 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1907897 # categorize write packet sizes +system.physmem.writePktSize::2 1937150 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59126 # categorize write packet sizes +system.physmem.writePktSize::6 59111 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,30 +117,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1042834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 938516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 972890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2730387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2738053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5375105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 57584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 37998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 64788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -154,59 +154,59 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3875 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31479 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests -system.physmem.totBusLat 60386104000 # Total cycles spent in databus access -system.physmem.totBankLat 210282128000 # Total cycles spent in bank access -system.physmem.avgQLat 3116.78 # Average queueing delay per request -system.physmem.avgBankLat 13929.17 # Average bank access latency per request +system.physmem.totQLat 328143428340 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 404872878340 # Sum of mem lat for all requests +system.physmem.totBusLat 60385948000 # Total cycles spent in databus access +system.physmem.totBankLat 16343502000 # Total cycles spent in bank access +system.physmem.avgQLat 21736.41 # Average queueing delay per request +system.physmem.avgBankLat 1082.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgMemAccLat 26819.01 # Average memory access latency system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 11.37 # Average write queue length over time -system.physmem.readRowHits 15049962 # Number of row buffer hits during reads -system.physmem.writeRowHits 784769 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes -system.physmem.avgGap 158610.84 # Average gap between requests +system.physmem.avgRdQLen 0.16 # Average read queue length over time +system.physmem.avgWrQLen 11.85 # Average write queue length over time +system.physmem.readRowHits 15052691 # Number of row buffer hits during reads +system.physmem.writeRowHits 784814 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.52 # Row buffer hit rate for writes +system.physmem.avgGap 158612.28 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048842 # DTB read hits -system.cpu.checker.dtb.read_misses 7308 # DTB read misses -system.cpu.checker.dtb.write_hits 11294147 # DTB write hits +system.cpu.checker.dtb.read_hits 15048937 # DTB read hits +system.cpu.checker.dtb.read_misses 7310 # DTB read misses +system.cpu.checker.dtb.write_hits 11294198 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056150 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296336 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056247 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296387 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26342989 # DTB hits -system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26352486 # DTB accesses -system.cpu.checker.itb.inst_hits 61775601 # ITB inst hits +system.cpu.checker.dtb.hits 26343135 # DTB hits +system.cpu.checker.dtb.misses 9499 # DTB misses +system.cpu.checker.dtb.accesses 26352634 # DTB accesses +system.cpu.checker.itb.inst_hits 61775993 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -263,36 +263,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61780072 # ITB inst accesses -system.cpu.checker.itb.hits 61775601 # DTB hits +system.cpu.checker.itb.inst_accesses 61780464 # ITB inst accesses +system.cpu.checker.itb.hits 61775993 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61780072 # DTB accesses -system.cpu.checker.numCycles 78235487 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61780464 # DTB accesses +system.cpu.checker.numCycles 78235922 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51279526 # DTB read hits -system.cpu.dtb.read_misses 73667 # DTB read misses -system.cpu.dtb.write_hits 11753863 # DTB write hits -system.cpu.dtb.write_misses 17234 # DTB write misses +system.cpu.dtb.read_hits 51295505 # DTB read hits +system.cpu.dtb.read_misses 73548 # DTB read misses +system.cpu.dtb.write_hits 11769416 # DTB write hits +system.cpu.dtb.write_misses 17308 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7683 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7698 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2384 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 485 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51353193 # DTB read accesses -system.cpu.dtb.write_accesses 11771097 # DTB write accesses +system.cpu.dtb.perms_faults 1341 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51369053 # DTB read accesses +system.cpu.dtb.write_accesses 11786724 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63033389 # DTB hits -system.cpu.dtb.misses 90901 # DTB misses -system.cpu.dtb.accesses 63124290 # DTB accesses -system.cpu.itb.inst_hits 11603865 # ITB inst hits -system.cpu.itb.inst_misses 11359 # ITB inst misses +system.cpu.dtb.hits 63064921 # DTB hits +system.cpu.dtb.misses 90856 # DTB misses +system.cpu.dtb.accesses 63155777 # DTB accesses +system.cpu.itb.inst_hits 11599470 # ITB inst hits +system.cpu.itb.inst_misses 11387 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -301,122 +301,122 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5142 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5136 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2925 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11615224 # ITB inst accesses -system.cpu.itb.hits 11603865 # DTB hits -system.cpu.itb.misses 11359 # DTB misses -system.cpu.itb.accesses 11615224 # DTB accesses -system.cpu.numCycles 470951029 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11610857 # ITB inst accesses +system.cpu.itb.hits 11599470 # DTB hits +system.cpu.itb.misses 11387 # DTB misses +system.cpu.itb.accesses 11610857 # DTB accesses +system.cpu.numCycles 470965317 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits +system.cpu.BPredUnit.lookups 14487364 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11552940 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711872 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9478925 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7718754 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413170 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72913 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29863213 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90950612 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14487364 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9131924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20302505 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4756883 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122119 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96718680 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94285 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205383 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11595815 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 694954 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5716 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150585846 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.753226 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.110122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130298669 86.53% 86.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1345087 0.89% 87.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1687300 1.12% 88.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2309882 1.53% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2120076 1.41% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1117365 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2592055 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 766865 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8348547 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150585846 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030761 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.193115 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31645642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96356331 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18440866 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1036174 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106833 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1972079 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172496 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107972230 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569848 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106833 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33398103 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36860235 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53381295 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17668341 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6171039 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103073979 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21323 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016179 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4134721 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29043 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106845782 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 470577676 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 470486821 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90855 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 28114572 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 880520 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786795 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12341610 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19847152 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13390380 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1964070 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2407797 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95636460 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2047932 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123412976 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 169796 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19147761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47762380 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503425 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150585846 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.531798 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106411056 70.66% 70.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13811108 9.17% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7031286 4.67% 84.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5838601 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442775 8.26% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2756258 1.83% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1722165 1.14% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 442663 0.29% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 129934 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150585846 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60097 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available @@ -444,545 +444,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367175 94.63% 95.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 414340 4.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57952199 46.96% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93294 0.08% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52612072 42.63% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12389576 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued -system.cpu.iq.rate 0.261997 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123412976 # Type of FU issued +system.cpu.iq.rate 0.262043 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8841615 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071643 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406490722 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116848589 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85936823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22982 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12524 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131878765 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12160 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623393 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4131120 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30077 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1591861 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107803 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 700236 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106833 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27952249 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 439003 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97906020 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205363 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19847152 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13390380 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1460347 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 117327 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3551 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30077 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 353051 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272581 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625632 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121337067 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51981447 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075909 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220747 # number of nop insts executed -system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed -system.cpu.iew.exec_branches 11527542 # Number of branches executed -system.cpu.iew.exec_stores 12265452 # Number of stores executed -system.cpu.iew.exec_rate 0.257499 # Inst execution rate -system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47162688 # num instructions producing a value -system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value +system.cpu.iew.exec_nop 221628 # number of nop insts executed +system.cpu.iew.exec_refs 64262784 # number of memory reference insts executed +system.cpu.iew.exec_branches 11537560 # Number of branches executed +system.cpu.iew.exec_stores 12281337 # Number of stores executed +system.cpu.iew.exec_rate 0.257635 # Inst execution rate +system.cpu.iew.wb_sent 120375089 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85947111 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47183541 # num instructions producing a value +system.cpu.iew.wb_consumers 88082196 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182491 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535676 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18905107 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544507 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541940 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147479013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529538 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516870 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119767946 81.21% 81.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13521242 9.17% 90.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3932347 2.67% 93.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2139837 1.45% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947041 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 981141 0.67% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1580635 1.07% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 757975 0.51% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2850849 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747230 # Number of instructions committed -system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147479013 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747621 # Number of instructions committed +system.cpu.commit.committedOps 78095743 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514399 # Number of memory references committed -system.cpu.commit.loads 15715935 # Number of loads committed -system.cpu.commit.membars 413101 # Number of memory barriers committed -system.cpu.commit.branches 10023041 # Number of branches committed +system.cpu.commit.refs 27514551 # Number of memory references committed +system.cpu.commit.loads 15716032 # Number of loads committed +system.cpu.commit.membars 413105 # Number of memory barriers committed +system.cpu.commit.branches 10023101 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. -system.cpu.commit.function_calls 995976 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69134175 # Number of committed integer instructions. +system.cpu.commit.function_calls 995982 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2850849 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239806361 # The number of ROB reads -system.cpu.rob.rob_writes 197293644 # The number of ROB writes -system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60596849 # Number of Instructions Simulated -system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated -system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 549353820 # number of integer regfile reads -system.cpu.int_regfile_writes 87979072 # number of integer regfile writes -system.cpu.fp_regfile_reads 8318 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads -system.cpu.misc_regfile_writes 912865 # number of misc regfile writes -system.cpu.icache.replacements 980837 # number of replacements -system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use -system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor +system.cpu.rob.rob_reads 239713879 # The number of ROB reads +system.cpu.rob.rob_writes 197204165 # The number of ROB writes +system.cpu.timesIdled 1775890 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320379471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575982354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60597240 # Number of Instructions Simulated +system.cpu.committedOps 77945362 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60597240 # Number of Instructions Simulated +system.cpu.cpi 7.772059 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.772059 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128666 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128666 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549724993 # number of integer regfile reads +system.cpu.int_regfile_writes 88045460 # number of integer regfile writes +system.cpu.fp_regfile_reads 8276 # number of floating regfile reads +system.cpu.fp_regfile_writes 2926 # number of floating regfile writes +system.cpu.misc_regfile_reads 30431218 # number of misc regfile reads +system.cpu.misc_regfile_writes 912900 # number of misc regfile writes +system.cpu.icache.replacements 981280 # number of replacements +system.cpu.icache.tagsinuse 511.007424 # Cycle average of tags in use +system.cpu.icache.total_refs 10533801 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981792 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.729157 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6666221000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.007424 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits -system.cpu.icache.overall_hits::total 10539450 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses -system.cpu.icache.overall_misses::total 1060605 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand 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(read+write) misses +system.cpu.icache.demand_misses::total 1061888 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061888 # number of overall misses +system.cpu.icache.overall_misses::total 1061888 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13967491489 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13967491489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13967491489 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13967491489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13967491489 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13967491489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11595689 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11595689 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11595689 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11595689 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11595689 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11595689 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091576 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091576 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091576 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091576 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091576 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091576 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13153.450730 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13153.450730 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13153.450730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13153.450730 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5396 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1220 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.808581 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 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-system.cpu.icache.demand_mshr_misses::total 981391 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981391 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981391 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11354795991 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11354795991 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11354795991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80057 # number of ReadReq MSHR hits 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miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084672 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.084672 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.084672 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.406015 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.406015 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 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ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks -system.cpu.dcache.writebacks::total 607749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 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rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses 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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1103,6 +941,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 643581 # number of replacements +system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use +system.cpu.dcache.total_refs 21676734 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644093 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.654665 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13816029 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13816029 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7289413 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7289413 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 282441 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 282441 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285740 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285740 # number of StoreCondReq hits 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miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 244000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113591601731 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113591601731 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113591601731 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113591601731 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14547863 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14547863 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250668 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250668 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296044 # number of LoadLockedReq accesses(hits+misses) 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0.288884 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045949 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045949 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148924 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148924 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148924 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148924 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.548559 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.548559 # average ReadReq miss latency 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+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712226 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2712226 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1428 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1428 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3058209 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3058209 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3058209 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3058209 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385851 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385851 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249029 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249029 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634880 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634880 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634880 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634880 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768256000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768256000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8126256417 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8126256417 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140756500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140756500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 212000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 212000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12894512417 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12894512417 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12894512417 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12894512417 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182401837500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182401837500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28201633550 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28201633550 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210603471050 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210603471050 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041126 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041126 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025602 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025602 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12357.765044 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12357.765044 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32631.767453 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32631.767453 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11561.108830 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11561.108830 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13250 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1117,16 +1117,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1148123553642 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1148123553642 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88023 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index f6cdc434a..691cf1068 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing +mem_ranges=0:134217727 memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,12 +65,12 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -96,7 +96,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -118,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -155,6 +155,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu0.tracer trapLatency=13 @@ -171,21 +172,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -474,21 +470,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -497,6 +488,23 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=ArmInterrupts +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu0.itb] type=ArmTLB children=walker @@ -515,7 +523,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -541,7 +549,6 @@ cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -563,6 +570,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -600,6 +608,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu1.tracer trapLatency=13 @@ -616,21 +625,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -919,21 +923,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -942,6 +941,23 @@ mem_side=system.toL2Bus.slave[4] [system.cpu1.interrupts] type=ArmInterrupts +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu1.itb] type=ArmTLB children=walker @@ -974,30 +990,25 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache -addr_ranges=0:268435455 +addr_ranges=0:134217727 assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c] type=BaseCache @@ -1006,25 +1017,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[1] [system.membus] type=CoherentBus @@ -1036,7 +1042,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1166,11 +1172,12 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=41667 +clock=1000 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 +pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 523f8a126..e8e271d58 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -12,8 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index ac731cab9..7a0146bc3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 21:14:52 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 02:00:26 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2593146078000 because m5_exit instruction encountered +Exiting @ tick 2603185215000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3f5cdc3ab..de425fd79 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,135 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.593146 # Number of seconds simulated -sim_ticks 2593146078000 # Number of ticks simulated -final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603185 # Number of seconds simulated +sim_ticks 2603185215000 # Number of ticks simulated +final_tick 2603185215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77303 # Simulator instruction rate (inst/s) -host_op_rate 99505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3178225665 # Simulator tick rate (ticks/s) -host_mem_usage 449664 # Number of bytes of host memory used -host_seconds 815.91 # Real time elapsed on the host -sim_insts 63072130 # Number of instructions simulated -sim_ops 81187111 # Number of ops (including micro ops) simulated +host_inst_rate 24146 # Simulator instruction rate (inst/s) +host_op_rate 31077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 996702828 # Simulator tick rate (ticks/s) +host_mem_usage 410224 # Number of bytes of host memory used +host_seconds 2611.80 # Real time elapsed on the host +sim_insts 63063952 # Number of instructions simulated +sim_ops 81166306 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4376500 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 426752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5261232 # Number of bytes read from this memory -system.physmem.bytes_read::total 131572388 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 426752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282048 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 396288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4383412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5252400 # Number of bytes read from this memory +system.physmem.bytes_read::total 131570212 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4280832 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7311184 # Number of bytes written to this memory +system.physmem.bytes_written::total 7309968 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68455 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82233 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302381 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66907 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6192 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82095 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302347 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66888 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824191 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46704090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 152451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1687718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2028899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50738518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 152451 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164569 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1651295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6556 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1161576 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2819426 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1651295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46704090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 152451 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1694274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3190475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53557944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302381 # Total number of read requests seen -system.physmem.writeReqs 824191 # Total number of write requests seen -system.physmem.cpureqs 284713 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979352384 # Total number of bytes read from memory -system.physmem.bytesWritten 52748224 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131572388 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7311184 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 335 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14131 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956655 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956499 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956473 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956086 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 957009 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 956354 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 956393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 956606 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 956542 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955941 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50933 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51869 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51569 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51383 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51546 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51788 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51769 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51735 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51546 # Track writes on a per bank basis +system.physmem.num_writes::total 824172 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46523977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 152232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1683865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 163467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2017682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50542010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 152232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 163467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315699 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1644459 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1157096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2808086 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1644459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46523977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 152232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1690395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 163467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3174778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53350096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302347 # Total number of read requests seen +system.physmem.writeReqs 824172 # Total number of write requests seen +system.physmem.cpureqs 284728 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979350208 # Total number of bytes read from memory +system.physmem.bytesWritten 52747008 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131570212 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7309968 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 346 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14078 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956691 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956557 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956110 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955970 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 956364 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 956322 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 956651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956317 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 956502 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955936 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50766 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50996 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51588 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51566 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52101 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51588 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51672 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51523 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1150487 # Number of times wr buffer was full causing retry -system.physmem.totGap 2593144762500 # Total gap between requests +system.physmem.numWrRetry 1182222 # Number of times wr buffer was full causing retry +system.physmem.totGap 2603183939000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163460 # Categorize read packet sizes +system.physmem.readPktSize::6 163426 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1907771 # categorize write packet sizes +system.physmem.writePktSize::2 1939506 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66907 # categorize write packet sizes +system.physmem.writePktSize::6 66888 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -138,29 +134,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 14131 # categorize neither packet sizes +system.physmem.neitherpktsize::6 14078 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 15151641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 94331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1062295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 996413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 951405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 986255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2765519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2772335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5446641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 44668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 31245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 58473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 38578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 65793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3001 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -174,60 +170,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4366 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31468 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 47868619345 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 322210199345 # Sum of mem lat for all requests -system.physmem.totBusLat 61208184000 # Total cycles spent in databus access -system.physmem.totBankLat 213133396000 # Total cycles spent in bank access -system.physmem.avgQLat 3128.25 # Average queueing delay per request -system.physmem.avgBankLat 13928.42 # Average bank access latency per request +system.physmem.totQLat 332610890470 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 410507230470 # Sum of mem lat for all requests +system.physmem.totBusLat 61208004000 # Total cycles spent in databus access +system.physmem.totBankLat 16688336000 # Total cycles spent in bank access +system.physmem.avgQLat 21736.43 # Average queueing delay per request +system.physmem.avgBankLat 1090.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21056.67 # Average memory access latency -system.physmem.avgRdBW 377.67 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.34 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.82 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 26827.03 # Average memory access latency +system.physmem.avgRdBW 376.21 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.49 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.12 # Average read queue length over time -system.physmem.avgWrQLen 10.88 # Average write queue length over time -system.physmem.readRowHits 15253448 # Number of row buffer hits during reads -system.physmem.writeRowHits 789566 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads +system.physmem.busUtil 2.48 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.16 # Average read queue length over time +system.physmem.avgWrQLen 12.97 # Average write queue length over time +system.physmem.readRowHits 15255805 # Number of row buffer hits during reads +system.physmem.writeRowHits 789541 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes -system.physmem.avgGap 160799.50 # Average gap between requests +system.physmem.avgGap 161422.56 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -239,258 +235,244 @@ system.realview.nvmem.num_reads::cpu1.inst 6 # system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 173 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 173 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 173 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 73184 # number of replacements -system.l2c.tagsinuse 53096.266008 # Cycle average of tags in use -system.l2c.total_refs 1906265 # Total number of references to valid blocks. -system.l2c.sampled_refs 138351 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.778469 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 73139 # number of replacements +system.l2c.tagsinuse 53098.784053 # Cycle average of tags in use +system.l2c.total_refs 1903330 # Total number of references to valid blocks. +system.l2c.sampled_refs 138315 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.760836 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37733.790025 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 7.219153 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4206.047810 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2960.317078 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.178862 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.966447 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4058.933416 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4117.812877 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575772 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000110 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37803.409303 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 5.317240 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.004373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4191.158517 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2951.048787 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 13.024682 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4037.185847 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4097.635305 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.576834 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 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of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 53008 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6038 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 608232 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 201468 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1465388 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583960 # number of Writeback hits -system.l2c.Writeback_hits::total 583960 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1107 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 848 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1955 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits +system.l2c.occ_percent::cpu0.inst 0.063952 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045029 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000199 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061603 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062525 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.810223 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 33629 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4816 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 393434 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165508 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 53340 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6018 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 607751 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201341 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1465837 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 582635 # number of Writeback hits +system.l2c.Writeback_hits::total 582635 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1118 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 732 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1850 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 368 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47823 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59123 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106946 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 33579 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 393016 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 212907 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 53008 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6038 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 608232 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260591 # number of demand (read+write) hits -system.l2c.demand_hits::total 1572334 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 33579 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4963 # number of overall hits -system.l2c.overall_hits::cpu0.inst 393016 # number of overall hits -system.l2c.overall_hits::cpu0.data 212907 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 53008 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6038 # number of overall hits -system.l2c.overall_hits::cpu1.inst 608232 # number of overall hits -system.l2c.overall_hits::cpu1.data 260591 # number of overall hits -system.l2c.overall_hits::total 1572334 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6056 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6345 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6633 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6362 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25428 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5684 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4404 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10088 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 773 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 585 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1358 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63519 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77106 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140625 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6056 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69864 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6633 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83468 # number of demand (read+write) misses -system.l2c.demand_misses::total 166053 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6056 # number of overall misses -system.l2c.overall_misses::cpu0.data 69864 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6633 # number of overall misses -system.l2c.overall_misses::cpu1.data 83468 # number of overall misses -system.l2c.overall_misses::total 166053 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1175500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 320358500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 344253498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1038500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 122500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 371653000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 369594500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1408313998 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 9084989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12192500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21277489 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2932000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3523000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3155374488 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4272368491 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7427742979 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1175500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 320358500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3499627986 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1038500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 122500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 371653000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4641962991 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8836056977 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1175500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 320358500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3499627986 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1038500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 122500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 371653000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4641962991 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8836056977 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 33593 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4965 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 399072 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 171429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 53023 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6039 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 614865 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 207830 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1490816 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 583960 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 583960 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6791 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5252 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 12043 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 982 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 744 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1726 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111342 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 136229 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247571 # number of ReadExReq accesses(hits+misses) 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-system.l2c.overall_mshr_uncacheable_latency::total 185427370895 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036785 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030491 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017006 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.836990 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.838538 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.837665 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787169 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786290 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.786790 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570486 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566003 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.568019 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.095478 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.095478 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41581.881859 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45433.619852 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 42739.057192 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.183673 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10162.641916 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.237411 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.377749 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.136752 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10044.427835 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37301.377525 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42974.593287 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40412.054677 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13393471796 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1893563 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172316371500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 185716295022 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036773 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030263 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016973 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.835298 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.856386 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.844342 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783231 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786003 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784428 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.571798 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565799 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568496 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.242351 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.095451 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.242351 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.095451 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42313.900949 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 44452.303628 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42058.111023 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10079.971605 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10142.215349 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10107.046238 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10064.283290 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.691781 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.830370 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36873.037733 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42513.081479 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39962.425613 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37364.803873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42659.334233 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37364.803873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42659.334233 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -695,27 +665,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9014303 # DTB read hits -system.cpu0.dtb.read_misses 34965 # DTB read misses -system.cpu0.dtb.write_hits 5253714 # DTB write hits -system.cpu0.dtb.write_misses 6399 # DTB write misses +system.cpu0.dtb.read_hits 9024363 # DTB read hits +system.cpu0.dtb.read_misses 35062 # DTB read misses +system.cpu0.dtb.write_hits 5257895 # DTB write hits +system.cpu0.dtb.write_misses 6477 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2155 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1094 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 321 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2160 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9049268 # DTB read accesses -system.cpu0.dtb.write_accesses 5260113 # DTB write accesses +system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9059425 # DTB read accesses +system.cpu0.dtb.write_accesses 5264372 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14268017 # DTB hits -system.cpu0.dtb.misses 41364 # DTB misses -system.cpu0.dtb.accesses 14309381 # DTB accesses -system.cpu0.itb.inst_hits 4294311 # ITB inst hits -system.cpu0.itb.inst_misses 5261 # ITB inst misses +system.cpu0.dtb.hits 14282258 # DTB hits +system.cpu0.dtb.misses 41539 # DTB misses +system.cpu0.dtb.accesses 14323797 # DTB accesses +system.cpu0.itb.inst_hits 4307156 # ITB inst hits +system.cpu0.itb.inst_misses 5205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -724,156 +694,156 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1385 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1360 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1364 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4299572 # ITB inst accesses -system.cpu0.itb.hits 4294311 # DTB hits -system.cpu0.itb.misses 5261 # DTB misses -system.cpu0.itb.accesses 4299572 # DTB accesses -system.cpu0.numCycles 69013505 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4312361 # ITB inst accesses +system.cpu0.itb.hits 4307156 # DTB hits +system.cpu0.itb.misses 5205 # DTB misses +system.cpu0.itb.accesses 4312361 # DTB accesses +system.cpu0.numCycles 69075583 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6123831 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4675790 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 298271 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3798227 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2989296 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6134621 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4681383 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 299233 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3810859 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2992358 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 685728 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 28375 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 11998527 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32710943 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6123831 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3675024 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7667644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1480146 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 66638 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21758305 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5862 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 53793 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 221 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4292744 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 155269 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2401 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42704543 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.988603 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.369673 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 688987 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 28743 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12013253 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32740564 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6134621 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3681345 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7677557 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1482239 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 64559 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21828282 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 53864 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90312 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 236 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4305560 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 159104 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2370 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42798314 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.987162 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.368020 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35044149 82.06% 82.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 606065 1.42% 83.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 793528 1.86% 85.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 689319 1.61% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 781424 1.83% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 567584 1.33% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 711320 1.67% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 364019 0.85% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3147135 7.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35128127 82.08% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 610328 1.43% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 795353 1.86% 85.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 689183 1.61% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 781372 1.83% 88.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 569733 1.33% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 711695 1.66% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364225 0.85% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3148298 7.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42704543 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088734 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.473979 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12497333 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21726841 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6896095 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 584636 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 999638 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 951812 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64726 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40836330 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213865 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 999638 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13071648 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5812993 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13759259 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6855374 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2205631 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39711904 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2173 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 427558 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1242268 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 68 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40116309 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 179435830 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 179401258 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34572 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31681024 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8435284 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 457771 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 414521 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5443309 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7819363 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5820332 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1146243 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1242216 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37575405 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 946067 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37951575 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 82274 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6366228 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13456450 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257591 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42704543 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.888701 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.500077 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42798314 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088810 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.473982 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12517044 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21792466 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6901256 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 586970 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1000578 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 954803 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64851 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40861344 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213562 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1000578 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13092600 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5813788 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13806762 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6861684 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2222902 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39740402 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2257 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 444272 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1240471 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 77 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40148585 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 179562690 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 179528337 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34353 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31678708 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8469876 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 458191 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414927 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5465728 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7827563 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5820560 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1149873 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1213359 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37598856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 946637 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37967135 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82667 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6387129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13438267 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 258027 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42798314 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.887118 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.498670 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27159670 63.60% 63.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6000291 14.05% 77.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3232720 7.57% 85.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2489147 5.83% 91.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2132528 4.99% 96.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 950123 2.22% 98.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 497063 1.16% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 188710 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54291 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27228481 63.62% 63.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6024200 14.08% 77.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3238541 7.57% 85.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2496476 5.83% 91.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2116280 4.94% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 952748 2.23% 98.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 498209 1.16% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188721 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54658 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42704543 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42798314 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 24659 2.31% 2.31% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 467 0.04% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 838061 78.41% 80.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 205631 19.24% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25719 2.40% 2.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 458 0.04% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 838558 78.31% 80.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 206136 19.25% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22793341 60.06% 60.20% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48224 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22801553 60.06% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48143 0.13% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued @@ -883,10 +853,10 @@ system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Ty system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued @@ -897,365 +867,365 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9480747 24.98% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5576214 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9487186 24.99% 85.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5577397 14.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37951575 # Type of FU issued -system.cpu0.iq.rate 0.549915 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1068818 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028163 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 119791525 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44895833 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35071497 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8304 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3884 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38963714 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4335 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 318123 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37967135 # Type of FU issued +system.cpu0.iq.rate 0.549646 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070871 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028205 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119919123 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44940813 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35094596 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8245 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4688 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3877 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38981568 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4289 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 319568 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1396327 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2506 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13403 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 544501 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1406645 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2495 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13426 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 546497 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149359 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5385 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149373 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5419 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 999638 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4184428 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 103741 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38639126 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85944 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7819363 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5820332 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 614711 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 41414 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3290 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13403 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 151339 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 119425 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 270764 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37563861 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9331167 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 387714 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1000578 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4177293 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 102909 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38663154 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 84882 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7827563 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5820560 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 615194 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 41110 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3269 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13426 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151880 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 119782 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 271662 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37584827 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9341263 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 382308 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117654 # number of nop insts executed -system.cpu0.iew.exec_refs 14857557 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4958494 # Number of branches executed -system.cpu0.iew.exec_stores 5526390 # Number of stores executed -system.cpu0.iew.exec_rate 0.544297 # Inst execution rate -system.cpu0.iew.wb_sent 37365472 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35075381 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18655901 # num instructions producing a value -system.cpu0.iew.wb_consumers 35819655 # num instructions consuming a value +system.cpu0.iew.exec_nop 117661 # number of nop insts executed +system.cpu0.iew.exec_refs 14871823 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4965899 # Number of branches executed +system.cpu0.iew.exec_stores 5530560 # Number of stores executed +system.cpu0.iew.exec_rate 0.544112 # Inst execution rate +system.cpu0.iew.wb_sent 37390069 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35098473 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18662098 # num instructions producing a value +system.cpu0.iew.wb_consumers 35837598 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.508239 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520829 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.508117 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520741 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6205381 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688476 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 234604 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41741265 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.766601 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.727877 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6206788 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688610 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 235451 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41797736 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.765444 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.723461 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29720457 71.20% 71.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5963123 14.29% 85.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1948324 4.67% 90.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1002440 2.40% 92.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 789371 1.89% 94.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 520489 1.25% 95.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 393953 0.94% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 216687 0.52% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1186421 2.84% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29752237 71.18% 71.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5970878 14.29% 85.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1965315 4.70% 90.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 999760 2.39% 92.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 803961 1.92% 94.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 518760 1.24% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395530 0.95% 96.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 220150 0.53% 97.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1171145 2.80% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41741265 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24264310 # Number of instructions committed -system.cpu0.commit.committedOps 31998915 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41797736 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24265529 # Number of instructions committed +system.cpu0.commit.committedOps 31993822 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11698867 # Number of memory references committed -system.cpu0.commit.loads 6423036 # Number of loads committed -system.cpu0.commit.membars 234373 # Number of memory barriers committed -system.cpu0.commit.branches 4346960 # Number of branches committed +system.cpu0.commit.refs 11694981 # Number of memory references committed +system.cpu0.commit.loads 6420918 # Number of loads committed +system.cpu0.commit.membars 234476 # Number of memory barriers committed +system.cpu0.commit.branches 4347395 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28266871 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499893 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1186421 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28261624 # Number of committed integer instructions. +system.cpu0.commit.function_calls 500034 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1171145 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77875275 # The number of ROB reads -system.cpu0.rob.rob_writes 77410136 # The number of ROB writes -system.cpu0.timesIdled 364830 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26308962 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5117234895 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24183568 # Number of Instructions Simulated -system.cpu0.committedOps 31918173 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24183568 # Number of Instructions Simulated -system.cpu0.cpi 2.853735 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.853735 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.350418 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.350418 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 175323075 # number of integer regfile reads -system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads -system.cpu0.fp_regfile_writes 906 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13342715 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes -system.cpu0.icache.replacements 399233 # number of replacements -system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use -system.cpu0.icache.total_refs 3861943 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 399745 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.661016 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6802423000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.592262 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999204 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999204 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3861943 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3861943 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3861943 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3861943 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3861943 # number of overall hits -system.cpu0.icache.overall_hits::total 3861943 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 430668 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 430668 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 430668 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 430668 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 430668 # number of overall misses -system.cpu0.icache.overall_misses::total 430668 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5857521993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5857521993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5857521993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5857521993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5857521993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5857521993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4292611 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4292611 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4292611 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4292611 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4292611 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4292611 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100328 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100328 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100328 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100328 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100328 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100328 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13601.015151 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13601.015151 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13601.015151 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13601.015151 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2687 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77942939 # The number of ROB reads +system.cpu0.rob.rob_writes 77403720 # The number of ROB writes +system.cpu0.timesIdled 364282 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26277269 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5137251054 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24184787 # Number of Instructions Simulated +system.cpu0.committedOps 31913080 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24184787 # Number of Instructions Simulated +system.cpu0.cpi 2.856158 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.856158 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.350121 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.350121 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 175453235 # number of integer regfile reads +system.cpu0.int_regfile_writes 34873256 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3235 # number of floating regfile reads +system.cpu0.fp_regfile_writes 908 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13424511 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527689 # number of misc regfile writes +system.cpu0.icache.replacements 399628 # number of replacements +system.cpu0.icache.tagsinuse 511.593033 # Cycle average of tags in use +system.cpu0.icache.total_refs 3873847 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 400140 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.681229 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6818802000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.593033 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999205 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999205 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3873847 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3873847 # number of ReadReq hits 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+system.cpu0.dcache.WriteReq_miss_latency::total 60454939374 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88150000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88150000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50211500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 50211500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 65843987874 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 65843987874 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 65843987874 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 65843987874 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6285689 # number of ReadReq accesses(hits+misses) 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accesses +system.cpu0.dcache.overall_accesses::total 11104251 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062139 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062139 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327810 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.327810 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048519 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048519 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043099 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043099 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177424 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.177424 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177424 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.177424 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.306362 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.306362 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38272.963246 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38272.963246 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9908.947842 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9908.947842 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6497.347308 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6497.347308 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33420.629733 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33420.629733 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8059 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2986 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 556 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.494604 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 37.325000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255577 # number of writebacks -system.cpu0.dcache.writebacks::total 255577 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202032 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202032 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450989 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1450989 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 498 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 498 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653021 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1653021 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653021 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1653021 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188734 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188734 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131032 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131032 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8374 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8374 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319766 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319766 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319766 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319766 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2333622500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2333622500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054127491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054127491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66245000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66245000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34997500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34997500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6387749991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6387749991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6387749991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6387749991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431600500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431600500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199905877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199905877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631506377 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631506377 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030063 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030063 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027183 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027183 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045875 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045875 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043166 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043166 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028812 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028812 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7910.795319 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7910.795319 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4522.225094 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4522.225094 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255180 # number of writebacks +system.cpu0.dcache.writebacks::total 255180 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202008 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202008 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1448555 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1448555 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 484 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 484 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650563 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1650563 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650563 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1650563 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188579 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188579 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131018 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131018 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8412 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8412 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7726 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7726 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319597 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319597 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319597 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319597 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2343972000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2343972000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4029495991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4029495991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66259000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66259000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34759500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34759500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6373467991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6373467991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6373467991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6373467991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432446000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432446000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199878877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199878877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14632324877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14632324877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030001 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030001 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045879 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045879 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043088 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043088 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028781 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028781 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12429.655476 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12429.655476 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30755.285465 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30755.285465 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7876.723728 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7876.723728 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4499.029252 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4499.029252 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1265,27 +1235,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43030291 # DTB read hits -system.cpu1.dtb.read_misses 42638 # DTB read misses -system.cpu1.dtb.write_hits 6991861 # DTB write hits -system.cpu1.dtb.write_misses 11867 # DTB write misses +system.cpu1.dtb.read_hits 43034108 # DTB read hits +system.cpu1.dtb.read_misses 42641 # DTB read misses +system.cpu1.dtb.write_hits 7001737 # DTB write hits +system.cpu1.dtb.write_misses 11814 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2362 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2846 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.flush_entries 2370 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2838 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 690 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43072929 # DTB read accesses -system.cpu1.dtb.write_accesses 7003728 # DTB write accesses +system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43076749 # DTB read accesses +system.cpu1.dtb.write_accesses 7013551 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50022152 # DTB hits -system.cpu1.dtb.misses 54505 # DTB misses -system.cpu1.dtb.accesses 50076657 # DTB accesses -system.cpu1.itb.inst_hits 7786412 # ITB inst hits -system.cpu1.itb.inst_misses 5635 # ITB inst misses +system.cpu1.dtb.hits 50035845 # DTB hits +system.cpu1.dtb.misses 54455 # DTB misses +system.cpu1.dtb.accesses 50090300 # DTB accesses +system.cpu1.itb.inst_hits 7783284 # ITB inst hits +system.cpu1.itb.inst_misses 5669 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1294,538 +1264,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1584 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1542 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7792047 # ITB inst accesses -system.cpu1.itb.hits 7786412 # DTB hits -system.cpu1.itb.misses 5635 # DTB misses -system.cpu1.itb.accesses 7792047 # DTB accesses -system.cpu1.numCycles 409024249 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7788953 # ITB inst accesses +system.cpu1.itb.hits 7783284 # DTB hits +system.cpu1.itb.misses 5669 # DTB misses +system.cpu1.itb.accesses 7788953 # DTB accesses +system.cpu1.numCycles 409060969 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9020667 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7346445 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 421687 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 5902094 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5066087 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9019142 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7341577 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 421290 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 5896961 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5059614 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 810235 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 44717 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 19548819 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 61628162 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9020667 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5876322 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13445282 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3432135 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 71958 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78159434 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 48212 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 140837 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7784486 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 545452 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3066 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 113770833 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.663645 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.994153 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 812166 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 44802 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 19538569 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61710735 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9019142 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5871780 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13457716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3440559 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 72159 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78167878 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5662 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 49809 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 140998 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7781352 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 538014 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3102 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113786982 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.664391 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.995438 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100333102 88.19% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 820750 0.72% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 967014 0.85% 89.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1722421 1.51% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1420935 1.25% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 598048 0.53% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1962596 1.73% 94.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 435893 0.38% 95.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5510074 4.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100336589 88.18% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 821334 0.72% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 966420 0.85% 89.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1725152 1.52% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1418529 1.25% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 601242 0.53% 93.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1958088 1.72% 94.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 436465 0.38% 95.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5523163 4.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 113770833 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022054 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.150671 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20932611 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77783544 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12260401 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 543319 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2250958 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1146967 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100968 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 71503765 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 336196 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2250958 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22152530 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32126143 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41276446 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11489660 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4475096 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 67542275 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19496 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 697256 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3178756 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 32684 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 70870880 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 310023883 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 309964693 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59190 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50213421 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20657459 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 473589 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 413624 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8131877 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12919526 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8160199 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1076421 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1515550 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 62172086 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1201080 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89161848 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 100982 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13762748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36926540 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 280453 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 113770833 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.783697 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520241 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113786982 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022048 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.150860 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20926147 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77797918 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12266013 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 542191 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2254713 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1149115 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100993 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71511004 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 338807 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2254713 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22129407 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32117603 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41299485 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11510444 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4475330 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67658360 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19594 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 697706 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3178110 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 32539 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70993653 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 310596355 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 310537273 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59082 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50200074 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20793579 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 474201 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 414075 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8134070 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12921007 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8155176 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1083797 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1589261 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 62166896 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1195329 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89153414 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 99788 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13746763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36760953 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 275268 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113786982 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.783512 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519359 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83205809 73.13% 73.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8622127 7.58% 80.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4341809 3.82% 84.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3750529 3.30% 87.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10472490 9.20% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1973623 1.73% 98.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1061651 0.93% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 265825 0.23% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 76970 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83183185 73.10% 73.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8664055 7.61% 80.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4355929 3.83% 84.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3746204 3.29% 87.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10471181 9.20% 97.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1956933 1.72% 98.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1074012 0.94% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 258436 0.23% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 77047 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 113770833 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113786982 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29803 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 992 0.01% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7572506 95.90% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 293239 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29283 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 991 0.01% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7571422 95.88% 96.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 294824 3.73% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37491969 42.05% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61148 0.07% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43923048 49.26% 91.73% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7369892 8.27% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37493479 42.06% 42.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61246 0.07% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43910750 49.25% 91.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7372221 8.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89161848 # Type of FU issued -system.cpu1.iq.rate 0.217987 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7896540 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088564 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300131429 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 77144913 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54450273 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14948 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8092 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6814 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96736439 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7887 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 357826 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89153414 # Type of FU issued +system.cpu1.iq.rate 0.217947 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7896520 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088572 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300129512 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 77117892 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54483079 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14896 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8093 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96728092 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7845 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 354516 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2919371 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4089 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1133342 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2925065 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4096 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17562 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1131401 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965401 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 692354 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31964883 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 695794 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2250958 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24192691 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 367138 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63477454 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 113697 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12919526 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8160199 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 893697 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 68960 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3858 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17660 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 208465 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 159370 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 367835 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87401818 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43412086 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1760030 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2254713 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24187633 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 367329 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63466208 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 114663 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12921007 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8155176 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 887376 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 69283 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3741 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17562 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 208254 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 160111 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 368365 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87428231 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43415449 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1725183 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104288 # number of nop insts executed -system.cpu1.iew.exec_refs 50709476 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7088545 # Number of branches executed -system.cpu1.iew.exec_stores 7297390 # Number of stores executed -system.cpu1.iew.exec_rate 0.213684 # Inst execution rate -system.cpu1.iew.wb_sent 86601126 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54457087 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30364436 # num instructions producing a value -system.cpu1.iew.wb_consumers 54295656 # num instructions consuming a value +system.cpu1.iew.exec_nop 103983 # number of nop insts executed +system.cpu1.iew.exec_refs 50722611 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7090027 # Number of branches executed +system.cpu1.iew.exec_stores 7307162 # Number of stores executed +system.cpu1.iew.exec_rate 0.213729 # Inst execution rate +system.cpu1.iew.wb_sent 86641966 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54489882 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30361493 # num instructions producing a value +system.cpu1.iew.wb_consumers 54263873 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.133139 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.559242 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.133207 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.559516 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13692554 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 920627 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 322274 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111568344 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.442227 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.413238 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13678793 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 920061 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 321962 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111532269 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.442230 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.412276 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94375668 84.59% 84.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8446118 7.57% 92.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2197127 1.97% 94.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1290727 1.16% 95.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1277171 1.14% 96.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 591366 0.53% 96.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1009730 0.91% 97.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 541366 0.49% 98.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1839071 1.65% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94330377 84.58% 84.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8440609 7.57% 92.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2214130 1.99% 94.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1297536 1.16% 95.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1275593 1.14% 96.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 591609 0.53% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 995873 0.89% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 566603 0.51% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1819939 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111568344 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38958201 # Number of instructions committed -system.cpu1.commit.committedOps 49338577 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111532269 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38948804 # Number of instructions committed +system.cpu1.commit.committedOps 49322865 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17027012 # Number of memory references committed -system.cpu1.commit.loads 10000155 # Number of loads committed -system.cpu1.commit.membars 202531 # Number of memory barriers committed -system.cpu1.commit.branches 6139960 # Number of branches committed +system.cpu1.commit.refs 17019717 # Number of memory references committed +system.cpu1.commit.loads 9995942 # Number of loads committed +system.cpu1.commit.membars 202353 # Number of memory barriers committed +system.cpu1.commit.branches 6138218 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43727423 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556605 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1839071 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43713249 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556359 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1819939 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 171645222 # The number of ROB reads -system.cpu1.rob.rob_writes 128401309 # The number of ROB writes -system.cpu1.timesIdled 1423775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295253416 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4776625618 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38888562 # Number of Instructions Simulated -system.cpu1.committedOps 49268938 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38888562 # Number of Instructions Simulated -system.cpu1.cpi 10.517855 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.517855 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.095076 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.095076 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391481129 # number of integer regfile reads -system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18962770 # number of misc regfile reads -system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes -system.cpu1.icache.replacements 614989 # number of replacements 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(read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7122851 # number of overall hits -system.cpu1.icache.overall_hits::total 7122851 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 661583 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 661583 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 661583 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 661583 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 661583 # number of overall misses -system.cpu1.icache.overall_misses::total 661583 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8883357995 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8883357995 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8883357995 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8883357995 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8883357995 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8883357995 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7784434 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7784434 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7784434 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7784434 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7784434 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7784434 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084988 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084988 # miss rate for ReadReq accesses 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cycles access was blocked +system.cpu1.rob.rob_reads 171599349 # The number of ROB reads +system.cpu1.rob.rob_writes 128350222 # The number of ROB writes +system.cpu1.timesIdled 1423694 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295273987 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4796667155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38879165 # Number of Instructions Simulated +system.cpu1.committedOps 49253226 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38879165 # Number of Instructions Simulated +system.cpu1.cpi 10.521341 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.521341 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.095045 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.095045 # IPC: Total IPC of All Threads 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per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974210 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974210 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7119619 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7119619 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7119619 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7119619 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7119619 # number of overall hits +system.cpu1.icache.overall_hits::total 7119619 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661683 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661683 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661683 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661683 # number of demand (read+write) misses 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13386.929233 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13386.929233 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13386.929233 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2804 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 188 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.489011 # average number of cycles each access was blocked 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-system.cpu1.icache.overall_mshr_miss_latency::total 7269169496 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079072 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.079072 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.079072 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11809.552853 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46618 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46618 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46618 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46618 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46618 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46618 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615065 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 615065 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 615065 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 615065 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 615065 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 615065 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7253593996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7253593996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7253593996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7253593996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7253593996 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7253593996 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2902500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2902500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2902500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2902500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079044 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.079044 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.079044 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11793.215345 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363437 # number of replacements -system.cpu1.dcache.tagsinuse 485.666262 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13086846 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363802 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.972441 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70623957000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 485.666262 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.948567 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.948567 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8551806 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8551806 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4291461 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4291461 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103521 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 103521 # 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LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10942 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10942 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1967160 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1967160 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1967160 # number of overall misses -system.cpu1.dcache.overall_misses::total 1967160 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6026246000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6026246000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64613580018 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 64613580018 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131651000 # number of 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LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 104307 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100808 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100808 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12846778 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12846778 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12846778 # number of overall hits +system.cpu1.dcache.overall_hits::total 12846778 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 401782 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 401782 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1563319 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1563319 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14178 # number of LoadLockedReq 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# miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.132671 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14995.710360 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14995.710360 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40964.872491 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 40964.872491 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9248.448300 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9248.448300 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5367.158841 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5367.158841 # average StoreCondReq miss latency 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32495.934004 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7054.207436 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7054.207436 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3384.144111 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3384.144111 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327455 # number of writebacks +system.cpu1.dcache.writebacks::total 327455 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170587 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170587 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400204 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1400204 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1432 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1432 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570791 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1570791 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570791 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1570791 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231195 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231195 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163115 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163115 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10902 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10902 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394310 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394310 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394310 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394310 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2860496500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2860496500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5258978708 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5258978708 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89750500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89750500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36721500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36721500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8119475208 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8119475208 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8119475208 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8119475208 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169298302500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169298302500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27190030960 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27190030960 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196488333460 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196488333460 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025809 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025809 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097590 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097590 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026621 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026621 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12372.657281 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12372.657281 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32240.926389 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32240.926389 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7041.463989 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7041.463989 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3368.326912 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3368.326912 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1847,18 +1821,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1082174693399 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1162989936366 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1162989936366 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43757 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43794 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53969 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53929 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 842d69c20..94ce5b470 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing +mem_ranges=0:134217727 memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,12 +65,12 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -96,7 +96,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -118,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -155,6 +155,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -171,21 +172,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -474,21 +470,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -497,6 +488,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -517,25 +525,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus @@ -566,30 +569,25 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache -addr_ranges=0:268435455 +addr_ranges=0:134217727 assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.membus] type=CoherentBus @@ -601,7 +599,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side +slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -731,11 +729,12 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=41667 +clock=1000 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 +pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index affb69ad6..3ee89fc27 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -11,8 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index e4320499c..f7bd2d44c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 21:11:31 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 01:42:51 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2523500318000 because m5_exit instruction encountered +Exiting @ tick 2523517846500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 0468c1634..b454be827 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523500 # Number of seconds simulated -sim_ticks 2523500318000 # Number of ticks simulated -final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523518 # Number of seconds simulated +sim_ticks 2523517846500 # Number of ticks simulated +final_tick 2523517846500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76318 # Simulator instruction rate (inst/s) -host_op_rate 98167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3178196363 # Simulator tick rate (ticks/s) -host_mem_usage 441472 # Number of bytes of host memory used -host_seconds 794.00 # Real time elapsed on the host -sim_insts 60596849 # Number of instructions simulated -sim_ops 77944928 # Number of ops (including micro ops) simulated +host_inst_rate 24932 # Simulator instruction rate (inst/s) +host_op_rate 32070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1038273503 # Simulator tick rate (ticks/s) +host_mem_usage 403456 # Number of bytes of host memory used +host_seconds 2430.49 # Real time elapsed on the host +sim_insts 60597240 # Number of instructions simulated +sim_ops 77945362 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 798272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799176 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096842 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813129 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1040 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51290337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499139 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1040 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096860 # Total number of read requests seen -system.physmem.writeReqs 813144 # Total number of write requests seen -system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966199040 # Total number of bytes read from memory -system.physmem.bytesWritten 52041216 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 316333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53984661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096842 # Total number of read requests seen +system.physmem.writeReqs 813129 # Total number of write requests seen +system.physmem.cpureqs 218393 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966197888 # Total number of bytes read from memory +system.physmem.bytesWritten 52040256 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129432080 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799176 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 355 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943949 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943429 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943294 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943633 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankRdReqs::13 943617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943223 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50104 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51125 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51177 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523499110500 # Total gap between requests +system.physmem.numWrRetry 1183132 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523516727500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154616 # Categorize read packet sizes +system.physmem.readPktSize::6 154598 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1907897 # categorize write packet sizes +system.physmem.writePktSize::2 1937150 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59126 # categorize write packet sizes +system.physmem.writePktSize::6 59111 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,30 +117,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1042834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 938516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 972890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2730387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2738053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5375105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 57584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 37998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 64788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -154,59 +154,59 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3875 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31479 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests -system.physmem.totBusLat 60386104000 # Total cycles spent in databus access -system.physmem.totBankLat 210282128000 # Total cycles spent in bank access -system.physmem.avgQLat 3116.78 # Average queueing delay per request -system.physmem.avgBankLat 13929.17 # Average bank access latency per request +system.physmem.totQLat 328143428340 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 404872878340 # Sum of mem lat for all requests +system.physmem.totBusLat 60385948000 # Total cycles spent in databus access +system.physmem.totBankLat 16343502000 # Total cycles spent in bank access +system.physmem.avgQLat 21736.41 # Average queueing delay per request +system.physmem.avgBankLat 1082.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgMemAccLat 26819.01 # Average memory access latency system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 11.37 # Average write queue length over time -system.physmem.readRowHits 15049962 # Number of row buffer hits during reads -system.physmem.writeRowHits 784769 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes -system.physmem.avgGap 158610.84 # Average gap between requests +system.physmem.avgRdQLen 0.16 # Average read queue length over time +system.physmem.avgWrQLen 11.85 # Average write queue length over time +system.physmem.readRowHits 15052691 # Number of row buffer hits during reads +system.physmem.writeRowHits 784814 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.52 # Row buffer hit rate for writes +system.physmem.avgGap 158612.28 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51279526 # DTB read hits -system.cpu.dtb.read_misses 73667 # DTB read misses -system.cpu.dtb.write_hits 11753863 # DTB write hits -system.cpu.dtb.write_misses 17234 # DTB write misses +system.cpu.dtb.read_hits 51295505 # DTB read hits +system.cpu.dtb.read_misses 73548 # DTB read misses +system.cpu.dtb.write_hits 11769416 # DTB write hits +system.cpu.dtb.write_misses 17308 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4224 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4227 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2384 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 485 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51353193 # DTB read accesses -system.cpu.dtb.write_accesses 11771097 # DTB write accesses +system.cpu.dtb.perms_faults 1341 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51369053 # DTB read accesses +system.cpu.dtb.write_accesses 11786724 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63033389 # DTB hits -system.cpu.dtb.misses 90901 # DTB misses -system.cpu.dtb.accesses 63124290 # DTB accesses -system.cpu.itb.inst_hits 11603865 # ITB inst hits -system.cpu.itb.inst_misses 11359 # ITB inst misses +system.cpu.dtb.hits 63064921 # DTB hits +system.cpu.dtb.misses 90856 # DTB misses +system.cpu.dtb.accesses 63155777 # DTB accesses +system.cpu.itb.inst_hits 11599470 # ITB inst hits +system.cpu.itb.inst_misses 11387 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -256,122 +256,122 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2573 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2571 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2925 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11615224 # ITB inst accesses -system.cpu.itb.hits 11603865 # DTB hits -system.cpu.itb.misses 11359 # DTB misses -system.cpu.itb.accesses 11615224 # DTB accesses -system.cpu.numCycles 470951029 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11610857 # ITB inst accesses +system.cpu.itb.hits 11599470 # DTB hits +system.cpu.itb.misses 11387 # DTB misses +system.cpu.itb.accesses 11610857 # DTB accesses +system.cpu.numCycles 470965317 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits +system.cpu.BPredUnit.lookups 14487364 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11552940 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711872 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9478925 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7718754 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413170 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72913 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29863213 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90950612 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14487364 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9131924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20302505 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4756883 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122119 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96718680 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94285 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205383 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11595815 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 694954 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5716 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150585846 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.753226 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.110122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130298669 86.53% 86.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1345087 0.89% 87.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1687300 1.12% 88.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2309882 1.53% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2120076 1.41% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1117365 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2592055 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 766865 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8348547 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150585846 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030761 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.193115 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31645642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96356331 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18440866 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1036174 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106833 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1972079 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172496 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107972230 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569848 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106833 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33398103 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36860235 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53381295 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17668341 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6171039 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103073979 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21323 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016179 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4134721 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29043 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106845782 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 470577676 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 470486821 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90855 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 28114572 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 880520 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786795 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12341610 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19847152 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13390380 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1964070 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2407797 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95636460 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2047932 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123412976 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 169796 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19147761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47762380 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503425 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150585846 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.531798 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106411056 70.66% 70.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13811108 9.17% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7031286 4.67% 84.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5838601 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442775 8.26% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2756258 1.83% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1722165 1.14% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 442663 0.29% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 129934 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150585846 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60097 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available @@ -399,545 +399,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367175 94.63% 95.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 414340 4.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57952199 46.96% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93294 0.08% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52612072 42.63% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12389576 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued -system.cpu.iq.rate 0.261997 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123412976 # Type of FU issued +system.cpu.iq.rate 0.262043 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8841615 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071643 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406490722 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116848589 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85936823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22982 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12524 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131878765 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12160 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623393 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4131120 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30077 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1591861 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107803 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 700236 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106833 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27952249 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 439003 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97906020 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205363 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19847152 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13390380 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1460347 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 117327 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3551 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30077 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 353051 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272581 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625632 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121337067 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51981447 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075909 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220747 # number of nop insts executed -system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed -system.cpu.iew.exec_branches 11527542 # Number of branches executed -system.cpu.iew.exec_stores 12265452 # Number of stores executed -system.cpu.iew.exec_rate 0.257499 # Inst execution rate -system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47162688 # num instructions producing a value -system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value +system.cpu.iew.exec_nop 221628 # number of nop insts executed +system.cpu.iew.exec_refs 64262784 # number of memory reference insts executed +system.cpu.iew.exec_branches 11537560 # Number of branches executed +system.cpu.iew.exec_stores 12281337 # Number of stores executed +system.cpu.iew.exec_rate 0.257635 # Inst execution rate +system.cpu.iew.wb_sent 120375089 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85947111 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47183541 # num instructions producing a value +system.cpu.iew.wb_consumers 88082196 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182491 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535676 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18905107 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544507 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541940 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147479013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529538 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516870 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119767946 81.21% 81.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13521242 9.17% 90.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3932347 2.67% 93.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2139837 1.45% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947041 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 981141 0.67% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1580635 1.07% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 757975 0.51% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2850849 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747230 # Number of instructions committed -system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147479013 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747621 # Number of instructions committed +system.cpu.commit.committedOps 78095743 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514399 # Number of memory references committed -system.cpu.commit.loads 15715935 # Number of loads committed -system.cpu.commit.membars 413101 # Number of memory barriers committed -system.cpu.commit.branches 10023041 # Number of branches committed +system.cpu.commit.refs 27514551 # Number of memory references committed +system.cpu.commit.loads 15716032 # Number of loads committed +system.cpu.commit.membars 413105 # Number of memory barriers committed +system.cpu.commit.branches 10023101 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. -system.cpu.commit.function_calls 995976 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69134175 # Number of committed integer instructions. +system.cpu.commit.function_calls 995982 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2850849 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239806361 # The number of ROB reads -system.cpu.rob.rob_writes 197293644 # The number of ROB writes -system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60596849 # Number of Instructions Simulated -system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated -system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 549353817 # number of integer regfile reads -system.cpu.int_regfile_writes 87979071 # number of integer regfile writes -system.cpu.fp_regfile_reads 8318 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads -system.cpu.misc_regfile_writes 912865 # number of misc regfile writes -system.cpu.icache.replacements 980837 # number of replacements -system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use -system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor +system.cpu.rob.rob_reads 239713879 # The number of ROB reads +system.cpu.rob.rob_writes 197204165 # The number of ROB writes +system.cpu.timesIdled 1775890 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320379471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575982354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60597240 # Number of Instructions Simulated +system.cpu.committedOps 77945362 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60597240 # Number of Instructions Simulated +system.cpu.cpi 7.772059 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.772059 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128666 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128666 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549724990 # number of integer regfile reads +system.cpu.int_regfile_writes 88045459 # number of integer regfile writes +system.cpu.fp_regfile_reads 8276 # number of floating regfile reads +system.cpu.fp_regfile_writes 2926 # number of floating regfile writes +system.cpu.misc_regfile_reads 30431218 # number of misc regfile reads +system.cpu.misc_regfile_writes 912900 # number of misc regfile writes +system.cpu.icache.replacements 981280 # number of replacements +system.cpu.icache.tagsinuse 511.007424 # Cycle average of tags in use +system.cpu.icache.total_refs 10533801 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981792 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.729157 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6666221000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.007424 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits -system.cpu.icache.overall_hits::total 10539450 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses -system.cpu.icache.overall_misses::total 1060605 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091431 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091431 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13163.622169 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 10533801 # 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miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091576 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091576 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091576 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091576 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091576 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13153.450730 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13153.450730 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13153.450730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13153.450730 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80057 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 80057 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 80057 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 80057 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 80057 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 80057 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981831 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981831 # 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number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084602 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.084602 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.084602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11570.104057 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11570.104057 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084672 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.084672 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.084672 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.406015 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.406015 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks -system.cpu.dcache.writebacks::total 607749 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.091159 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.091159 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40229.876973 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42392.344595 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41265.161490 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37724.699758 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37724.699758 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1058,6 +896,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 643581 # number of replacements +system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use +system.cpu.dcache.total_refs 21676734 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644093 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.654665 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13816029 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13816029 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7289413 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7289413 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 282441 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 282441 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285740 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285740 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21105442 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21105442 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21105442 # number of overall hits +system.cpu.dcache.overall_hits::total 21105442 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731834 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731834 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2961255 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2961255 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13603 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13603 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3693089 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3693089 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3693089 # number of overall misses +system.cpu.dcache.overall_misses::total 3693089 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9564740000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9564740000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104026861731 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104026861731 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180604500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180604500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 244000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 244000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113591601731 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113591601731 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113591601731 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113591601731 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14547863 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14547863 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250668 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250668 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296044 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 296044 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285756 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285756 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24798531 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24798531 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24798531 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24798531 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050305 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050305 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288884 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288884 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045949 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045949 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148924 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148924 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148924 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148924 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.548559 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.548559 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35129.315689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35129.315689 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13276.813938 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13276.813938 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15250 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30757.883639 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30757.883639 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32046 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14482 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.377752 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 57.697211 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks +system.cpu.dcache.writebacks::total 607832 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345983 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345983 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712226 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2712226 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1428 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1428 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3058209 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3058209 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3058209 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3058209 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385851 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385851 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249029 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249029 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634880 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634880 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634880 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634880 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768256000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768256000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8126256417 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8126256417 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140756500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140756500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 212000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 212000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12894512417 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12894512417 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12894512417 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12894512417 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182401837500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182401837500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28201633550 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28201633550 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210603471050 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210603471050 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041126 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041126 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025602 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025602 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12357.765044 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12357.765044 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32631.767453 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32631.767453 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11561.108830 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11561.108830 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13250 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1072,16 +1072,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1148123553642 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1148123553642 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88023 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index fbde95c56..5ab2174c6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,16 +19,14 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 -panic_on_oops=true -panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -67,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index f0052292c..209411c61 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2012 16:28:23 -gem5 started Dec 11 2012 16:28:35 -gem5 executing on e103721-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 02:09:50 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Switching CPUs... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index ba425396c..41aab5e9e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,13 +4,25 @@ sim_seconds 2.401421 # Nu sim_ticks 2401421439000 # Number of ticks simulated final_tick 2401421439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170882 # Simulator instruction rate (inst/s) -host_op_rate 219406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6786575645 # Simulator tick rate (ticks/s) -host_mem_usage 393972 # Number of bytes of host memory used -host_seconds 353.85 # Real time elapsed on the host +host_inst_rate 75201 # Simulator instruction rate (inst/s) +host_op_rate 96555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2986582566 # Simulator tick rate (ticks/s) +host_mem_usage 393856 # Number of bytes of host memory used +host_seconds 804.07 # Real time elapsed on the host sim_insts 60466509 # Number of instructions simulated sim_ops 77636591 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory @@ -245,18 +257,6 @@ system.physmem.writeRowHits 499132 # Nu system.physmem.readRowHitRate 99.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.24 # Row buffer hit rate for writes system.physmem.avgGap 182850.04 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 63371 # number of replacements system.l2c.tagsinuse 50440.930838 # Cycle average of tags in use system.l2c.total_refs 1764263 # Total number of references to valid blocks. @@ -1541,7 +1541,7 @@ system.cpu2.int_regfile_reads 159046643 # nu system.cpu2.int_regfile_writes 30194860 # number of integer regfile writes system.cpu2.fp_regfile_reads 22317 # number of floating regfile reads system.cpu2.fp_regfile_writes 20822 # number of floating regfile writes -system.cpu2.misc_regfile_reads 41979427 # number of misc regfile reads +system.cpu2.misc_regfile_reads 9419199 # number of misc regfile reads system.cpu2.misc_regfile_writes 278833 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 340fc8f35..697dbdcbc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,16 +19,14 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 -panic_on_oops=true -panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -67,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 5acdb7217..0b3cf2832 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2012 16:28:23 -gem5 started Dec 11 2012 16:28:35 -gem5 executing on e103721-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 02:15:48 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Switching CPUs... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index b8d7124f2..317771e8c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,13 +4,25 @@ sim_seconds 2.540587 # Nu sim_ticks 2540587123500 # Number of ticks simulated final_tick 2540587123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67374 # Simulator instruction rate (inst/s) -host_op_rate 86663 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2824409714 # Simulator tick rate (ticks/s) -host_mem_usage 407052 # Number of bytes of host memory used -host_seconds 899.51 # Real time elapsed on the host +host_inst_rate 28859 # Simulator instruction rate (inst/s) +host_op_rate 37121 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1209803028 # Simulator tick rate (ticks/s) +host_mem_usage 406188 # Number of bytes of host memory used +host_seconds 2100.00 # Real time elapsed on the host sim_insts 60603607 # Number of instructions simulated sim_ops 77954043 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory @@ -224,18 +236,6 @@ system.physmem.writeRowHits 786076 # Nu system.physmem.readRowHitRate 99.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate 96.67 # Row buffer hit rate for writes system.physmem.avgGap 157735.86 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 64360 # number of replacements system.l2c.tagsinuse 51403.610979 # Cycle average of tags in use system.l2c.total_refs 1940230 # Total number of references to valid blocks. @@ -964,7 +964,7 @@ system.cpu0.int_regfile_reads 285784738 # nu system.cpu0.int_regfile_writes 46365180 # number of integer regfile writes system.cpu0.fp_regfile_reads 22828 # number of floating regfile reads system.cpu0.fp_regfile_writes 19904 # number of floating regfile writes -system.cpu0.misc_regfile_reads 64493667 # number of misc regfile reads +system.cpu0.misc_regfile_reads 16064067 # number of misc regfile reads system.cpu0.misc_regfile_writes 471303 # number of misc regfile writes system.cpu0.icache.replacements 986601 # number of replacements system.cpu0.icache.tagsinuse 511.585602 # Cycle average of tags in use @@ -1651,7 +1651,7 @@ system.cpu1.int_regfile_reads 264545362 # nu system.cpu1.int_regfile_writes 41743183 # number of integer regfile writes system.cpu1.fp_regfile_reads 22037 # number of floating regfile reads system.cpu1.fp_regfile_writes 19620 # number of floating regfile writes -system.cpu1.misc_regfile_reads 56567930 # number of misc regfile reads +system.cpu1.misc_regfile_reads 14602821 # number of misc regfile reads system.cpu1.misc_regfile_writes 442325 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index f7ba63a28..71b7ba73e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -16,9 +16,10 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing +mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 readfile=tests/halt.sh @@ -98,7 +99,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -158,6 +158,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -174,21 +175,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -213,21 +209,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port @@ -503,21 +494,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -530,7 +516,7 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 system=system -int_master=system.membus.slave[4] +int_master=system.membus.slave[3] int_slave=system.membus.master[3] pio=system.membus.master[2] @@ -556,21 +542,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port @@ -583,25 +564,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[3] +mem_side=system.membus.slave[2] [system.cpu.toL2Bus] type=CoherentBus @@ -997,25 +973,20 @@ assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[18] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[4] [system.membus] type=CoherentBus @@ -1027,7 +998,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1297,7 +1268,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-x86.img +image_file=/gem5/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1317,7 +1288,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/gem5/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 334789158..a2d9ec174 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:14:29 -gem5 started Oct 30 2012 18:26:17 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 23:13:25 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5132789913000 because m5_exit instruction encountered +Exiting @ tick 5136797077000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 87b53a299..48207d64f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.132790 # Number of seconds simulated -sim_ticks 5132789913000 # Number of ticks simulated -final_tick 5132789913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.136797 # Number of seconds simulated +sim_ticks 5136797077000 # Number of ticks simulated +final_tick 5136797077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148899 # Simulator instruction rate (inst/s) -host_op_rate 294332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1873578722 # Simulator tick rate (ticks/s) -host_mem_usage 406892 # Number of bytes of host memory used -host_seconds 2739.56 # Real time elapsed on the host -sim_insts 407917143 # Number of instructions simulated -sim_ops 806342485 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2491072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1075264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10835456 # Number of bytes read from this memory -system.physmem.bytes_read::total 14405312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1075264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1075264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9578880 # Number of bytes written to this memory -system.physmem.bytes_written::total 9578880 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16801 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169304 # Number of read requests responded to by this memory -system.physmem.num_reads::total 225083 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149670 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149670 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 485325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 209489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2111027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2806527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 209489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 209489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1866213 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1866213 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1866213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 485325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 209489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2111027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4672740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 225083 # Total number of read requests seen -system.physmem.writeReqs 149670 # Total number of write requests seen -system.physmem.cpureqs 388719 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14405312 # Total number of bytes read from memory -system.physmem.bytesWritten 9578880 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14405312 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9578880 # bytesWritten derated as per pkt->getSize() +host_inst_rate 59794 # Simulator instruction rate (inst/s) +host_op_rate 118197 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 752889080 # Simulator tick rate (ticks/s) +host_mem_usage 765888 # Number of bytes of host memory used +host_seconds 6822.78 # Real time elapsed on the host +sim_insts 407963976 # Number of instructions simulated +sim_ops 806432115 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2490112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1077440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10840448 # Number of bytes read from this memory +system.physmem.bytes_read::total 14411520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1077440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1077440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9595008 # Number of bytes written to this memory +system.physmem.bytes_written::total 9595008 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169382 # Number of read requests responded to by this memory +system.physmem.num_reads::total 225180 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149922 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149922 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 484760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2110352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2805546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1867897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1867897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1867897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 484760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 209749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2110352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4673443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 225180 # Total number of read requests seen +system.physmem.writeReqs 149922 # Total number of write requests seen +system.physmem.cpureqs 389082 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14411520 # Total number of bytes read from memory +system.physmem.bytesWritten 9595008 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14411520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9595008 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4102 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14948 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 15106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14545 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13582 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 14874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14098 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 14962 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14549 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 14901 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 10390 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 10526 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 9845 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8546 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9654 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 10118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9236 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 10295 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9932 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8008 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 10206 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 4150 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13684 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12992 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 15044 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13538 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13271 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14556 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13867 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 14842 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12817 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15188 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8767 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 10396 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8323 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 10488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 10117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8482 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9956 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8780 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 9930 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 10179 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8298 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9881 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8122 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 10268 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 49 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132789860500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136797025000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 225083 # Categorize read packet sizes +system.physmem.readPktSize::6 225180 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 149719 # categorize write packet sizes +system.physmem.writePktSize::6 149922 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -114,33 +114,33 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4102 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4150 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 176543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 176541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -150,47 +150,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 841 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 56 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3269589754 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7518085754 # Sum of mem lat for all requests -system.physmem.totBusLat 900032000 # Total cycles spent in databus access -system.physmem.totBankLat 3348464000 # Total cycles spent in bank access -system.physmem.avgQLat 14530.99 # Average queueing delay per request -system.physmem.avgBankLat 14881.53 # Average bank access latency per request +system.physmem.totQLat 3390959114 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7646017114 # Sum of mem lat for all requests +system.physmem.totBusLat 900420000 # Total cycles spent in databus access +system.physmem.totBankLat 3354638000 # Total cycles spent in bank access +system.physmem.avgQLat 15063.90 # Average queueing delay per request +system.physmem.avgBankLat 14902.55 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33412.53 # Average memory access latency +system.physmem.avgMemAccLat 33966.45 # Average memory access latency system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s @@ -198,45 +198,45 @@ system.physmem.avgConsumedWrBW 1.87 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.37 # Average write queue length over time -system.physmem.readRowHits 198566 # Number of row buffer hits during reads -system.physmem.writeRowHits 87960 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.77 # Row buffer hit rate for writes -system.physmem.avgGap 13696461.03 # Average gap between requests -system.iocache.replacements 47576 # number of replacements -system.iocache.tagsinuse 0.103964 # Cycle average of tags in use +system.physmem.avgWrQLen 11.93 # Average write queue length over time +system.physmem.readRowHits 198524 # Number of row buffer hits during reads +system.physmem.writeRowHits 88099 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes +system.physmem.avgGap 13694400.52 # Average gap between requests +system.iocache.replacements 47577 # number of replacements +system.iocache.tagsinuse 0.116411 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991828572000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.103964 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses -system.iocache.ReadReq_misses::total 911 # number of ReadReq misses +system.iocache.warmup_cycle 4991829125000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.116411 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007276 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007276 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses -system.iocache.demand_misses::total 47631 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses -system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146267932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 146267932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8962382160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 8962382160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9108650092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9108650092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9108650092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9108650092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses +system.iocache.demand_misses::total 47632 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses +system.iocache.overall_misses::total 47632 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146446932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 146446932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9011912160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9011912160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 9158359092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9158359092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 9158359092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9158359092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160557.554336 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160557.554336 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191831.809932 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 191831.809932 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191233.652285 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191233.652285 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 51554 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160577.776316 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160577.776316 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192891.955479 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 192891.955479 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192273.242610 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 192273.242610 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 57584 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7256 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7533 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.105017 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.644232 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98865990 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 98865990 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6530591975 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 6530591975 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6629457965 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6629457965 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98991992 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 98991992 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6580127962 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 6580127962 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6679119954 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6679119954 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,18 +287,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108524.687157 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108524.687157 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139781.506314 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 139781.506314 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108543.850877 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108543.850877 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140841.780009 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 140841.780009 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -308,141 +308,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 447650408 # number of cpu cycles simulated +system.cpu.numCycles 447871414 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86252473 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86252473 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1112360 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81440812 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79250759 # Number of BTB hits +system.cpu.BPredUnit.lookups 86248524 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86248524 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1109719 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81324372 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79248318 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27455337 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426133339 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86252473 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79250759 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163637491 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4749598 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 117040 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 62764723 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36355 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 51011 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 275 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9043493 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 487667 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3497 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257661797 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.265027 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27555812 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426098303 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86248524 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79248318 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163629889 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4731856 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 116400 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62921622 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 35870 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 52533 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 368 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9034264 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 488269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3183 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257896503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.261731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418044 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94448905 36.66% 36.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1567012 0.61% 37.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71922195 27.91% 65.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 935544 0.36% 65.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1602565 0.62% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2433530 0.94% 67.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1078893 0.42% 67.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1381790 0.54% 68.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82291363 31.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94692515 36.72% 36.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1566812 0.61% 37.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71928839 27.89% 65.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 936780 0.36% 65.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1600320 0.62% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2427387 0.94% 67.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1078261 0.42% 67.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1378215 0.53% 68.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82287374 31.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257661797 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192678 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.951933 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31146269 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60227421 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159444515 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3244027 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3599565 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838112106 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3599565 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33887749 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37302672 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10848429 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159621170 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12402212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834448767 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20383 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5810954 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4749020 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7935 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 996003699 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1811552283 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1811551779 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964308271 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31695421 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 457655 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 465271 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28736743 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17096853 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10140380 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1243307 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 975146 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828306292 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1248163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823283697 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 148415 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22289625 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33892420 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 195525 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257661797 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.195211 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.383294 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257896503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192574 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.951385 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31239529 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60388203 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159435692 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3249070 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3584009 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838053376 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 983 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3584009 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33976924 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37367105 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10941861 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159620502 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12406102 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834408692 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19434 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5810292 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4754441 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7847 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 995994396 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1811420133 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1811419405 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 728 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964426992 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31567397 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 458567 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 466421 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28739056 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17094362 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10134243 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1234841 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 965780 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 828292865 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1249354 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823298492 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 149694 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22192286 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33736795 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 196434 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257896503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.192360 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.384089 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71201357 27.63% 27.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15459797 6.00% 33.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10286150 3.99% 37.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7472850 2.90% 40.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75924697 29.47% 69.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3857138 1.50% 71.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72522119 28.15% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 785654 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152035 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71417814 27.69% 27.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15473003 6.00% 33.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10302554 3.99% 37.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7467952 2.90% 40.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75909427 29.43% 70.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3864522 1.50% 71.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72522780 28.12% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 788081 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 150370 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257661797 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257896503 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 364358 34.12% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 552545 51.74% 85.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150975 14.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 363959 34.09% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 552647 51.76% 85.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 151055 14.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 312887 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795710532 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 310624 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795733525 96.65% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -471,246 +471,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17869782 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9390496 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17867181 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9387162 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823283697 # Type of FU issued -system.cpu.iq.rate 1.839122 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1067878 # FU busy when requested +system.cpu.iq.FU_type_0::total 823298492 # Type of FU issued +system.cpu.iq.rate 1.838247 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1067661 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905576298 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851854038 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818789401 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 824038596 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1642479 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 1905840686 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851744345 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818819585 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 303 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 346 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 824055392 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 137 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1644579 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3121524 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22243 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11430 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1726583 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3112367 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 23963 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11499 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1716857 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932632 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11779 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932401 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11954 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3599565 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26096083 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2112224 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829554455 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 302739 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17096853 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10140380 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 717341 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1614771 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11695 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11430 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 654771 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 594016 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1248787 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821389011 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17449263 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1894685 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3584009 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26166561 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2112396 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829542219 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 307602 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17094362 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10134243 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 718774 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1614614 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11947 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11499 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 653687 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 591965 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1245652 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821416518 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17449825 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1881973 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26607287 # number of memory reference insts executed -system.cpu.iew.exec_branches 83217289 # Number of branches executed -system.cpu.iew.exec_stores 9158024 # Number of stores executed -system.cpu.iew.exec_rate 1.834889 # Inst execution rate -system.cpu.iew.wb_sent 820925784 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818789455 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639951171 # num instructions producing a value -system.cpu.iew.wb_consumers 1045809475 # num instructions consuming a value +system.cpu.iew.exec_refs 26604955 # number of memory reference insts executed +system.cpu.iew.exec_branches 83223788 # Number of branches executed +system.cpu.iew.exec_stores 9155130 # Number of stores executed +system.cpu.iew.exec_rate 1.834045 # Inst execution rate +system.cpu.iew.wb_sent 820955265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818819659 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639977790 # num instructions producing a value +system.cpu.iew.wb_consumers 1045837145 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.829082 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back +system.cpu.iew.wb_rate 1.828247 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611929 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23105687 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052636 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1116569 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254077625 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.173607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.854352 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 23003299 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052918 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1114308 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254312494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.171028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.854625 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82352974 32.41% 32.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11796837 4.64% 37.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3872314 1.52% 38.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74949594 29.50% 68.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2433419 0.96% 69.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1479159 0.58% 69.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 902635 0.36% 69.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70918587 27.91% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5372106 2.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82565112 32.47% 32.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11801317 4.64% 37.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3875007 1.52% 38.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74957575 29.47% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2434316 0.96% 69.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1480794 0.58% 69.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 899910 0.35% 70.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70920339 27.89% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5378124 2.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254077625 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407917143 # Number of instructions committed -system.cpu.commit.committedOps 806342485 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254312494 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407963976 # Number of instructions committed +system.cpu.commit.committedOps 806432115 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22389123 # Number of memory references committed -system.cpu.commit.loads 13975326 # Number of loads committed -system.cpu.commit.membars 473463 # Number of memory barriers committed -system.cpu.commit.branches 82187715 # Number of branches committed +system.cpu.commit.refs 22399378 # Number of memory references committed +system.cpu.commit.loads 13981992 # Number of loads committed +system.cpu.commit.membars 473513 # Number of memory barriers committed +system.cpu.commit.branches 82199908 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735283087 # Number of committed integer instructions. +system.cpu.commit.int_insts 735371295 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5372106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5378124 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078075497 # The number of ROB reads -system.cpu.rob.rob_writes 1662514782 # The number of ROB writes -system.cpu.timesIdled 1218897 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 189988611 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9817926834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407917143 # Number of Instructions Simulated -system.cpu.committedOps 806342485 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407917143 # Number of Instructions Simulated -system.cpu.cpi 1.097405 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.097405 # CPI: Total CPI of All Threads -system.cpu.ipc 0.911240 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.911240 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1506960736 # number of integer regfile reads -system.cpu.int_regfile_writes 976968921 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.misc_regfile_reads 264713842 # number of misc regfile reads -system.cpu.misc_regfile_writes 402218 # number of misc regfile writes -system.cpu.icache.replacements 1046081 # number of replacements -system.cpu.icache.tagsinuse 510.992308 # Cycle average of tags in use -system.cpu.icache.total_refs 7932749 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1046593 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.579593 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1078291467 # The number of ROB reads +system.cpu.rob.rob_writes 1662473587 # The number of ROB writes +system.cpu.timesIdled 1221266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189974911 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9825720160 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407963976 # Number of Instructions Simulated +system.cpu.committedOps 806432115 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407963976 # Number of Instructions Simulated +system.cpu.cpi 1.097821 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.097821 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910895 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910895 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1507038080 # number of integer regfile reads +system.cpu.int_regfile_writes 977032757 # number of integer regfile writes +system.cpu.fp_regfile_reads 74 # number of floating regfile reads +system.cpu.misc_regfile_reads 264726295 # number of misc regfile reads +system.cpu.misc_regfile_writes 402502 # number of misc regfile writes +system.cpu.icache.replacements 1052817 # number of replacements +system.cpu.icache.tagsinuse 510.984184 # Cycle average of tags in use +system.cpu.icache.total_refs 7916649 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1053329 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.515837 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 55992087000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.992308 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998032 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998032 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7932749 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7932749 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7932749 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7932749 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7932749 # number of overall hits -system.cpu.icache.overall_hits::total 7932749 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1110744 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1110744 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1110744 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1110744 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1110744 # number of overall misses -system.cpu.icache.overall_misses::total 1110744 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15035266490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15035266490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15035266490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15035266490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15035266490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15035266490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9043493 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9043493 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9043493 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9043493 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9043493 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9043493 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122822 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122822 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122822 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122822 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122822 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122822 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13536.212206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13536.212206 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13536.212206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13536.212206 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5934 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.984184 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998016 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998016 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7916649 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7916649 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7916649 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7916649 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7916649 # number of overall hits +system.cpu.icache.overall_hits::total 7916649 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1117614 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1117614 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1117614 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1117614 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1117614 # number of overall misses +system.cpu.icache.overall_misses::total 1117614 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15123913488 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15123913488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15123913488 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15123913488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15123913488 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15123913488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9034263 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9034263 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9034263 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9034263 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9034263 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9034263 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123708 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123708 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123708 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123708 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123708 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123708 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13532.322866 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13532.322866 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13532.322866 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13532.322866 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13532.322866 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13532.322866 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6872 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12388903990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12388903990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12388903990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12388903990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116002 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12467027488 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12467027488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116867 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116867 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116867 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.010608 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.010608 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.010608 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.010608 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.010608 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.010608 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9937 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.006130 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 26086 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9951 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.621445 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5106893785000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006130 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375383 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375383 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26219 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26219 # number of ReadReq hits -system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits -system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26222 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26222 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26222 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26222 # 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number of cycles access was blocked @@ -719,78 +719,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10817 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10817 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10817 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10817 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10817 # 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number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 91089500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 91089500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 91089500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 91089500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.273683 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.273683 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.273668 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.273668 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.273668 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.273668 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9065.435908 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9065.435908 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9065.435908 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 113923 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.921985 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 130116 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 113938 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.141990 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100448688500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.921985 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.807624 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.807624 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130138 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 130138 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130138 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 130138 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130138 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 130138 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 114896 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 114896 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 114896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 114896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 114896 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 114896 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1427497500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1427497500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1427497500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1427497500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1427497500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1427497500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245034 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 245034 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245034 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 245034 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245034 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 245034 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.468898 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.468898 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.468898 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.468898 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468898 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.468898 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.257589 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.257589 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.257589 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 111590 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 11.995325 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 130038 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 111605 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.165163 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100439779500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.995325 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749708 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.749708 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130049 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 130049 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130049 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 130049 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130049 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 130049 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 112651 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 112651 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 112651 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 112651 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 112651 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 112651 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1400311500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1400311500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1400311500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1400311500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1400311500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1400311500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 242700 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 242700 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 242700 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 242700 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 242700 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 242700 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.464157 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.464157 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.464157 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.464157 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.464157 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.464157 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12430.528801 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12430.528801 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12430.528801 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12430.528801 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,146 +799,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35555 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35555 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 114896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 114896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 114896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 114896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 114896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 114896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1197705500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1197705500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1197705500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.468898 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.468898 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.468898 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10424.257589 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35078 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35078 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 112651 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 112651 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 112651 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 112651 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 112651 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 112651 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1175009500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1175009500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1175009500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.464157 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.464157 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.464157 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10430.528801 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10430.528801 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10430.528801 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1657882 # number of replacements -system.cpu.dcache.tagsinuse 511.998105 # Cycle average of tags in use -system.cpu.dcache.total_refs 19102953 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1658394 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.518947 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27815000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998105 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11010989 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11010989 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8086819 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8086819 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19097808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19097808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19097808 # number of overall hits -system.cpu.dcache.overall_hits::total 19097808 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2233987 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2233987 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317747 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317747 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2551734 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2551734 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2551734 # number of overall misses -system.cpu.dcache.overall_misses::total 2551734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31818004500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31818004500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9564256493 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9564256493 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41382260993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41382260993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41382260993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41382260993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13244976 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13244976 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8404566 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8404566 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21649542 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21649542 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21649542 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21649542 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168667 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.168667 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037806 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037806 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117865 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117865 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117865 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117865 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14242.699040 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14242.699040 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30100.225944 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30100.225944 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16217.309874 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16217.309874 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 396326 # number of cycles access was blocked +system.cpu.dcache.replacements 1661569 # number of replacements +system.cpu.dcache.tagsinuse 511.994847 # Cycle average of tags in use +system.cpu.dcache.total_refs 19098471 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1662081 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.490698 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994847 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11004011 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11004011 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8089317 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8089317 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19093328 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19093328 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19093328 # number of overall hits +system.cpu.dcache.overall_hits::total 19093328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2239016 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2239016 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318822 # 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average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16262.755301 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16262.755301 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16262.755301 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 404649 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42512 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42429 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.322685 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.537085 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12612.557591 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29939.641189 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29939.641189 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1562908 # number of writebacks +system.cpu.dcache.writebacks::total 1562908 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864676 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 864676 # 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