diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:49 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:49 -0400 |
commit | f821c5472b5e524053846bd57b83c81238be159f (patch) | |
tree | 39f89e2f5574b7006a917323e3cde40d02885497 /tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini | |
parent | 3b927489371d61ef8b4d0ca9d7a2ca6a5c85f38b (diff) | |
download | gem5-f821c5472b5e524053846bd57b83c81238be159f.tar.xz |
tests: Prune 00.gzip from the regressions
This patch prunes the 00.gzip regressions with the main motivation
being that it adds little (or no) coverage and requires a substantial
amount of run time.
A complete regression run, including compilation from a clean repo, is
almost 20% faster(!).
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini')
-rw-r--r-- | tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini | 249 |
1 files changed, 0 insertions, 249 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini deleted file mode 100644 index 695f11b1b..000000000 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ /dev/null @@ -1,249 +0,0 @@ -[root] -type=Root -children=system -full_system=false -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -boot_osflags=a -clock=1000 -init_param=0 -kernel= -load_addr_mask=1099511627775 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.cpu] -type=InOrderCPU -children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -activity=0 -branchPred=system.cpu.branchPred -cachePorts=2 -checker=Null -clock=500 -cpu_id=0 -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchBuffSize=4 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -profile=0 -progress_interval=0 -stageTracing=false -stageWidth=4 -switched_out=false -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=262144 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=2 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -size=131072 -system=system -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.interrupts] -type=AlphaInterrupts - -[system.cpu.isa] -type=AlphaISA - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=500 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -size=2097152 -system=system -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.toL2Bus] -type=CoherentBus -block_size=64 -clock=500 -header_cycles=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=openmap -banks_per_rank=8 -channels=1 -clock=1000 -conf_table_reported=false -in_addr_map=true -lines_per_rowbuffer=32 -mem_sched_policy=frfcfs -null=false -page_policy=open -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 -zero=false -port=system.membus.master[0] - |