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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
commit | 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch) | |
tree | 64b85031cb791a21af6059778384d358d992b817 /tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | |
parent | dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff) | |
download | gem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz |
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt')
-rw-r--r-- | tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 759350e06..393ed8f87 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133779 # Nu sim_ticks 133778696500 # Number of ticks simulated final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 208111 # Simulator instruction rate (inst/s) -host_op_rate 208111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49227708 # Simulator tick rate (ticks/s) -host_mem_usage 215496 # Number of bytes of host memory used -host_seconds 2717.55 # Real time elapsed on the host +host_inst_rate 160169 # Simulator instruction rate (inst/s) +host_op_rate 160169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37887208 # Simulator tick rate (ticks/s) +host_mem_usage 273648 # Number of bytes of host memory used +host_seconds 3530.97 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory @@ -192,6 +192,15 @@ system.physmem.writeRowHits 53 # Nu system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes system.physmem.avgGap 4852854.06 # Average gap between requests +system.cpu.branchPred.lookups 76440222 # Number of BP lookups +system.cpu.branchPred.condPredicted 70864810 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2706098 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43060392 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41933015 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.381870 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1604413 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 267557394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 76440222 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 70864810 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2706098 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 43060392 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41933015 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1604413 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered |