diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/00.gzip/ref/alpha | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha')
12 files changed, 831 insertions, 563 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 6c1c0e974..b932d7fd7 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 30b31a527..26d645fed 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:21 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index b5662ac02..1a8f04561 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.274500 # Nu sim_ticks 274500333500 # Number of ticks simulated final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113367 # Simulator instruction rate (inst/s) -host_tick_rate 51705325 # Simulator tick rate (ticks/s) -host_mem_usage 207980 # Number of bytes of host memory used -host_seconds 5308.94 # Real time elapsed on the host +host_inst_rate 160535 # Simulator instruction rate (inst/s) +host_op_rate 160535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73218214 # Simulator tick rate (ticks/s) +host_mem_usage 209892 # Number of bytes of host memory used +host_seconds 3749.07 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5894016 # Number of bytes read from this memory system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory system.physmem.bytes_written 3798080 # Number of bytes written to this memory @@ -69,9 +71,10 @@ system.cpu.comNops 36304520 # Nu system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed system.cpu.comInts 349039879 # Number of Integer instructions committed system.cpu.comFloats 24 # Number of Floating Point instructions committed -system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads @@ -125,26 +128,39 @@ system.cpu.icache.total_refs 27985205 # To system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 728.259897 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.355596 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 27985205 # number of ReadReq hits -system.cpu.icache.demand_hits 27985205 # number of demand (read+write) hits -system.cpu.icache.overall_hits 27985205 # number of overall hits -system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses -system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 56646500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 56646500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 56646500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 27986224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 27986224 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 27986224 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55590.284593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55590.284593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55590.284593 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 728.259897 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355596 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355596 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27985205 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27985205 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27985205 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27985205 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27985205 # number of overall hits +system.cpu.icache.overall_hits::total 27985205 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1019 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1019 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1019 # number of overall misses +system.cpu.icache.overall_misses::total 1019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56646500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56646500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56646500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56646500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56646500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56646500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27986224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27986224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27986224 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27986224 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27986224 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27986224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55590.284593 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 855 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 855 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 855 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45774000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45774000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45774000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45774000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45774000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45774000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45774000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45774000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45774000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.842105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use @@ -181,32 +200,49 @@ system.cpu.dcache.total_refs 152394244 # To system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.126386 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999543 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114120509 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38273735 # number of WriteReq hits -system.cpu.dcache.demand_hits 152394244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 152394244 # number of overall hits -system.cpu.dcache.ReadReq_misses 393533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1177586 # number of WriteReq misses -system.cpu.dcache.demand_misses 1571119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1571119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 8150453500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25245531000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 33395984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 33395984500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.029849 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 21256.177603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 21256.177603 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.126386 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38273735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38273735 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152394244 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152394244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152394244 # number of overall hits +system.cpu.dcache.overall_hits::total 152394244 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1177586 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1177586 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1571119 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1571119 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1571119 # number of overall misses +system.cpu.dcache.overall_misses::total 1571119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150453500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8150453500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25245531000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25245531000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33395984500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33395984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33395984500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33395984500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029849 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20710.978495 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21438.375626 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked @@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408188 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 192301 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 923423 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1115724 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1115724 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3562138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5466740000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9028878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9028878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 408188 # number of writebacks +system.cpu.dcache.writebacks::total 408188 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923423 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 923423 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115724 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115724 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115724 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115724 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466740000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466740000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028878000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9028878000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028878000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9028878000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.647849 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21508.795537 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73797 # number of replacements system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use @@ -248,36 +292,72 @@ system.cpu.l2cache.total_refs 445688 # To system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364156 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92094 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16056.957351 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 28.224139 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1609.913702 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.490019 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000861 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.049131 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.540011 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 170051 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 170051 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4764594000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4809363000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44769000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4764594000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4809363000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201215 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202070 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 408188 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 408188 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254180 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254180 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154879 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236348 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200351 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200351 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.403509 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52308.689514 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52175.547233 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked @@ -286,30 +366,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59345 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59345 # number of writebacks +system.cpu.l2cache.writebacks::total 59345 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60075 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653580500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3687925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653580500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3687925500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154879 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.882685 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.910529 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index cc9b0c683..d5e06addc 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index ad1c408b1..e473c70fd 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:26 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 8681db468..6a8942beb 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.144450 # Nu sim_ticks 144450185500 # Number of ticks simulated final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205040 # Simulator instruction rate (inst/s) -host_tick_rate 52370107 # Simulator tick rate (ticks/s) -host_mem_usage 208620 # Number of bytes of host memory used -host_seconds 2758.26 # Real time elapsed on the host +host_inst_rate 270959 # Simulator instruction rate (inst/s) +host_op_rate 270959 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69206896 # Simulator tick rate (ticks/s) +host_mem_usage 211048 # Number of bytes of host memory used +host_seconds 2087.22 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated +sim_ops 565552443 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5936768 # Number of bytes read from this memory system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory system.physmem.bytes_written 3797120 # Number of bytes written to this memory @@ -272,6 +274,7 @@ system.cpu.iew.wb_rate 2.107953 # in system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions +system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted @@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle -system.cpu.commit.count 601856963 # Number of instructions committed +system.cpu.commit.committedInsts 601856963 # Number of instructions committed +system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed system.cpu.commit.loads 114514042 # Number of loads committed @@ -308,6 +312,7 @@ system.cpu.rob.rob_writes 1385724156 # Th system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated +system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads @@ -325,26 +330,39 @@ system.cpu.icache.total_refs 70951127 # To system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 75160.092161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 801.236568 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.391229 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 70951127 # number of ReadReq hits -system.cpu.icache.demand_hits 70951127 # number of demand (read+write) hits -system.cpu.icache.overall_hits 70951127 # number of overall hits -system.cpu.icache.ReadReq_misses 1272 # number of ReadReq misses -system.cpu.icache.demand_misses 1272 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 45919500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 45919500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 45919500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 70952399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 70952399 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 70952399 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36100.235849 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36100.235849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36100.235849 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 801.236568 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.391229 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.391229 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 70951127 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70951127 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70951127 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70951127 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70951127 # number of overall hits +system.cpu.icache.overall_hits::total 70951127 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1272 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1272 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1272 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1272 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1272 # number of overall misses +system.cpu.icache.overall_misses::total 1272 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45919500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45919500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45919500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45919500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45919500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45919500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 70952399 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 70952399 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 70952399 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 70952399 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 70952399 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 70952399 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000018 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000018 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36100.235849 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 944 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 944 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 944 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33676000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35673.728814 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 944 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 944 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 944 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33676000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33676000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33676000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33676000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33676000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33676000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35673.728814 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 470690 # number of replacements system.cpu.dcache.tagsinuse 4093.940031 # Cycle average of tags in use @@ -381,34 +402,53 @@ system.cpu.dcache.total_refs 151212527 # To system.cpu.dcache.sampled_refs 474786 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 318.485648 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4093.940031 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 113064898 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38147626 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 151212524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 151212524 # number of overall hits -system.cpu.dcache.ReadReq_misses 732041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1303695 # number of WriteReq misses -system.cpu.dcache.demand_misses 2035736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2035736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11783533000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 19632740219 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 31416273219 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 31416273219 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 113796939 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153248260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153248260 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.033046 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013284 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013284 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16096.821080 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15059.304683 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15432.390653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15432.390653 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4093.940031 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999497 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999497 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 113064898 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113064898 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38147626 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38147626 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 151212524 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151212524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151212524 # number of overall hits +system.cpu.dcache.overall_hits::total 151212524 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 732041 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 732041 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1303695 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1303695 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2035736 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2035736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2035736 # number of overall misses +system.cpu.dcache.overall_misses::total 2035736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11783533000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11783533000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19632740219 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19632740219 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31416273219 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31416273219 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31416273219 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31416273219 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 113796939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 113796939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 153248260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 153248260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 153248260 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 153248260 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006433 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033046 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013284 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013284 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16096.821080 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15059.304683 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 804496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked @@ -417,32 +457,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 6935.310345 system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423044 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 513277 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1047673 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1560950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1560950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256022 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 474786 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 474786 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1640072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3027658494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4667730994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4667730994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001922 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003098 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003098 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.994478 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.774715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 423044 # 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number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 256022 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 474786 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 474786 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 474786 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 474786 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1640072500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1640072500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3027658494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3027658494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4667730994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4667730994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4667730994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4667730994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001922 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7496.994478 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11825.774715 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74463 # number of replacements system.cpu.l2cache.tagsinuse 17661.712037 # Cycle average of tags in use @@ -450,36 +498,72 @@ system.cpu.l2cache.total_refs 478021 # To system.cpu.l2cache.sampled_refs 90363 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 5.290008 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1743.919943 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15917.792095 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053220 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485772 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186750 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423044 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 196218 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 382968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 382968 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32958 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92762 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92762 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1133680000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2065878500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3199558500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3199558500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219708 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423044 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256022 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 475730 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 475730 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.150008 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.233589 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194989 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194989 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34397.718308 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34544.152565 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34492.125008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34492.125008 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15917.792095 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 36.116254 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1707.803688 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.485772 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001102 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.538993 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 186750 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 186750 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 423044 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 423044 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 196218 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 196218 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 475730 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 944 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 474786 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 475730 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.146340 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.233589 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.193388 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.193388 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34369.173729 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.560005 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34544.152565 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked @@ -488,30 +572,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59330 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32958 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92762 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92762 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1022345000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877543500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2899888500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2899888500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150008 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233589 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194989 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194989 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.631046 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31394.948498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59330 # number of writebacks +system.cpu.l2cache.writebacks::total 59330 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32014 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32958 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 59804 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 59804 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91818 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91818 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92762 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29409000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 992936000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1022345000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1877543500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1877543500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29409000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2870479500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2899888500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29409000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2870479500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2899888500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.146340 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.233589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31153.601695 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.680640 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31394.948498 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 282141772..8be56150d 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout index 1dc402141..b88c15875 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:30 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index ad4f39b85..97a3f2734 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.300931 # Nu sim_ticks 300930958000 # Number of ticks simulated final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4527143 # Simulator instruction rate (inst/s) -host_tick_rate 2263589972 # Simulator tick rate (ticks/s) -host_mem_usage 198960 # Number of bytes of host memory used -host_seconds 132.94 # Real time elapsed on the host +host_inst_rate 5630967 # Simulator instruction rate (inst/s) +host_op_rate 5630966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2815505896 # Simulator tick rate (ticks/s) +host_mem_usage 200704 # Number of bytes of host memory used +host_seconds 106.88 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2782990928 # Number of bytes read from this memory system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory system.physmem.bytes_written 152669504 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 601861917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.committedInsts 601856964 # Number of instructions committed +system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses system.cpu.num_func_calls 2395217 # number of times a function call or return occured diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 0bc5277c7..83c88fa93 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index 36bd68fb7..dfe9fcdd2 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:31 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 4d7850adf..4b454bbcf 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.765623 # Nu sim_ticks 765623032000 # Number of ticks simulated final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2199350 # Simulator instruction rate (inst/s) -host_tick_rate 2797795440 # Simulator tick rate (ticks/s) -host_mem_usage 207676 # Number of bytes of host memory used -host_seconds 273.65 # Real time elapsed on the host +host_inst_rate 2698243 # Simulator instruction rate (inst/s) +host_op_rate 2698243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3432438217 # Simulator tick rate (ticks/s) +host_mem_usage 209572 # Number of bytes of host memory used +host_seconds 223.06 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5889984 # Number of bytes read from this memory system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory system.physmem.bytes_written 3797824 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 1531246064 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.committedInsts 601856964 # Number of instructions committed +system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses system.cpu.num_func_calls 2395217 # number of times a function call or return occured @@ -79,26 +82,39 @@ system.cpu.icache.total_refs 601861103 # To system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits -system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits -system.cpu.icache.overall_hits 601861103 # number of overall hits -system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.demand_misses 795 # number of demand (read+write) misses -system.cpu.icache.overall_misses 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 601861103 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 601861103 # number of overall hits +system.cpu.icache.overall_hits::total 601861103 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 795 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 795 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses +system.cpu.icache.overall_misses::total 795 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 601861898 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 795 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use @@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 153509968 # To system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 10207442000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits +system.cpu.dcache.overall_hits::total 153509968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses +system.cpu.dcache.overall_misses::total 455395 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408190 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8841257000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks +system.cpu.dcache.writebacks::total 408190 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73734 # number of replacements system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use @@ -199,36 +232,72 @@ system.cpu.l2cache.total_refs 445709 # To system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170065 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364159 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364159 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31962 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92031 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.543931 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3123588000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41340000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4744272000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4785612000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41340000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4744272000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4785612000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456190 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,30 +306,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59341 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks +system.cpu.l2cache.writebacks::total 59341 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91236 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92031 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1278480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2402760000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2402760000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |