diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
| commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
| tree | 81108e7ff1951b652258f53bd5615a617b734ce2 /tests/long/se/00.gzip/ref/alpha | |
| parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
| download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz | |
update stats for preceeding changes
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha')
6 files changed, 1031 insertions, 985 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 0e8616cf5..8c8aecb35 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 282b60660..5289b243e 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:09:56 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:21:21 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274137499500 because target called exit() +Exiting @ tick 269661304500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 01d17fd64..e8752c3e3 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269731 # Number of seconds simulated -sim_ticks 269730745500 # Number of ticks simulated -final_tick 269730745500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269661 # Number of seconds simulated +sim_ticks 269661304500 # Number of ticks simulated +final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168515 # Simulator instruction rate (inst/s) -host_op_rate 168515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75522303 # Simulator tick rate (ticks/s) -host_mem_usage 218132 # Number of bytes of host memory used -host_seconds 3571.54 # Real time elapsed on the host +host_inst_rate 125304 # Simulator instruction rate (inst/s) +host_op_rate 125304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56142087 # Simulator tick rate (ticks/s) +host_mem_usage 214336 # Number of bytes of host memory used +host_seconds 4803.19 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6039326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6238873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240595 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240595 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6039326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6479469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 74 # Tr system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269730693500 # Total gap between requests +system.physmem.totGap 269661252500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,9 +105,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 17613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 360576187 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1020404187 # Sum of mem lat for all requests +system.physmem.totQLat 364261179 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests system.physmem.totBusLat 105120000 # Total cycles spent in databus access -system.physmem.totBankLat 554708000 # Total cycles spent in bank access -system.physmem.avgQLat 13720.56 # Average queueing delay per request -system.physmem.avgBankLat 21107.61 # Average bank access latency per request +system.physmem.totBankLat 554778000 # Total cycles spent in bank access +system.physmem.avgQLat 13860.78 # Average queueing delay per request +system.physmem.avgBankLat 21110.27 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38828.17 # Average memory access latency +system.physmem.avgMemAccLat 38971.05 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -187,31 +187,31 @@ system.physmem.peakBW 16000.00 # Th system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 17405 # Number of row buffer hits during reads +system.physmem.readRowHits 17406 # Number of row buffer hits during reads system.physmem.writeRowHits 51 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes -system.physmem.avgGap 9877350.72 # Average gap between requests +system.physmem.avgGap 9874807.84 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517567 # DTB read hits +system.cpu.dtb.read_hits 114517568 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520198 # DTB read accesses -system.cpu.dtb.write_hits 39453373 # DTB write hits +system.cpu.dtb.read_accesses 114520199 # DTB read accesses +system.cpu.dtb.write_hits 39453362 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455675 # DTB write accesses -system.cpu.dtb.data_hits 153970940 # DTB hits +system.cpu.dtb.write_accesses 39455664 # DTB write accesses +system.cpu.dtb.data_hits 153970930 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153975873 # DTB accesses -system.cpu.itb.fetch_hits 25065868 # ITB hits +system.cpu.dtb.data_accesses 153975863 # DTB accesses +system.cpu.itb.fetch_hits 24997854 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25065890 # ITB accesses +system.cpu.itb.fetch_accesses 24997876 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539461492 # number of cpu cycles simulated +system.cpu.numCycles 539322610 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86297721 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81352852 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36357676 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52914836 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34319624 # Number of BTB hits +system.cpu.branch_predictor.lookups 86405274 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81476244 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36343014 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 44773910 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34660000 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.858226 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36896934 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49400787 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541636673 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 77.411153 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005491519 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 254989713 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155053642 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33759621 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2593068 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36352689 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26195221 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.119750 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334808 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 154928367 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535900413 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 295985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50743768 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488717724 # Number of cycles cpu stages are processed. -system.cpu.activity 90.593626 # Percentage of cycles cpu is active +system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed. +system.cpu.activity 90.582759 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -272,72 +272,72 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896328 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896328 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115663 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115663 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200698192 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338763300 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.796568 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228822575 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310638917 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.583149 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197865765 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341595727 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.321615 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 428073840 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111387652 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.647934 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192651610 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346809882 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.288163 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.083311 # Cycle average of tags in use -system.cpu.icache.total_refs 25064833 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use +system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29315.594152 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.083311 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355998 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355998 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25064833 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25064833 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25064833 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25064833 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25064833 # number of overall hits -system.cpu.icache.overall_hits::total 25064833 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1035 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1035 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1035 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1035 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1035 # number of overall misses -system.cpu.icache.overall_misses::total 1035 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52854000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52854000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52854000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52854000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52854000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52854000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25065868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25065868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25065868 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25065868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25065868 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25065868 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits +system.cpu.icache.overall_hits::total 24996820 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses +system.cpu.icache.overall_misses::total 1034 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51066.666667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51066.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51066.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51066.666667 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -346,158 +346,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 180 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 180 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 180 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 180 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 179 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 179 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43286500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43286500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43286500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43286500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43286500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43286500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50627.485380 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50627.485380 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.419858 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786041 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306341 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.419858 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665413 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665413 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786041 # number of overall hits -system.cpu.dcache.overall_hits::total 151786041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785908 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179322 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179322 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179322 # number of overall misses -system.cpu.dcache.overall_misses::total 2179322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991589500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5991589500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22875440000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22875440000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28867029500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28867029500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28867029500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28867029500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses 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-system.cpu.dcache.ReadReq_avg_miss_latency::total 15229.731275 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12808.856895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12808.856895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13245.876240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13245.876240 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 165761 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 544 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5600 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access 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of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723927 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723927 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645854500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645854500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3731128500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3731128500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6376983000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6376983000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6376983000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6376983000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13148.279101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13148.279101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14680.061614 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14680.061614 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22878.552216 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531848 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. 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+system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -522,17 +414,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses 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cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -557,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50274.078478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114589.454545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103697.543294 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53773.912228 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53773.912228 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 63202.707842 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 63202.707842 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency 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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 877062534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31666859 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1296316456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1327983315 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31666859 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1296316456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1327983315 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles 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ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37665388 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37665388 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151786016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151786016 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151786016 # number of overall hits +system.cpu.dcache.overall_hits::total 151786016 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1785933 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1785933 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2179347 # number of demand (read+write) misses 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+system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks +system.cpu.dcache.writebacks::total 436887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 5bc85930f..ba863cc04 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index ddf76222f..396a60755 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:10:10 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:21:56 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 135504709500 because target called exit() +Exiting @ tick 133778696500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 82eaca8c6..759350e06 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.135739 # Number of seconds simulated -sim_ticks 135738546500 # Number of ticks simulated -final_tick 135738546500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133779 # Number of seconds simulated +sim_ticks 133778696500 # Number of ticks simulated +final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149707 # Simulator instruction rate (inst/s) -host_op_rate 149707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35931284 # Simulator tick rate (ticks/s) -host_mem_usage 219152 # Number of bytes of host memory used -host_seconds 3777.73 # Real time elapsed on the host +host_inst_rate 208111 # Simulator instruction rate (inst/s) +host_op_rate 208111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49227708 # Simulator tick rate (ticks/s) +host_mem_usage 215496 # Number of bytes of host memory used +host_seconds 2717.55 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory -system.physmem.bytes_written::total 67072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26528 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 454049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12053761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12507810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 454049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 454049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 494126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 494126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 494126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 454049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12053761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13001937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26528 # Total number of read requests seen -system.physmem.writeReqs 1048 # Total number of write requests seen -system.physmem.cpureqs 27576 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697792 # Total number of bytes read from memory -system.physmem.bytesWritten 67072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697792 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636416 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67008 # Number of bytes written to this memory +system.physmem.bytes_written::total 67008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25569 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26520 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1047 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1047 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 454960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12232262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12687222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 454960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 500887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 500887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 500887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 454960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12232262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13188109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26520 # Total number of read requests seen +system.physmem.writeReqs 1047 # Total number of write requests seen +system.physmem.cpureqs 27567 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697280 # Total number of bytes read from memory +system.physmem.bytesWritten 67008 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697280 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67008 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1612 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1569 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1630 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1568 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1615 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1704 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis @@ -65,26 +65,26 @@ system.physmem.perBankWrReqs::2 55 # Tr system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 84 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 57 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 80 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 78 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 135738512500 # Total gap between requests +system.physmem.totGap 133778628000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26528 # Categorize read packet sizes +system.physmem.readPktSize::6 26520 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1048 # categorize write packet sizes +system.physmem.writePktSize::6 1047 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4903 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,7 +150,7 @@ system.physmem.wrQLenPdf::8 46 # Wh system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 656768415 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1272742415 # Sum of mem lat for all requests -system.physmem.totBusLat 106052000 # Total cycles spent in databus access -system.physmem.totBankLat 509922000 # Total cycles spent in bank access -system.physmem.avgQLat 24771.56 # Average queueing delay per request -system.physmem.avgBankLat 19232.90 # Average bank access latency per request +system.physmem.totQLat 650833420 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1266537420 # Sum of mem lat for all requests +system.physmem.totBusLat 106020000 # Total cycles spent in databus access +system.physmem.totBankLat 509684000 # Total cycles spent in bank access +system.physmem.avgQLat 24555.12 # Average queueing delay per request +system.physmem.avgBankLat 19229.73 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 48004.47 # Average memory access latency -system.physmem.avgRdBW 12.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.49 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.49 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 47784.85 # Average memory access latency +system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.03 # Average write queue length over time -system.physmem.readRowHits 18053 # Number of row buffer hits during reads -system.physmem.writeRowHits 56 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.34 # Row buffer hit rate for writes -system.physmem.avgGap 4922342.34 # Average gap between requests +system.physmem.avgWrQLen 10.37 # Average write queue length over time +system.physmem.readRowHits 18044 # Number of row buffer hits during reads +system.physmem.writeRowHits 53 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes +system.physmem.avgGap 4852854.06 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123922794 # DTB read hits -system.cpu.dtb.read_misses 28366 # DTB read misses +system.cpu.dtb.read_hits 122603551 # DTB read hits +system.cpu.dtb.read_misses 28565 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123951160 # DTB read accesses -system.cpu.dtb.write_hits 40833980 # DTB write hits -system.cpu.dtb.write_misses 25612 # DTB write misses +system.cpu.dtb.read_accesses 122632116 # DTB read accesses +system.cpu.dtb.write_hits 40753368 # DTB write hits +system.cpu.dtb.write_misses 25574 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40859592 # DTB write accesses -system.cpu.dtb.data_hits 164756774 # DTB hits -system.cpu.dtb.data_misses 53978 # DTB misses +system.cpu.dtb.write_accesses 40778942 # DTB write accesses +system.cpu.dtb.data_hits 163356919 # DTB hits +system.cpu.dtb.data_misses 54139 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164810752 # DTB accesses -system.cpu.itb.fetch_hits 66580671 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.dtb.data_accesses 163411058 # DTB accesses +system.cpu.itb.fetch_hits 65475592 # ITB hits +system.cpu.itb.fetch_misses 42 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66580711 # ITB accesses +system.cpu.itb.fetch_accesses 65475634 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 271477094 # number of cpu cycles simulated +system.cpu.numCycles 267557394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78553522 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72909571 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3050106 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42863354 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41672348 # Number of BTB hits +system.cpu.BPredUnit.lookups 76440222 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 70864810 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2706098 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 43060392 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41933015 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1629524 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 245 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68542455 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 711581178 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78553522 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43301872 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119313775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13045820 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73380337 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1305 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66580671 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 946763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 271202747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.623798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454049 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1604413 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43537428 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117782486 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11617306 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73490715 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1303 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65475592 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 928038 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267274328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.615488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444547 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151888972 56.01% 56.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10373570 3.83% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11841110 4.37% 64.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10622549 3.92% 68.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7004922 2.58% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2671761 0.99% 71.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3503178 1.29% 72.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3113300 1.15% 74.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70183385 25.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149491842 55.93% 55.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10342090 3.87% 59.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11847639 4.43% 64.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10563390 3.95% 68.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7011808 2.62% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2869024 1.07% 71.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3576964 1.34% 73.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3101400 1.16% 74.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68470171 25.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271202747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289356 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.621146 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 86023061 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57429003 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104152322 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13634796 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9963565 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3909126 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702760367 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4141 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9963565 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 94304341 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12784998 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1531 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104174044 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49974268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690768624 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 416 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38037873 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5669894 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527681051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 907529781 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 907526811 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2970 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267274328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285697 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.612721 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84240613 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57793701 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102635866 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13724657 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8879491 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3873839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 920 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691093913 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3105 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8879491 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92211740 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12790279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1241 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103054645 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50336932 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 680961604 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 408 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38688874 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5430085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520709674 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 896990234 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 896987596 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2638 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63826162 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 100 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112138467 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129142032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42466663 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14842304 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10368291 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626932339 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608621790 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 344229 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60678365 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33855512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271202747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.244158 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.828491 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 56854785 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 64 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 69 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112289485 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 126970724 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42377686 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14852387 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10147583 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621083354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604563100 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299815 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 54897951 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29938787 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267274328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.261957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823661 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55518105 20.47% 20.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55264401 20.38% 40.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53914091 19.88% 60.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 37013789 13.65% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31720099 11.70% 86.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23689667 8.74% 94.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10003906 3.69% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3493839 1.29% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 584850 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52499760 19.64% 19.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55875325 20.91% 40.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53442699 20.00% 60.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36269586 13.57% 74.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31423380 11.76% 85.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23799839 8.90% 94.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9996979 3.74% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3415050 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 551710 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271202747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267274328 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2803923 71.85% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 36 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 717323 18.38% 90.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 381401 9.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2734710 70.93% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 35 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 729519 18.92% 89.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 391400 10.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441148473 72.48% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7331 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126212456 20.74% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41253487 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439055623 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7072 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124323040 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41177317 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608621790 # Type of FU issued -system.cpu.iq.rate 2.241890 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3902683 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006412 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1492689315 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 687613743 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598990581 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2505 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1722 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612522503 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1970 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12211500 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604563100 # Type of FU issued +system.cpu.iq.rate 2.259564 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3855664 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006378 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480552206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 675984537 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596489873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3801 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2284 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1738 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608416848 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1916 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12282855 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14627990 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32965 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5519 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3015342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12456682 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35904 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5518 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2926365 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6777 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 53391 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6461 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 52889 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9963565 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1456092 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 187737 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670933978 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1716868 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129142032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42466663 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 140012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5519 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1345446 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2210203 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3555649 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602801961 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123951309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5819829 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8879491 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1456554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 192142 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 663913486 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1691538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 126970724 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42377686 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 144242 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7408 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5518 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1333964 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1804152 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3138116 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599464075 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122632263 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5099025 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 44001547 # number of nop insts executed -system.cpu.iew.exec_refs 164826908 # number of memory reference insts executed -system.cpu.iew.exec_branches 67037045 # Number of branches executed -system.cpu.iew.exec_stores 40875599 # Number of stores executed -system.cpu.iew.exec_rate 2.220452 # Inst execution rate -system.cpu.iew.wb_sent 600240253 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598992303 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417488059 # num instructions producing a value -system.cpu.iew.wb_consumers 532706701 # num instructions consuming a value +system.cpu.iew.exec_nop 42830076 # number of nop insts executed +system.cpu.iew.exec_refs 163429760 # number of memory reference insts executed +system.cpu.iew.exec_branches 66623337 # Number of branches executed +system.cpu.iew.exec_stores 40797497 # Number of stores executed +system.cpu.iew.exec_rate 2.240506 # Inst execution rate +system.cpu.iew.wb_sent 597426155 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596491611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415927297 # num instructions producing a value +system.cpu.iew.wb_consumers 530215795 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.206419 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.783711 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229397 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784449 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 68955725 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61932723 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3049050 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 261239182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.303854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.691353 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2705240 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258394837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.691172 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82351408 31.52% 31.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72672063 27.82% 59.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25867656 9.90% 69.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8932880 3.42% 72.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10297113 3.94% 76.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20861196 7.99% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6530231 2.50% 87.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3837950 1.47% 88.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29888685 11.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79550578 30.79% 30.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72525012 28.07% 58.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25515345 9.87% 68.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9289171 3.59% 72.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10288497 3.98% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21029047 8.14% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6874256 2.66% 87.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3694459 1.43% 88.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29628472 11.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 261239182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258394837 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,368 +475,368 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29888685 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29628472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 902098796 # The number of ROB reads -system.cpu.rob.rob_writes 1351611788 # The number of ROB writes -system.cpu.timesIdled 34221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 274347 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892491662 # The number of ROB reads +system.cpu.rob.rob_writes 1336472901 # The number of ROB writes +system.cpu.timesIdled 34286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 283066 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.480021 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.480021 # CPI: Total CPI of All Threads -system.cpu.ipc 2.083242 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.083242 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848885274 # number of integer regfile reads -system.cpu.int_regfile_writes 492863541 # number of integer regfile writes -system.cpu.fp_regfile_reads 396 # number of floating regfile reads -system.cpu.fp_regfile_writes 49 # number of floating regfile writes +system.cpu.cpi 0.473090 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473090 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113761 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113761 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 844970192 # number of integer regfile reads +system.cpu.int_regfile_writes 490533624 # number of integer regfile writes +system.cpu.fp_regfile_reads 397 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 43 # number of replacements -system.cpu.icache.tagsinuse 832.109405 # Cycle average of tags in use -system.cpu.icache.total_refs 66579220 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 984 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67661.808943 # Average number of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.tagsinuse 825.012562 # Cycle average of tags in use +system.cpu.icache.total_refs 65474211 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67848.923316 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 832.109405 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.406303 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.406303 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66579220 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66579220 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66579220 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66579220 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66579220 # number of overall hits -system.cpu.icache.overall_hits::total 66579220 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1449 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51513.457557 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51513.457557 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 825.012562 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.402838 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.402838 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65474211 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65474211 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65474211 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65474211 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65474211 # number of overall hits +system.cpu.icache.overall_hits::total 65474211 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses +system.cpu.icache.overall_misses::total 1381 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68875500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68875500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68875500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68875500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68875500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68875500 # 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miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.642288 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49873.642288 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49873.642288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49873.642288 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 73.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 465 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 465 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 465 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 465 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 465 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 984 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 984 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52037.823834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52037.823834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460800 # number of replacements -system.cpu.dcache.tagsinuse 4090.940281 # Cycle average of tags in use -system.cpu.dcache.total_refs 148282429 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464896 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 318.958281 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 305241000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.940281 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998765 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998765 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73359.302280 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72580.109351 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 1047 # number of writebacks +system.cpu.l2cache.writebacks::total 1047 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 951 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4308 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5259 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21261 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21261 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 951 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25569 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26520 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 951 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25569 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26520 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37144486 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39058.344900 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85735.098422 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77294.407682 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55726.736889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55726.736889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60782.703938 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60003.674321 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60782.703938 # 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109242892 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648409 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648409 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146891301 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146891301 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146891301 # number of overall hits +system.cpu.dcache.overall_hits::total 146891301 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1026587 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1026587 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802912 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802912 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2829499 # number of overall misses +system.cpu.dcache.overall_misses::total 2829499 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15441177000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15441177000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25867331616 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25867331616 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41310977656 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41310977656 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41310977656 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057692 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018716 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018716 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018716 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018716 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.004347 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.004347 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14366.481581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14366.481581 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 21 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14607.201684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14607.201684 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 279576 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17250 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.207304 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.250000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14599.230682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14599.230682 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 277266 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17305 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.022306 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 83.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445038 # number of writebacks -system.cpu.dcache.writebacks::total 445038 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 815637 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4051961986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4051961986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6752483486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6752483486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6752483486 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6752483486 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14524.718402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14524.718402 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 2364362 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2364362 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2364362 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2364362 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210561 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210561 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254576 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254576 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 465137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 465137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 465137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 465137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2703972000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2703972000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4046409990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4046409990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6750381990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6750381990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6750381990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6750381990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003107 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003107 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12841.751321 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12841.751321 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15894.703311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15894.703311 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1080 # number of replacements -system.cpu.l2cache.tagsinuse 22929.630995 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547178 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23523 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.261404 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21483.752454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 824.475298 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 621.403243 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655632 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025161 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018964 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699757 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 206090 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 206111 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 445038 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 445038 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233241 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 233241 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 439331 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 439352 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 439331 # number of overall hits -system.cpu.l2cache.overall_hits::total 439352 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4290 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5253 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21275 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21275 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25565 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26528 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25565 # number of overall misses -system.cpu.l2cache.overall_misses::total 26528 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 423158500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 474105000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1457229500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1457229500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50946500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1880388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1931334500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50946500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1880388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1931334500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211364 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 445038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 445038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 464896 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 465880 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 464896 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 465880 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978659 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020392 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024853 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083590 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083590 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.978659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054991 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.978659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054991 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056942 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52903.946002 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 98638.344988 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 90254.140491 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68494.923619 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68494.923619 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72803.622587 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72803.622587 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks -system.cpu.l2cache.writebacks::total 1049 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5253 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21275 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21275 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25565 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26528 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25565 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26528 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38838509 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 367821283 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 406659792 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1190995676 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1190995676 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38838509 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1558816959 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1597655468 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38838509 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1558816959 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1597655468 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024853 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083590 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083590 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056942 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40330.746625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85739.226807 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77414.770988 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55980.995347 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55980.995347 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |