diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/long/se/00.gzip/ref/alpha | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha')
3 files changed, 932 insertions, 942 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 56312634f..011acdd4e 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274137 # Number of seconds simulated -sim_ticks 274137453500 # Number of ticks simulated -final_tick 274137453500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.271545 # Number of seconds simulated +sim_ticks 271544682500 # Number of ticks simulated +final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134061 # Simulator instruction rate (inst/s) -host_op_rate 134061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61063086 # Simulator tick rate (ticks/s) -host_mem_usage 219148 # Number of bytes of host memory used -host_seconds 4489.41 # Real time elapsed on the host +host_inst_rate 105483 # Simulator instruction rate (inst/s) +host_op_rate 105483 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47591638 # Simulator tick rate (ticks/s) +host_mem_usage 219440 # Number of bytes of host memory used +host_seconds 5705.72 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,37 +23,37 @@ system.physmem.num_reads::cpu.data 25316 # Nu system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5910261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6106601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5910261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6314613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5966694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6164908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 209999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 209999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 209999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5966694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6374907 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114518787 # DTB read hits +system.cpu.dtb.read_hits 114517787 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114521418 # DTB read accesses -system.cpu.dtb.write_hits 39662426 # DTB write hits +system.cpu.dtb.read_accesses 114520418 # DTB read accesses +system.cpu.dtb.write_hits 39661840 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664728 # DTB write accesses -system.cpu.dtb.data_hits 154181213 # DTB hits +system.cpu.dtb.write_accesses 39664142 # DTB write accesses +system.cpu.dtb.data_hits 154179627 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154186146 # DTB accesses -system.cpu.itb.fetch_hits 25086764 # ITB hits +system.cpu.dtb.data_accesses 154184560 # DTB accesses +system.cpu.itb.fetch_hits 25070818 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25086786 # ITB accesses +system.cpu.itb.fetch_accesses 25070840 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 548274908 # number of cpu cycles simulated +system.cpu.numCycles 543089366 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81377487 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36366052 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52958494 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34331818 # Number of BTB hits +system.cpu.branch_predictor.lookups 86310005 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36354317 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52694904 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34317639 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541561072 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 65.125157 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36895090 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49414915 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541552617 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005415918 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1005407463 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255070175 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155050348 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36361065 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26186838 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.133148 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334459 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 255071199 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155051796 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2591546 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36349330 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26198577 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.114383 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 539843953 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538349706 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 672397 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59138093 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489136815 # Number of cycles cpu stages are processed. -system.cpu.activity 89.213788 # Percentage of cycles cpu is active +system.cpu.timesIdled 387700 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53984537 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489104829 # Number of cycles cpu stages are processed. +system.cpu.activity 90.059732 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.910972 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.902356 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.910972 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.902356 # CPI: Total CPI of All Threads +system.cpu.ipc 1.108210 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 209382923 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338891985 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.810595 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 237433150 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310841758 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.694507 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 206489347 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341785561 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.338355 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 436702871 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.349652 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201266007 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347008901 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.291042 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.108210 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 204234221 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338855145 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.393994 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 232262845 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310826521 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.233034 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 201309957 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341779409 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.932444 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 431519146 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111570220 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.543621 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 196111910 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346977456 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.889569 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.512382 # Cycle average of tags in use -system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.073717 # Cycle average of tags in use +system.cpu.icache.total_refs 25069794 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29321.396491 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.512382 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25085741 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25085741 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25085741 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25085741 # number of overall hits -system.cpu.icache.overall_hits::total 25085741 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses -system.cpu.icache.overall_misses::total 1021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 57700000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 57700000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 57700000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 57700000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 57700000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 57700000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25086762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25086762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25086762 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25086762 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25086762 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25086762 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.073717 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355993 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355993 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25069794 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25069794 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25069794 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25069794 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25069794 # number of overall hits +system.cpu.icache.overall_hits::total 25069794 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses +system.cpu.icache.overall_misses::total 1022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56347500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56347500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56347500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56347500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56347500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56347500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25070816 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25070816 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25070816 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25070816 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25070816 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25070816 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56513.222331 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56513.222331 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56513.222331 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56513.222331 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55134.540117 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55134.540117 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55134.540117 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46832500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46832500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46832500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46832500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46832500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46832500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46510500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46510500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46510500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54774.853801 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54774.853801 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54398.245614 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54398.245614 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.836594 # Cycle average of tags in use -system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.014631 # Cycle average of tags in use +system.cpu.dcache.total_refs 152406162 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.836594 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120497 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38285544 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38285544 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152406041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152406041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152406041 # number of overall hits -system.cpu.dcache.overall_hits::total 152406041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393545 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393545 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1165777 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1165777 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1559322 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses -system.cpu.dcache.overall_misses::total 1559322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7771987000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228329000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30228329000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38000316000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38000316000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38000316000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38000316000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.668062 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 268976000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.014631 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999515 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999515 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38285655 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38285655 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152406162 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152406162 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152406162 # number of overall hits +system.cpu.dcache.overall_hits::total 152406162 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1165666 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1165666 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1559201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1559201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1559201 # number of overall misses +system.cpu.dcache.overall_misses::total 1559201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5490501500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5490501500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16777875500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16777875500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22268377000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22268377000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22268377000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22268377000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363 system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029550 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029550 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.661525 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.661525 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25929.769587 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25929.769587 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24369.768399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24369.768399 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28216000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3564 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7916.947250 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13951.748891 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13951.748891 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14393.381552 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14393.381552 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21072500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2046602500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6660.082174 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9678.575313 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks system.cpu.dcache.writebacks::total 436902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192313 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192313 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911614 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911614 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1103927 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1103927 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1103927 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1103927 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911503 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911503 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1103806 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1103806 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1103806 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1103806 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820633500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7820633500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820633500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7820633500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395605000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395605000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3804662000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3804662000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6200267000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6200267000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6200267000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6200267000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,35 +318,35 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.729586 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.729586 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.083686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.083686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11904.692097 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11904.692097 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14969.377919 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14969.377919 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 917 # number of replacements -system.cpu.l2cache.tagsinuse 22837.818508 # Cycle average of tags in use -system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22852.343306 # Cycle average of tags in use +system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21635.297320 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 719.415407 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 483.105781 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.696955 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21651.877416 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 719.990292 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 480.475597 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660763 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021972 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014663 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697398 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197099 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197113 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232980 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232980 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232992 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232992 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits @@ -364,24 +364,24 @@ system.cpu.l2cache.demand_misses::total 26157 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 260244000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215397500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1215397500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1430257500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1475641500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1430257500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1475641500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 215882000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 261384000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1220308500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1220308500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45502000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1436190500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1481692500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45502000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1436190500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1481692500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254176 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254176 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses @@ -389,32 +389,32 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020475 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024550 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083387 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083387 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.485437 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.972183 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57340.889791 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57340.889791 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56414.783805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56414.783805 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3419500 # number of cycles access was blocked +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54104.637337 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52398.543689 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52687.764564 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57572.584450 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57572.584450 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 108500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 115 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29734.782609 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 13562.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -431,39 +431,39 @@ system.cpu.l2cache.demand_mshr_misses::total 26157 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954509500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954509500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119870500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1155016500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119870500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1155016500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35251500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165390500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200642000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 961154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 961154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1126544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1161796000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1126544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1161796000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083387 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083387 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45032.529723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45032.529723 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41916.171225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.325243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40443.862125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45346.008681 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45346.008681 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index f78f2bef4..73ec0cee6 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.135471 # Number of seconds simulated -sim_ticks 135471331500 # Number of ticks simulated -final_tick 135471331500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133202 # Number of seconds simulated +sim_ticks 133202081500 # Number of ticks simulated +final_tick 133202081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 255662 # Simulator instruction rate (inst/s) -host_op_rate 255662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61240707 # Simulator tick rate (ticks/s) -host_mem_usage 220172 # Number of bytes of host memory used -host_seconds 2212.11 # Real time elapsed on the host +host_inst_rate 189557 # Simulator instruction rate (inst/s) +host_op_rate 189557 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44645563 # Simulator tick rate (ticks/s) +host_mem_usage 220464 # Number of bytes of host memory used +host_seconds 2983.55 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory -system.physmem.bytes_read::total 1689280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 58944 # Number of bytes written to this memory -system.physmem.bytes_written::total 58944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26395 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 921 # Number of write requests responded to by this memory -system.physmem.num_writes::total 921 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 456835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12012815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12469649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 456835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 456835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 435103 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 435103 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 435103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 456835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12012815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12904752 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627520 # Number of bytes read from this memory +system.physmem.bytes_read::total 1688832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58752 # Number of bytes written to this memory +system.physmem.bytes_written::total 58752 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25430 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 918 # Number of write requests responded to by this memory +system.physmem.num_writes::total 918 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 460293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12218428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12678721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 460293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 460293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 441074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 441074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 441074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 460293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12218428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13119795 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123970603 # DTB read hits -system.cpu.dtb.read_misses 28720 # DTB read misses +system.cpu.dtb.read_hits 123824653 # DTB read hits +system.cpu.dtb.read_misses 18111 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123999323 # DTB read accesses -system.cpu.dtb.write_hits 40821734 # DTB write hits -system.cpu.dtb.write_misses 42993 # DTB write misses +system.cpu.dtb.read_accesses 123842764 # DTB read accesses +system.cpu.dtb.write_hits 40832181 # DTB write hits +system.cpu.dtb.write_misses 27219 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40864727 # DTB write accesses -system.cpu.dtb.data_hits 164792337 # DTB hits -system.cpu.dtb.data_misses 71713 # DTB misses +system.cpu.dtb.write_accesses 40859400 # DTB write accesses +system.cpu.dtb.data_hits 164656834 # DTB hits +system.cpu.dtb.data_misses 45330 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164864050 # DTB accesses -system.cpu.itb.fetch_hits 66629589 # ITB hits +system.cpu.dtb.data_accesses 164702164 # DTB accesses +system.cpu.itb.fetch_hits 66456282 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66629628 # ITB accesses +system.cpu.itb.fetch_accesses 66456321 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +67,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 270942664 # number of cpu cycles simulated +system.cpu.numCycles 266404164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78540801 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72908130 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3045250 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42784442 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41679238 # Number of BTB hits +system.cpu.BPredUnit.lookups 78470433 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72835844 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3045377 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42694984 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41620121 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1625962 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68608304 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 712216936 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78540801 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43305200 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119376688 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13084394 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 72934666 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1626012 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68396808 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710651464 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78470433 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43246133 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119157795 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12900055 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 68967877 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66629589 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 948387 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 270906593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.629013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.455853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1025 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66456282 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 943162 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 266369518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.667916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.466169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151529905 55.93% 55.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10364245 3.83% 59.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11839822 4.37% 64.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10610225 3.92% 68.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6991463 2.58% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2667986 0.98% 71.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3540757 1.31% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3105472 1.15% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70256718 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 147211723 55.27% 55.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10361930 3.89% 59.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11839981 4.44% 63.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10604273 3.98% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6985851 2.62% 70.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2662888 1.00% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3489906 1.31% 72.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3104255 1.17% 73.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70108711 26.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270906593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289880 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.628663 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 86218522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56873885 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104030125 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13799230 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9984831 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3903379 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1089 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703205131 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9984831 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 94485896 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12289062 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1666 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104300720 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49844418 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 691143238 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5409 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37459217 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6250189 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527606706 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 907468723 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 907465803 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2920 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 266369518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.294554 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.667569 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85436450 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 53444664 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104479529 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13163939 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9844936 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3905187 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1152 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 701891597 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4998 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9844936 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93666462 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10915780 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 985 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104171147 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 47770208 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690014062 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37142293 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4412591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527194579 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906673497 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906670681 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2816 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63751817 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 122 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 110700400 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129196942 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42484118 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14760258 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9703253 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626892028 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 99 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608695355 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 350153 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60644934 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33797171 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 82 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270906593 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.246883 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.833563 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63339690 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 89 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 106261883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128976533 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42417035 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14777590 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9627827 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626339991 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608311695 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 332491 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60098493 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33347060 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 266369518 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.283714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.821089 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55377469 20.44% 20.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55325876 20.42% 40.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 54071762 19.96% 60.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36846414 13.60% 74.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30891550 11.40% 85.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23842623 8.80% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10560250 3.90% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3379294 1.25% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 611355 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 51762898 19.43% 19.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 53589578 20.12% 39.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53994858 20.27% 59.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 37661936 14.14% 73.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31638901 11.88% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23703533 8.90% 94.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10074612 3.78% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3319964 1.25% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 623238 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270906593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 266369518 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2755770 75.48% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 573872 15.72% 91.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 321392 8.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2702741 76.36% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 515259 14.56% 90.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 321532 9.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441149057 72.47% 72.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7297 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126283457 20.75% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41255500 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 440952184 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7450 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126098325 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41253693 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608695355 # Type of FU issued -system.cpu.iq.rate 2.246584 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3651064 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005998 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1492294648 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 687539732 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598944947 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3872 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2425 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1713 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612344476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1943 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12180058 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608311695 # Type of FU issued +system.cpu.iq.rate 2.283417 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3539537 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005819 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1486861080 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686441117 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598748300 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3856 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2343 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1699 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 611849296 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1936 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12174453 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14682900 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33847 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5158 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3032797 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14462491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33569 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4944 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2965714 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6745 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162513 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6773 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 155 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9984831 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 591994 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80208 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 671175480 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1733020 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129196942 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42484118 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 99 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8476 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 909 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5158 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342632 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2208039 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3550671 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602850413 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123999444 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5844942 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9844936 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 227072 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16439 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670244681 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1692417 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128976533 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42417035 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6445 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4188 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4944 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342659 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2208068 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3550727 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602499469 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123842867 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5812226 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 44283353 # number of nop insts executed -system.cpu.iew.exec_refs 164880697 # number of memory reference insts executed -system.cpu.iew.exec_branches 67045865 # Number of branches executed -system.cpu.iew.exec_stores 40881253 # Number of stores executed -system.cpu.iew.exec_rate 2.225011 # Inst execution rate -system.cpu.iew.wb_sent 600209978 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598946660 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417271834 # num instructions producing a value -system.cpu.iew.wb_consumers 532298467 # num instructions consuming a value +system.cpu.iew.exec_nop 43904609 # number of nop insts executed +system.cpu.iew.exec_refs 164718956 # number of memory reference insts executed +system.cpu.iew.exec_branches 66994757 # Number of branches executed +system.cpu.iew.exec_stores 40876089 # Number of stores executed +system.cpu.iew.exec_rate 2.261599 # Inst execution rate +system.cpu.iew.wb_sent 599990050 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598749999 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417673921 # num instructions producing a value +system.cpu.iew.wb_consumers 531386701 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.210603 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.783906 # average fanout of values written-back +system.cpu.iew.wb_rate 2.247525 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786007 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69202424 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68221188 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3044252 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 260921762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.306657 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.693748 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3044329 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 256524582 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.346196 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.706570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 81870366 31.38% 31.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72918515 27.95% 59.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26232772 10.05% 69.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8204750 3.14% 72.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10788682 4.13% 76.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20849092 7.99% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6203888 2.38% 87.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3594438 1.38% 88.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30259259 11.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77999684 30.41% 30.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72616675 28.31% 58.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26248532 10.23% 68.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7743107 3.02% 71.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10914414 4.25% 76.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20847110 8.13% 84.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6257952 2.44% 86.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3103879 1.21% 88.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30793229 12.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 260921762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 256524582 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30259259 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30793229 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 901657501 # The number of ROB reads -system.cpu.rob.rob_writes 1352126118 # The number of ROB writes -system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36071 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 895745115 # The number of ROB reads +system.cpu.rob.rob_writes 1350023504 # The number of ROB writes +system.cpu.timesIdled 796 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34646 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.479076 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.479076 # CPI: Total CPI of All Threads -system.cpu.ipc 2.087351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.087351 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848921354 # number of integer regfile reads -system.cpu.int_regfile_writes 492788777 # number of integer regfile writes -system.cpu.fp_regfile_reads 376 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cpi 0.471051 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.471051 # CPI: Total CPI of All Threads +system.cpu.ipc 2.122911 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.122911 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848545483 # number of integer regfile reads +system.cpu.int_regfile_writes 492673182 # number of integer regfile writes +system.cpu.fp_regfile_reads 367 # number of floating regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 46 # number of replacements -system.cpu.icache.tagsinuse 834.348638 # Cycle average of tags in use -system.cpu.icache.total_refs 66628172 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67301.183838 # Average number of references to valid blocks. +system.cpu.icache.replacements 44 # number of replacements +system.cpu.icache.tagsinuse 827.655289 # Cycle average of tags in use +system.cpu.icache.total_refs 66454892 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67880.379980 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 834.348638 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.407397 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.407397 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66628172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66628172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66628172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66628172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66628172 # number of overall hits -system.cpu.icache.overall_hits::total 66628172 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1417 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1417 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1417 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1417 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1417 # number of overall misses -system.cpu.icache.overall_misses::total 1417 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51973000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51973000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51973000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51973000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51973000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51973000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66629589 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66629589 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66629589 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66629589 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66629589 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66629589 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 827.655289 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404129 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404129 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66454892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66454892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66454892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66454892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66454892 # number of overall hits +system.cpu.icache.overall_hits::total 66454892 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1390 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1390 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1390 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66456282 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66456282 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66456282 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36678.193366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36678.193366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36678.193366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36678.193366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34673.741007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34673.741007 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34673.741007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34673.741007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # 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mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37526.262626 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37526.262626 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37526.262626 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37526.262626 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37526.262626 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37526.262626 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36228.294178 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36228.294178 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36228.294178 # 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number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1770625 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1770625 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2348384 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2348384 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2348384 # number of overall misses -system.cpu.dcache.overall_misses::total 2348384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8217146500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8217146500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 45283421033 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45283421033 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 321.888467 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 135777000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.413189 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999368 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999368 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 111075212 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111075212 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38533998 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38533998 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 43 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 43 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149609210 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7625818400 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7625818400 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10903574900 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10903574900 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10903574900 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10903574900 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111643340 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111643340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151111803 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151111803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151111803 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151111803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005174 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005174 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.044881 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.044881 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015541 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015541 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015541 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015541 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14222.446556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14222.446556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25574.823033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25574.823033 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22781.865118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22781.865118 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 260996 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 204500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 99 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2636.323232 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20450 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151094661 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151094661 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151094661 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151094661 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005089 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005089 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.023252 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.023252 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009831 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009831 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009831 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009831 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5769.397917 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5769.397917 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8313.122423 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8313.122423 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7340.245420 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7340.245420 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 483496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4740.156863 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18772.727273 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444797 # number of writebacks -system.cpu.dcache.writebacks::total 444797 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367652 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 367652 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1516116 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1516116 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14607.039661 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2751.940307 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2751.940307 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5386.637052 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5386.637052 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4194.661621 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 464786 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 465765 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 464786 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 465765 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978550 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020411 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024851 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083054 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083054 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.978550 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.054713 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.056655 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.978550 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.054713 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.056655 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35946.764092 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34657.152842 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34892.476190 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.172864 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.172864 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38951.132939 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38951.132939 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 100996 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10499.428571 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1246.864198 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 921 # number of writebacks -system.cpu.l2cache.writebacks::total 921 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 967 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4296 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5263 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 967 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25428 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26395 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 967 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25428 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26395 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 136100000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167740000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 754125496 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 754125496 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 890225496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 921865496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 890225496 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 921865496 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.976768 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020447 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024932 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083029 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083029 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976768 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054729 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056690 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976768 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054729 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056690 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32719.751810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31680.633147 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31871.556147 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35686.423244 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35686.423244 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32719.751810 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.654554 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34925.762303 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32719.751810 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.654554 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34925.762303 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 918 # number of writebacks +system.cpu.l2cache.writebacks::total 918 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4292 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5250 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21138 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21138 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25430 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26388 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31379500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135795500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167175000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778051996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778051996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31379500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913847496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 945226996 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31379500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913847496 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 945226996 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020411 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024851 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083054 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083054 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054713 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056655 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054713 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056655 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32755.219207 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31639.212488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31842.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.212508 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.212508 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 6b056dd7e..cd0e43aa8 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.764109 # Number of seconds simulated -sim_ticks 764109115000 # Number of ticks simulated -final_tick 764109115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.762398 # Number of seconds simulated +sim_ticks 762397656000 # Number of ticks simulated +final_tick 762397656000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2465110 # Simulator instruction rate (inst/s) -host_op_rate 2465110 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3129668646 # Simulator tick rate (ticks/s) -host_mem_usage 218984 # Number of bytes of host memory used -host_seconds 244.15 # Real time elapsed on the host +host_inst_rate 1514073 # Simulator instruction rate (inst/s) +host_op_rate 1514073 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1917939864 # Simulator tick rate (ticks/s) +host_mem_usage 219440 # Number of bytes of host memory used +host_seconds 397.51 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25315 # Nu system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory system.physmem.num_writes::total 883 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 65582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2120325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2185908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 65582 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 65582 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 73958 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 73958 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 73958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 65582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2120325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2259866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2125085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2190815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 74124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 74124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 74124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2125085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2264939 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1528218230 # number of cpu cycles simulated +system.cpu.numCycles 1524795312 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1528218230 # Number of busy cycles +system.cpu.num_busy_cycles 1524795312 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.286058 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.382950 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.286058 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328753 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328753 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.382950 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328800 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328800 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44165000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44165000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44165000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44165000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44165000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44165000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 43221000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 43221000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 43221000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 43221000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 43221000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 43221000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55553.459119 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55553.459119 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55553.459119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55553.459119 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54366.037736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54366.037736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54366.037736 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41780000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41780000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52553.459119 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52553.459119 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.128141 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.202421 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 590218000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.128141 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 563489000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.202421 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2991812000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2991812000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4452609000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4452609000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7444421000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7444421000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7444421000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7444421000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789140000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2789140000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4194225000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4194225000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6983365000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6983365000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6983365000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6983365000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14867.476346 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14867.476346 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17518.714368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17518.714368 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16347.173333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16347.173333 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13860.320426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13860.320426 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16502.106916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16502.106916 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15334.742367 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2388116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2388116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3690120000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3690120000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6078236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078236000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6078236000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11867.476346 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11867.476346 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14518.714368 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14518.714368 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 903 # number of replacements -system.cpu.l2cache.tagsinuse 22839.375690 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22842.908958 # Cycle average of tags in use system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21645.673483 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 668.235332 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 525.466875 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660574 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.020393 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21649.670438 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 668.334752 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 524.903769 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660696 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.020396 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016019 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697110 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits |