diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/long/se/00.gzip/ref/alpha | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha')
13 files changed, 265 insertions, 86 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 37ea66e58..c1fb80fc3 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 4bff58d47..b4ecd43cf 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:38:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:43:43 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 7e649e9a6..e5597cd29 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.274300 # Nu sim_ticks 274300226500 # Number of ticks simulated final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71153 # Simulator instruction rate (inst/s) -host_op_rate 71153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32428333 # Simulator tick rate (ticks/s) -host_mem_usage 214868 # Number of bytes of host memory used -host_seconds 8458.66 # Real time elapsed on the host +host_inst_rate 112537 # Simulator instruction rate (inst/s) +host_op_rate 112537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51289289 # Simulator tick rate (ticks/s) +host_mem_usage 215256 # Number of bytes of host memory used +host_seconds 5348.10 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5894080 # Number of bytes read from this memory -system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3798144 # Number of bytes written to this memory -system.physmem.num_reads 92095 # Number of read requests responded to by this memory -system.physmem.num_writes 59346 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 21487696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13846667 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35334364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory +system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory +system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -156,11 +169,17 @@ system.cpu.icache.demand_accesses::total 25020500 # nu system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,11 +207,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 45765000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use @@ -236,13 +261,21 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked @@ -278,13 +311,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73798 # number of replacements system.cpu.l2cache.tagsinuse 17696.811171 # Cycle average of tags in use @@ -346,18 +387,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 455395 system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.158457 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.236350 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52310.393829 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52174.395765 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52221.678701 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52221.678701 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked @@ -392,18 +441,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158457 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236350 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40008.338799 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40063.993941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index d7f68c19e..01ebbe1c7 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index 1f4384270..ef914e93c 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:45 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 0a8d681a5..aa861e979 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.134621 # Nu sim_ticks 134621123500 # Number of ticks simulated final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99995 # Simulator instruction rate (inst/s) -host_op_rate 99995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23802311 # Simulator tick rate (ticks/s) -host_mem_usage 215740 # Number of bytes of host memory used -host_seconds 5655.80 # Real time elapsed on the host +host_inst_rate 192359 # Simulator instruction rate (inst/s) +host_op_rate 192359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45788058 # Simulator tick rate (ticks/s) +host_mem_usage 216172 # Number of bytes of host memory used +host_seconds 2940.09 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5937600 # Number of bytes read from this memory -system.physmem.bytes_inst_read 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797952 # Number of bytes written to this memory -system.physmem.num_reads 92775 # Number of read requests responded to by this memory -system.physmem.num_writes 59343 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 44106005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 476359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 28212155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 72318160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 64128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5873472 # Number of bytes read from this memory +system.physmem.bytes_read::total 5937600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3797952 # Number of bytes written to this memory +system.physmem.bytes_written::total 3797952 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1002 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91773 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92775 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59343 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59343 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 476359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43629646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 44106005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 476359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 476359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 28212155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 28212155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 28212155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 476359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43629646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72318160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -358,11 +371,17 @@ system.cpu.icache.demand_accesses::total 66483943 # nu system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34946.440912 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34946.440912 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,11 +409,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 35750000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35678.642715 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 460743 # number of replacements system.cpu.dcache.tagsinuse 4093.783086 # Cycle average of tags in use @@ -446,15 +471,25 @@ system.cpu.dcache.demand_accesses::total 151114481 # nu system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006469 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032971 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015873 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013388 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013388 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16273.449094 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15091.410417 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15513.457453 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15513.457453 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked @@ -492,13 +527,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7699.484588 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11899.490005 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74480 # number of replacements system.cpu.l2cache.tagsinuse 17651.004599 # Cycle average of tags in use @@ -560,18 +603,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 464839 system.cpu.l2cache.overall_accesses::total 465841 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151842 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.155864 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.235100 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.197430 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.199156 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.197430 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.199156 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34353.792415 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.888367 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.516471 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34540.434172 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34540.434172 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34489.695500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34489.695500 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 339500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 49 # number of cycles access was blocked @@ -606,18 +657,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2868929500 system.cpu.l2cache.overall_mshr_miss_latency::total 2900132500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.199156 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199156 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31018.914898 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31392.467997 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 927f52249..352fd32f4 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr index 1b49765a7..1ed796979 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout index db142b8a8..a4781a82f 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:40 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:03:38 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 068e22070..7df2c8121 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.300931 # Nu sim_ticks 300930958000 # Number of ticks simulated final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2479447 # Simulator instruction rate (inst/s) -host_op_rate 2479447 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1239733454 # Simulator tick rate (ticks/s) -host_mem_usage 205680 # Number of bytes of host memory used -host_seconds 242.74 # Real time elapsed on the host +host_inst_rate 3871430 # Simulator instruction rate (inst/s) +host_op_rate 3871429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1935730316 # Simulator tick rate (ticks/s) +host_mem_usage 206040 # Number of bytes of host memory used +host_seconds 155.46 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2782990928 # Number of bytes read from this memory -system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory -system.physmem.bytes_written 152669504 # Number of bytes written to this memory -system.physmem.num_reads 716375939 # Number of read requests responded to by this memory -system.physmem.num_writes 39451321 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9247938286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999999747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 507324022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9755262308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 375543340 # Number of bytes read from this memory +system.physmem.bytes_read::total 2782990928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2407447588 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2407447588 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 152669504 # Number of bytes written to this memory +system.physmem.bytes_written::total 152669504 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 601861897 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 114514042 # Number of read requests responded to by this memory +system.physmem.num_reads::total 716375939 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 39451321 # Number of write requests responded to by this memory +system.physmem.num_writes::total 39451321 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1247938539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9247938286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 507324022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 507324022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 86520ac69..f4efff3d6 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index 5a809a831..fcee7bced 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:36 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index fb6f85834..4082e04ad 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.765623 # Nu sim_ticks 765623032000 # Number of ticks simulated final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 835603 # Simulator instruction rate (inst/s) -host_op_rate 835603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1062971026 # Simulator tick rate (ticks/s) -host_mem_usage 214568 # Number of bytes of host memory used -host_seconds 720.27 # Real time elapsed on the host +host_inst_rate 1675799 # Simulator instruction rate (inst/s) +host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2131786057 # Simulator tick rate (ticks/s) +host_mem_usage 214908 # Number of bytes of host memory used +host_seconds 359.15 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5889984 # Number of bytes read from this memory -system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797824 # Number of bytes written to this memory -system.physmem.num_reads 92031 # Number of read requests responded to by this memory -system.physmem.num_writes 59341 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory +system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory +system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -110,11 +123,17 @@ system.cpu.icache.demand_accesses::total 601861898 # nu system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,11 +155,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 42135000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use @@ -184,13 +209,21 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22414.479737 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22414.479737 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -218,13 +251,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73734 # number of replacements system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use @@ -286,18 +327,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 455395 system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.158207 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.236340 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.201738 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.201738 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -332,18 +381,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158207 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236340 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.201738 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201738 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |