diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/long/se/00.gzip/ref/alpha | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha')
| -rw-r--r-- | tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt | 181 | ||||
| -rw-r--r-- | tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 1191 |
2 files changed, 671 insertions, 701 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 7484e6ff9..c659f4312 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.269672 # Nu sim_ticks 269671683500 # Number of ticks simulated final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125294 # Simulator instruction rate (inst/s) -host_op_rate 125294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56139844 # Simulator tick rate (ticks/s) -host_mem_usage 224468 # Number of bytes of host memory used -host_seconds 4803.57 # Real time elapsed on the host +host_inst_rate 149368 # Simulator instruction rate (inst/s) +host_op_rate 149368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66926769 # Simulator tick rate (ticks/s) +host_mem_usage 224496 # Number of bytes of host memory used +host_seconds 4029.35 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 26294 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1014 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1014 # Categorize write packet sizes system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 384531397 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests +system.physmem.totQLat 383646750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1095736750 # Sum of mem lat for all requests system.physmem.totBusLat 131400000 # Total cycles spent in databus access -system.physmem.totBankLat 580703750 # Total cycles spent in bank access -system.physmem.avgQLat 14632.09 # Average queueing delay per request -system.physmem.avgBankLat 22096.79 # Average bank access latency per request +system.physmem.totBankLat 580690000 # Total cycles spent in bank access +system.physmem.avgQLat 14598.43 # Average queueing delay per request +system.physmem.avgBankLat 22096.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41728.89 # Average memory access latency +system.physmem.avgMemAccLat 41694.70 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -379,14 +364,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.116549 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22879.116891 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.482794 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.953898 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.679858 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21684.482898 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.953897 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.680097 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy @@ -418,14 +403,14 @@ system.cpu.l2cache.overall_misses::total 26294 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199043000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1198171500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1198171500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1669703000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1714784000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1668831500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1713912500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1669703000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1714784000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1668831500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1713912500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -453,14 +438,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.057631 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56219.195424 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56178.333646 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56178.333646 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65182.646231 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65182.646231 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34645117 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418280186 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452925303 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 933604040 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 933604040 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34645117 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1351884226 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1386529343 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34645117 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1351884226 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1386529343 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34644438 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418276481 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452920919 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932715801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932715801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34644438 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350992282 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1385636720 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34644438 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350992282 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1385636720 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -504,25 +489,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41195.145065 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101401.257212 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91205.256343 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43773.632783 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43773.632783 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41194.337693 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.359030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91204.373540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43731.986168 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43731.986168 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.423527 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4093.423689 # Cycle average of tags in use system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 332210000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.423527 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.423689 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits @@ -543,12 +528,12 @@ system.cpu.dcache.overall_misses::cpu.data 2179204 # system.cpu.dcache.overall_misses::total 2179204 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23175803000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23175803000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29160484000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29160484000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29160484000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29160484000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23170641500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23170641500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29155322500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29155322500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29155322500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29155322500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -567,12 +552,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12976.569635 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12976.569635 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13381.254807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.679613 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.679613 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13378.886281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13378.886281 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked @@ -601,12 +586,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 455395 system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -617,12 +602,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index fd6611525..80e818735 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133806 # Number of seconds simulated -sim_ticks 133806308500 # Number of ticks simulated -final_tick 133806308500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133774 # Number of seconds simulated +sim_ticks 133773851500 # Number of ticks simulated +final_tick 133773851500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271409 # Simulator instruction rate (inst/s) -host_op_rate 271409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64213833 # Simulator tick rate (ticks/s) -host_mem_usage 226532 # Number of bytes of host memory used -host_seconds 2083.76 # Real time elapsed on the host +host_inst_rate 262576 # Simulator instruction rate (inst/s) +host_op_rate 262576 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62108832 # Simulator tick rate (ticks/s) +host_mem_usage 226536 # Number of bytes of host memory used +host_seconds 2153.86 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636352 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67200 # Number of bytes written to this memory -system.physmem.bytes_written::total 67200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25568 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26529 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 459649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12229259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12688908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 459649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 459649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 502218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 502218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 502218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 459649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12229259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13191127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26529 # Total number of read requests seen -system.physmem.writeReqs 1050 # Total number of write requests seen -system.physmem.cpureqs 27579 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697856 # Total number of bytes read from memory -system.physmem.bytesWritten 67200 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697856 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67200 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26524 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 455934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12233661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12689595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 455934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 501383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 501383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 501383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 455934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12233661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13190979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26524 # Total number of read requests seen +system.physmem.writeReqs 1048 # Total number of write requests seen +system.physmem.cpureqs 27572 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697536 # Total number of bytes read from memory +system.physmem.bytesWritten 67072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1631 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1647 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1682 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis @@ -72,44 +72,31 @@ system.physmem.perBankWrReqs::9 75 # Tr system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133806263000 # Total gap between requests +system.physmem.totGap 133773818000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26529 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1050 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.readPktSize::6 26524 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1048 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 8806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -137,8 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see @@ -151,8 +137,8 @@ system.physmem.wrQLenPdf::9 46 # Wh system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see @@ -161,7 +147,7 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 648232398 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1339932398 # Sum of mem lat for all requests -system.physmem.totBusLat 132570000 # Total cycles spent in databus access -system.physmem.totBankLat 559130000 # Total cycles spent in bank access -system.physmem.avgQLat 24448.68 # Average queueing delay per request -system.physmem.avgBankLat 21088.10 # Average bank access latency per request +system.physmem.totQLat 654284750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1345973500 # Sum of mem lat for all requests +system.physmem.totBusLat 132545000 # Total cycles spent in databus access +system.physmem.totBankLat 559143750 # Total cycles spent in bank access +system.physmem.avgQLat 24681.61 # Average queueing delay per request +system.physmem.avgBankLat 21092.60 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50536.79 # Average memory access latency +system.physmem.avgMemAccLat 50774.21 # Average memory access latency system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s @@ -186,41 +171,41 @@ system.physmem.avgConsumedWrBW 0.50 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.03 # Average write queue length over time -system.physmem.readRowHits 16972 # Number of row buffer hits during reads -system.physmem.writeRowHits 273 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 26.00 # Row buffer hit rate for writes -system.physmem.avgGap 4851744.55 # Average gap between requests -system.cpu.branchPred.lookups 76500721 # Number of BP lookups -system.cpu.branchPred.condPredicted 70919742 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2718676 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43116993 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41952631 # Number of BTB hits +system.physmem.avgWrQLen 9.24 # Average write queue length over time +system.physmem.readRowHits 16966 # Number of row buffer hits during reads +system.physmem.writeRowHits 271 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes +system.physmem.avgGap 4851799.58 # Average gap between requests +system.cpu.branchPred.lookups 76502410 # Number of BP lookups +system.cpu.branchPred.condPredicted 70922676 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2717282 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43095322 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41949760 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.299529 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1606312 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.341795 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1606512 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 241 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122623794 # DTB read hits -system.cpu.dtb.read_misses 28860 # DTB read misses +system.cpu.dtb.read_hits 122629608 # DTB read hits +system.cpu.dtb.read_misses 28810 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122652654 # DTB read accesses -system.cpu.dtb.write_hits 40761180 # DTB write hits -system.cpu.dtb.write_misses 25673 # DTB write misses +system.cpu.dtb.read_accesses 122658418 # DTB read accesses +system.cpu.dtb.write_hits 40760367 # DTB write hits +system.cpu.dtb.write_misses 25602 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40786853 # DTB write accesses -system.cpu.dtb.data_hits 163384974 # DTB hits -system.cpu.dtb.data_misses 54533 # DTB misses +system.cpu.dtb.write_accesses 40785969 # DTB write accesses +system.cpu.dtb.data_hits 163389975 # DTB hits +system.cpu.dtb.data_misses 54412 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163439507 # DTB accesses -system.cpu.itb.fetch_hits 65534932 # ITB hits +system.cpu.dtb.data_accesses 163444387 # DTB accesses +system.cpu.itb.fetch_hits 65529846 # ITB hits system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65534973 # ITB accesses +system.cpu.itb.fetch_accesses 65529887 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,133 +219,133 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267612618 # number of cpu cycles simulated +system.cpu.numCycles 267547704 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67186400 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699453099 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76500721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43558943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117852914 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11666249 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73358963 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 67181660 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699454641 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76502410 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43556272 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117851527 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11664601 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73301689 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65534932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 934826 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267314333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.616594 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.444810 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65529846 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 933458 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267250540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.617224 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444995 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149461419 55.91% 55.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10349982 3.87% 59.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11850266 4.43% 64.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10577716 3.96% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7012506 2.62% 70.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2870690 1.07% 71.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3579816 1.34% 73.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3108437 1.16% 74.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68503501 25.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149399013 55.90% 55.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10348526 3.87% 59.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11849388 4.43% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10578020 3.96% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7012807 2.62% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2871984 1.07% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3578789 1.34% 73.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3106707 1.16% 74.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68505306 25.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267314333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285864 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.613678 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84322022 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57655855 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102751859 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13670665 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8913932 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3876852 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 942 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691462372 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3197 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8913932 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92304341 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12773232 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1346 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103106270 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50215212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 681285072 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 434 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38522944 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5472741 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520920645 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 897379043 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 897376453 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2590 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267250540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285939 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.614317 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84320129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57595253 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102753479 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13668133 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8913546 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3876280 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 932 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691464517 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3449 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8913546 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92299678 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12776720 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1189 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103108433 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50150974 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681302234 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 431 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38477727 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5455282 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520934901 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 897390123 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 897387366 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2757 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 57065756 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 66 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112077327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 127005785 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42387861 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14833107 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10089887 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621266103 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 59 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604722021 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299730 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 55073821 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30009810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267314333 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.262213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.825151 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 57080012 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 63 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112027328 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127008438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42384710 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14844783 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10088023 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621271293 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604725807 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299798 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 55080788 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30005964 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267250540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.262767 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823653 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52513972 19.65% 19.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55954300 20.93% 40.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53424383 19.99% 60.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36299246 13.58% 74.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31212895 11.68% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23807225 8.91% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10138155 3.79% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3408674 1.28% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 555483 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52429829 19.62% 19.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55852855 20.90% 40.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53444845 20.00% 60.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36460113 13.64% 74.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31255141 11.70% 85.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23773948 8.90% 94.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10075913 3.77% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3406027 1.27% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 551869 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267314333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267250540 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2798552 71.38% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 727516 18.56% 89.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 394572 10.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2756472 71.14% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 40 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 728591 18.80% 89.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 389871 10.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439175234 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7035 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439176954 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7066 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued @@ -388,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124352577 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41187127 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124356224 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41185515 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604722021 # Type of FU issued -system.cpu.iq.rate 2.259692 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3920679 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480975025 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 676343136 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596595322 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3759 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2270 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1723 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608640802 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1898 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12279325 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604725807 # Type of FU issued +system.cpu.iq.rate 2.260254 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3874974 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006408 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480873086 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 676355161 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596602519 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3840 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2402 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1730 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608598846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1935 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12280408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12491743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36092 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5478 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2936540 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12494396 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35705 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5495 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2933389 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6432 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 54776 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6442 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 54892 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8913932 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1438086 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 192048 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 664143136 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1694587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 127005785 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42387861 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 59 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 143884 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7497 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5478 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342912 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1811100 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3154012 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599591446 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122652830 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5130575 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8913546 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1440408 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 191911 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 664145675 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1694595 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127008438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42384710 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 55 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 143753 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7490 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5495 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342563 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1811283 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3153846 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599598114 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122658565 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5127693 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42876974 # number of nop insts executed -system.cpu.iew.exec_refs 163458157 # number of memory reference insts executed -system.cpu.iew.exec_branches 66641389 # Number of branches executed -system.cpu.iew.exec_stores 40805327 # Number of stores executed -system.cpu.iew.exec_rate 2.240520 # Inst execution rate -system.cpu.iew.wb_sent 597536756 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596597045 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415962909 # num instructions producing a value -system.cpu.iew.wb_consumers 530370743 # num instructions consuming a value +system.cpu.iew.exec_nop 42874327 # number of nop insts executed +system.cpu.iew.exec_refs 163462793 # number of memory reference insts executed +system.cpu.iew.exec_branches 66641793 # Number of branches executed +system.cpu.iew.exec_stores 40804228 # Number of stores executed +system.cpu.iew.exec_rate 2.241089 # Inst execution rate +system.cpu.iew.wb_sent 597543507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596604249 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415969736 # num instructions producing a value +system.cpu.iew.wb_consumers 530347418 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229331 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784287 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229899 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62162261 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 62164646 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2717793 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258400401 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.329164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.692856 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2716416 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258336994 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329736 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.693311 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79574518 30.80% 30.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72566023 28.08% 58.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25599330 9.91% 68.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9197400 3.56% 72.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10258446 3.97% 76.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20921268 8.10% 84.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6836400 2.65% 87.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3734572 1.45% 88.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29712444 11.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79521079 30.78% 30.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72557315 28.09% 58.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25650829 9.93% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9136101 3.54% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10241480 3.96% 76.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20967757 8.12% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6801640 2.63% 87.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3711202 1.44% 88.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29749591 11.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258400401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258336994 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +461,192 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29712444 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29749591 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892642792 # The number of ROB reads -system.cpu.rob.rob_writes 1336966756 # The number of ROB writes -system.cpu.timesIdled 34291 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 298285 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892544623 # The number of ROB reads +system.cpu.rob.rob_writes 1336970755 # The number of ROB writes +system.cpu.timesIdled 34274 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 297164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.473188 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.473188 # CPI: Total CPI of All Threads -system.cpu.ipc 2.113325 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.113325 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 845166386 # number of integer regfile reads -system.cpu.int_regfile_writes 490617161 # number of integer regfile writes -system.cpu.fp_regfile_reads 389 # number of floating regfile reads +system.cpu.cpi 0.473073 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473073 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113838 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113838 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 845171662 # number of integer regfile reads +system.cpu.int_regfile_writes 490625638 # number of integer regfile writes +system.cpu.fp_regfile_reads 396 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 825.582407 # Cycle average of tags in use -system.cpu.icache.total_refs 65533545 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 66939.269663 # Average number of references to valid blocks. +system.cpu.icache.replacements 39 # number of replacements +system.cpu.icache.tagsinuse 824.684718 # Cycle average of tags in use +system.cpu.icache.total_refs 65528462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 971 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67485.542739 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 825.582407 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403116 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403116 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65533545 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65533545 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65533545 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65533545 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65533545 # number of overall hits -system.cpu.icache.overall_hits::total 65533545 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1386 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1386 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1386 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1386 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1386 # number of overall misses -system.cpu.icache.overall_misses::total 1386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74542000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 74542000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 74542000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 74542000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 74542000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 74542000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65534931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65534931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65534931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65534931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65534931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65534931 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 824.684718 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.402678 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.402678 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65528462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65528462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65528462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65528462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65528462 # number of overall hits +system.cpu.icache.overall_hits::total 65528462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses +system.cpu.icache.overall_misses::total 1383 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 72600500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 72600500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 72600500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 72600500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 72600500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 72600500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65529845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65529845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65529845 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65529845 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65529845 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65529845 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53782.106782 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53782.106782 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53782.106782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53782.106782 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52494.938539 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52494.938539 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52494.938539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52494.938539 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.400000 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 979 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54570500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54570500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54570500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54570500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54570500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54570500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 412 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58186.138825 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58186.138825 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks +system.cpu.l2cache.writebacks::total 1049 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 953 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5258 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21266 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21266 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25571 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26524 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25571 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26524 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41181755 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 363891160 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 405072915 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1243149416 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1243149416 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41181755 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1607040576 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1648222331 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41181755 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1607040576 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1648222331 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020464 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024879 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056932 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43212.754460 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84527.563298 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77039.352415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.134205 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.134205 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460939 # number of replacements -system.cpu.dcache.tagsinuse 4090.899850 # Cycle average of tags in use -system.cpu.dcache.total_refs 146914514 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465035 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.921412 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 301771000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.899850 # Average occupied blocks per requestor +system.cpu.dcache.replacements 460826 # number of replacements +system.cpu.dcache.tagsinuse 4090.898597 # Cycle average of tags in use +system.cpu.dcache.total_refs 146919615 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464922 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 316.009169 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 301835000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.898597 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998755 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998755 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109265934 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109265934 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37648563 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37648563 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146914497 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146914497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146914497 # number of overall hits -system.cpu.dcache.overall_hits::total 146914497 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1025246 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1025246 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802758 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802758 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2828004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2828004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2828004 # number of overall misses -system.cpu.dcache.overall_misses::total 2828004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15342477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15342477500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26169777829 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26169777829 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 37000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 37000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41512255329 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41512255329 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41512255329 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41512255329 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110291180 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110291180 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 109271003 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109271003 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648598 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648598 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146919601 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146919601 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146919601 # number of overall hits +system.cpu.dcache.overall_hits::total 146919601 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1024794 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1024794 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802723 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802723 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2827517 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2827517 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2827517 # number of overall misses +system.cpu.dcache.overall_misses::total 2827517 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15336763000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15336763000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26197701326 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26197701326 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 20000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 20000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41534464326 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41534464326 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41534464326 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41534464326 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110295797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110295797 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149742501 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149742501 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149742501 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149742501 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009296 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009296 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045696 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045696 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.190476 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.190476 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018886 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018886 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018886 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018886 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14964.679209 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14964.679209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14516.522922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14516.522922 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14678.994559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14678.994559 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301355 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2673 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17784 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 149747118 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149747118 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149747118 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149747118 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009291 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009291 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045695 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045695 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.125000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018882 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018882 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018882 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018882 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14965.703351 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14965.703351 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14532.294382 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14532.294382 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14689.377403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14689.377403 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 303569 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2051 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17829 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.945288 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 243 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.026698 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 186.454545 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445006 # number of writebacks -system.cpu.dcache.writebacks::total 445006 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814778 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 814778 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548191 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1548191 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2362969 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2362969 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2362969 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2362969 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 465035 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 465035 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 465035 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 465035 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697344500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697344500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097543997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097543997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6794888497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6794888497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6794888497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6794888497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12815.936389 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12815.936389 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16096.131851 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16096.131851 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 444903 # number of writebacks +system.cpu.dcache.writebacks::total 444903 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814423 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 814423 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548172 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548172 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2362595 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2362595 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2362595 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2362595 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210371 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210371 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254551 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254551 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464922 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464922 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464922 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2696208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2696208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4103693497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4103693497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6799901497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6799901497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6799901497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6799901497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12816.443331 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12816.443331 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16121.301810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16121.301810 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |