diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/se/00.gzip/ref/alpha | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha')
9 files changed, 955 insertions, 955 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 201ee02a7..0e8616cf5 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 4b4f6933d..282b60660 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:24 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:09:56 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 271948359500 because target called exit() +Exiting @ tick 274137499500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index c0f2578f2..5b9902e79 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.271948 # Number of seconds simulated -sim_ticks 271948359500 # Number of ticks simulated -final_tick 271948359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.274137 # Number of seconds simulated +sim_ticks 274137499500 # Number of ticks simulated +final_tick 274137499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167086 # Simulator instruction rate (inst/s) -host_op_rate 167086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75497413 # Simulator tick rate (ticks/s) -host_mem_usage 219024 # Number of bytes of host memory used -host_seconds 3602.09 # Real time elapsed on the host +host_inst_rate 167497 # Simulator instruction rate (inst/s) +host_op_rate 167497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76292716 # Simulator tick rate (ticks/s) +host_mem_usage 218988 # Number of bytes of host memory used +host_seconds 3593.23 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,37 +23,37 @@ system.physmem.num_reads::cpu.data 25316 # Nu system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5957837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6155757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197920 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197920 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 209687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 209687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 209687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5957837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6365444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5910260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6106600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5910260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6314612 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517207 # DTB read hits +system.cpu.dtb.read_hits 114518785 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114519838 # DTB read accesses -system.cpu.dtb.write_hits 39661898 # DTB write hits +system.cpu.dtb.read_accesses 114521416 # DTB read accesses +system.cpu.dtb.write_hits 39662429 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664200 # DTB write accesses -system.cpu.dtb.data_hits 154179105 # DTB hits +system.cpu.dtb.write_accesses 39664731 # DTB write accesses +system.cpu.dtb.data_hits 154181214 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154184038 # DTB accesses -system.cpu.itb.fetch_hits 25013413 # ITB hits +system.cpu.dtb.data_accesses 154186147 # DTB accesses +system.cpu.itb.fetch_hits 25086764 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25013435 # ITB accesses +system.cpu.itb.fetch_accesses 25086786 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 543896720 # number of cpu cycles simulated +system.cpu.numCycles 548275000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86316674 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81371545 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36360802 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52676212 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34326876 # Number of BTB hits +system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81377487 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36366052 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52958494 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34331818 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 65.165802 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36904283 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49412391 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541655345 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541561070 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005510191 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1005415916 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 254971320 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155049936 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33767521 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2588294 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36355815 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26192089 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.124753 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412333421 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 255070177 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155050348 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36361065 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26186838 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.133148 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334459 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538321020 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 539843930 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 407697 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 54736228 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489160492 # Number of cycles cpu stages are processed. -system.cpu.activity 89.936283 # Percentage of cycles cpu is active +system.cpu.timesIdled 672410 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59138192 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489136808 # Number of cycles cpu stages are processed. +system.cpu.activity 89.213772 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.903698 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.910972 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.903698 # CPI: Total CPI of All Threads -system.cpu.ipc 1.106565 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.910972 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.106565 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 205017879 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338878841 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.305734 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 233023029 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310873691 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.156750 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 202072445 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341824275 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.847276 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 432365235 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111531485 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.506004 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 196896047 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347000673 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.799001 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 209383014 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338891986 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.810585 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 237433241 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310841759 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.694498 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 206489440 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341785560 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.338345 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 436702963 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.349649 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201266098 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347008902 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.291031 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.555018 # Cycle average of tags in use -system.cpu.icache.total_refs 25012389 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 728.512372 # Cycle average of tags in use +system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29254.256140 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.555018 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355740 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355740 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25012389 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25012389 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25012389 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25012389 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25012389 # number of overall hits -system.cpu.icache.overall_hits::total 25012389 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses -system.cpu.icache.overall_misses::total 1022 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56014500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56014500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56014500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56014500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56014500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56014500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25013411 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25013411 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25013411 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25013411 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25013411 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25013411 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 728.512372 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25085741 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25085741 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25085741 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25085741 # number of overall hits +system.cpu.icache.overall_hits::total 25085741 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses +system.cpu.icache.overall_misses::total 1021 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 57700000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 57700000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 57700000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 57700000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 57700000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 57700000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25086762 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25086762 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25086762 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25086762 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25086762 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25086762 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54808.708415 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54808.708415 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54808.708415 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54808.708415 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56513.222331 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56513.222331 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56513.222331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56513.222331 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45159500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45159500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45159500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45159500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45159500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45159500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46832500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46832500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46832500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46832500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46832500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46832500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52818.128655 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52818.128655 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54774.853801 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54774.853801 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.146809 # Cycle average of tags in use -system.cpu.dcache.total_refs 152406141 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.836595 # Cycle average of tags in use +system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.668016 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 260481000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.146809 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999548 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999548 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38285634 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38285634 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152406141 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152406141 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152406141 # number of overall hits -system.cpu.dcache.overall_hits::total 152406141 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1165687 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1165687 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1559222 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1559222 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1559222 # number of overall misses -system.cpu.dcache.overall_misses::total 1559222 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5944936500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5944936500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18222826500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18222826500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24167763000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24167763000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24167763000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24167763000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.836595 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120497 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38285544 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38285544 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152406041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152406041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152406041 # number of overall hits +system.cpu.dcache.overall_hits::total 152406041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393545 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393545 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1165777 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1165777 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1559322 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses +system.cpu.dcache.overall_misses::total 1559322 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7771987500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228669000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30228669000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38000656500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38000656500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38000656500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38000656500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363 system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15106.500057 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15106.500057 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15632.692567 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15632.692567 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15499.885841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15499.885841 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10505000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2188634000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2561 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 211460 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4101.913315 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10350.108768 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029550 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029550 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.662796 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.662796 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25930.061238 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25930.061238 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24369.986763 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24369.986763 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28255500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3561 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7934.709351 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks system.cpu.dcache.writebacks::total 436902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911524 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911524 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1103827 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1103827 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1103827 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1103827 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192313 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192313 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911614 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911614 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1103927 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1103927 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1103927 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1103927 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2433186000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2433186000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3829787500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3829787500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6262973500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6262973500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6262973500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6262973500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136800000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136800000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820778500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7820778500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820778500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7820778500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,35 +318,35 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12091.446688 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12091.446688 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15068.233771 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15068.233771 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.732070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.732070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.652219 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.652219 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 917 # number of replacements -system.cpu.l2cache.tagsinuse 22852.415153 # Cycle average of tags in use -system.cpu.l2cache.total_refs 538842 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22837.818259 # Cycle average of tags in use +system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.284159 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21652.224350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 719.469676 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 480.721127 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660773 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021956 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014670 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697400 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21635.297134 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 719.415397 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 483.105728 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.696955 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197093 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197107 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 197099 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 197113 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232986 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232986 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232980 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232980 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits @@ -364,24 +364,24 @@ system.cpu.l2cache.demand_misses::total 26157 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44029000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214315000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 258344000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1104963500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1104963500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44029000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1319278500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1363307500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44029000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1319278500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1363307500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 260244500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215316500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1215316500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1430177000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1475561000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1430177000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1475561000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254176 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254176 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses @@ -389,32 +389,32 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024551 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083389 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083389 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020475 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024550 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083391 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52353.151011 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52018.203883 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.984882 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52130.755803 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52130.755803 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52120.178155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52120.178155 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 766500 # number of cycles access was blocked +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.606796 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52458.072969 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57337.068315 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57337.068315 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56411.706235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56411.706235 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3459500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 116 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9462.962963 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29823.275862 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -431,39 +431,39 @@ system.cpu.l2cache.demand_mshr_misses::total 26157 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33775500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 164851000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198626500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 849849500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 849849500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33775500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1014700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1048476000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33775500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1014700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1048476000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954428500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954428500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119789500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1154935500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119789500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1154935500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024551 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083389 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40161.117717 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40012.378641 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40037.593227 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40094.805624 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40094.805624 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45028.708247 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45028.708247 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 53e4b73f0..5bc85930f 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index 21003a7f0..ddf76222f 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:29 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:10:10 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 133563007500 because target called exit() +Exiting @ tick 135504709500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 38226af10..9f9fc3c8f 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133563 # Number of seconds simulated -sim_ticks 133563007500 # Number of ticks simulated -final_tick 133563007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.135505 # Number of seconds simulated +sim_ticks 135504709500 # Number of ticks simulated +final_tick 135504709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 301381 # Simulator instruction rate (inst/s) -host_op_rate 301381 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71175252 # Simulator tick rate (ticks/s) -host_mem_usage 220044 # Number of bytes of host memory used -host_seconds 1876.54 # Real time elapsed on the host +host_inst_rate 302966 # Simulator instruction rate (inst/s) +host_op_rate 302966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72589653 # Simulator tick rate (ticks/s) +host_mem_usage 220016 # Number of bytes of host memory used +host_seconds 1866.72 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory -system.physmem.bytes_read::total 1688512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 58688 # Number of bytes written to this memory -system.physmem.bytes_written::total 58688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26383 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 917 # Number of write requests responded to by this memory -system.physmem.num_writes::total 917 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 457612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12184452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12642063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 457612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 457612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 439403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 439403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 439403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 457612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12184452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13081466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627200 # Number of bytes read from this memory +system.physmem.bytes_read::total 1688960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58880 # Number of bytes written to this memory +system.physmem.bytes_written::total 58880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25425 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26390 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 920 # Number of write requests responded to by this memory +system.physmem.num_writes::total 920 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 455778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12008439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12464216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 455778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 434524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 434524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 434524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 455778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12008439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12898740 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123849413 # DTB read hits -system.cpu.dtb.read_misses 20691 # DTB read misses +system.cpu.dtb.read_hits 123973202 # DTB read hits +system.cpu.dtb.read_misses 28801 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123870104 # DTB read accesses -system.cpu.dtb.write_hits 40835064 # DTB write hits -system.cpu.dtb.write_misses 30091 # DTB write misses +system.cpu.dtb.read_accesses 124002003 # DTB read accesses +system.cpu.dtb.write_hits 40826098 # DTB write hits +system.cpu.dtb.write_misses 43038 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40865155 # DTB write accesses -system.cpu.dtb.data_hits 164684477 # DTB hits -system.cpu.dtb.data_misses 50782 # DTB misses +system.cpu.dtb.write_accesses 40869136 # DTB write accesses +system.cpu.dtb.data_hits 164799300 # DTB hits +system.cpu.dtb.data_misses 71839 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164735259 # DTB accesses -system.cpu.itb.fetch_hits 66492910 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 164871139 # DTB accesses +system.cpu.itb.fetch_hits 66654125 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66492948 # ITB accesses +system.cpu.itb.fetch_accesses 66654164 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,247 +67,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267126016 # number of cpu cycles simulated +system.cpu.numCycles 271009420 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78502606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72859176 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3048930 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42879233 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41644328 # Number of BTB hits +system.cpu.BPredUnit.lookups 78550084 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72909802 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3049618 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42960098 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41697412 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1629564 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 215 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68435581 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 710898129 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78502606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43273892 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119207604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12936161 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 69569484 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1627945 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 225 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68633140 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 712310900 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78550084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43325357 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119402153 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13096957 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72942972 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 914 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66492910 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 942940 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267090859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.661634 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.464377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66654125 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 952316 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 270973447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.628711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.455670 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 147883255 55.37% 55.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10367188 3.88% 59.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11844651 4.43% 63.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10612793 3.97% 67.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6990815 2.62% 70.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2667876 1.00% 71.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3494727 1.31% 72.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3104174 1.16% 73.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70125380 26.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151571294 55.94% 55.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10370513 3.83% 59.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11843929 4.37% 64.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10611726 3.92% 68.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6997698 2.58% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2669321 0.99% 71.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3542857 1.31% 72.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3106060 1.15% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70260049 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267090859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293879 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.661284 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85625908 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 53897418 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104721883 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12969411 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9876239 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3910148 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702131172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4692 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9876239 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93864195 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11132886 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1433 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104174566 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48041540 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690226135 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36911224 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4900299 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527321421 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 906904042 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 906901104 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2938 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 270973447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289843 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.628362 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 86239898 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56889648 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104078394 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13772489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9993018 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3907857 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1149 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703284399 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4152 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9993018 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 94515684 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12291800 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1567 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104313558 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49857820 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 691204157 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5604 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37465189 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 6251536 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527653035 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 907560525 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 907557502 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3023 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63466532 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 116 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 106984731 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129019631 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42434130 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14712304 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9648397 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626510721 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 98 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608418192 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 334492 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60261200 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33473416 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 81 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267090859 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.277945 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.835634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63798146 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 98 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 109 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 110554649 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129201281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42494660 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14706454 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9724071 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626942555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608726605 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 349964 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60693556 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33842727 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 71 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270973447 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.246444 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.833475 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52595450 19.69% 19.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54748440 20.50% 40.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53400082 19.99% 60.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36696955 13.74% 73.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30804090 11.53% 85.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24162728 9.05% 94.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10693904 4.00% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3328381 1.25% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 660829 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55588929 20.51% 20.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55068872 20.32% 40.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 54063102 19.95% 60.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36829632 13.59% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31174989 11.50% 85.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23761374 8.77% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10484912 3.87% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3386761 1.25% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 614876 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267090859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270973447 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2950080 75.40% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 582636 14.89% 90.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 379789 9.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2718607 75.19% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 33 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 573635 15.86% 91.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323505 8.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441018930 72.49% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7345 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126131577 20.73% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41260299 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441168683 72.47% 72.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7348 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126287390 20.75% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41263140 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608418192 # Type of FU issued -system.cpu.iq.rate 2.277645 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3912544 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006431 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1488170355 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 686774500 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598832188 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2359 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1719 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612328769 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1967 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12182137 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608726605 # Type of FU issued +system.cpu.iq.rate 2.246146 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3615780 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005940 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1492388483 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 687638825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598965859 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3918 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2476 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1713 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612340430 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1955 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12180256 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14505589 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 34191 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4885 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2982809 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14687239 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33196 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5150 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3043339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6785 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 71183 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6743 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 162277 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9876239 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 295412 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670453714 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1691855 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129019631 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42434130 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 98 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 899 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7278 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4885 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1348504 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2206028 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3554532 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602596052 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123870207 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5822140 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9993018 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 593522 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 81920 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 671227772 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1733098 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129201281 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42494660 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9721 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 904 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5150 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1349008 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2205914 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3554922 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602873827 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 124002105 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5852778 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43942895 # number of nop insts executed -system.cpu.iew.exec_refs 164752686 # number of memory reference insts executed -system.cpu.iew.exec_branches 67005259 # Number of branches executed -system.cpu.iew.exec_stores 40882479 # Number of stores executed -system.cpu.iew.exec_rate 2.255849 # Inst execution rate -system.cpu.iew.wb_sent 600080079 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598833907 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417539542 # num instructions producing a value -system.cpu.iew.wb_consumers 531416482 # num instructions consuming a value +system.cpu.iew.exec_nop 44285129 # number of nop insts executed +system.cpu.iew.exec_refs 164888589 # number of memory reference insts executed +system.cpu.iew.exec_branches 67046898 # Number of branches executed +system.cpu.iew.exec_stores 40886484 # Number of stores executed +system.cpu.iew.exec_rate 2.224549 # Inst execution rate +system.cpu.iew.wb_sent 600233130 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598967572 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417280903 # num instructions producing a value +system.cpu.iew.wb_consumers 532263406 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.241766 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.785711 # average fanout of values written-back +system.cpu.iew.wb_rate 2.210136 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.783974 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 68437583 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69254422 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3047922 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 257214620 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.339902 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.706449 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3048560 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 260980429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.306138 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.692981 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78375558 30.47% 30.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72865724 28.33% 58.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26619590 10.35% 69.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8074736 3.14% 72.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10311668 4.01% 76.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20443429 7.95% 84.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6319286 2.46% 86.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3488714 1.36% 88.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30715915 11.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82002311 31.42% 31.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72802901 27.90% 59.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26180796 10.03% 69.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8233037 3.15% 72.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10839669 4.15% 76.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20863917 7.99% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6243794 2.39% 87.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3659698 1.40% 88.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30154306 11.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 257214620 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 260980429 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30715915 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30154306 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 896728862 # The number of ROB reads -system.cpu.rob.rob_writes 1350487768 # The number of ROB writes -system.cpu.timesIdled 758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35157 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 901873119 # The number of ROB reads +system.cpu.rob.rob_writes 1352238413 # The number of ROB writes +system.cpu.timesIdled 924 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35973 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.472328 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.472328 # CPI: Total CPI of All Threads -system.cpu.ipc 2.117175 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.117175 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848664377 # number of integer regfile reads -system.cpu.int_regfile_writes 492741272 # number of integer regfile writes -system.cpu.fp_regfile_reads 384 # number of floating regfile reads -system.cpu.fp_regfile_writes 47 # number of floating regfile writes +system.cpu.cpi 0.479194 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.479194 # CPI: Total CPI of All Threads +system.cpu.ipc 2.086837 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.086837 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848955638 # number of integer regfile reads +system.cpu.int_regfile_writes 492807399 # number of integer regfile writes +system.cpu.fp_regfile_reads 373 # number of floating regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 44 # number of replacements -system.cpu.icache.tagsinuse 827.496665 # Cycle average of tags in use -system.cpu.icache.total_refs 66491540 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 975 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 68196.451282 # Average number of references to valid blocks. +system.cpu.icache.replacements 45 # number of replacements +system.cpu.icache.tagsinuse 834.184340 # Cycle average of tags in use +system.cpu.icache.total_refs 66652701 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 988 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67462.247976 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 827.496665 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.404051 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.404051 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66491540 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66491540 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66491540 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66491540 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66491540 # number of overall hits -system.cpu.icache.overall_hits::total 66491540 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1370 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1370 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1370 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1370 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1370 # number of overall misses -system.cpu.icache.overall_misses::total 1370 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47830500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47830500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47830500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47830500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47830500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47830500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66492910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66492910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66492910 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66492910 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66492910 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66492910 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 834.184340 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.407317 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.407317 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66652701 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66652701 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66652701 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66652701 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66652701 # number of overall hits +system.cpu.icache.overall_hits::total 66652701 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1424 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1424 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1424 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1424 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1424 # number of overall misses +system.cpu.icache.overall_misses::total 1424 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 52187000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52187000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 52187000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52187000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 52187000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52187000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66654125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66654125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66654125 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66654125 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66654125 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66654125 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34912.773723 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34912.773723 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34912.773723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34912.773723 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36648.174157 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36648.174157 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36648.174157 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36648.174157 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36648.174157 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36648.174157 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,296 +390,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 395 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 395 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 395 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 395 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 395 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 395 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 975 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 975 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34096000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34096000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34096000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34096000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34096000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34096000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 988 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 988 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 988 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 988 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 988 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37189000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37189000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37189000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37189000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37189000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37189000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34970.256410 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34970.256410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34970.256410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34970.256410 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37640.688259 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37640.688259 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37640.688259 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37640.688259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37640.688259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37640.688259 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460470 # number of replacements -system.cpu.dcache.tagsinuse 4093.773805 # Cycle average of tags in use -system.cpu.dcache.total_refs 149240040 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464566 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 321.246152 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 124982000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.773805 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999456 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999456 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 111034129 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 111034129 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38205852 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38205852 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 59 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 59 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 149239981 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 149239981 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 149239981 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999361 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 111085210 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111085210 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37680869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37680869 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 148766079 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 148766079 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 148766079 # number of overall hits +system.cpu.dcache.overall_hits::total 148766079 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 577881 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 577881 # 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number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 7000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 7000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17349599733 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17349599733 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17349599733 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17349599733 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 111654544 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 111654544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2348333 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2348333 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2348333 # number of overall misses +system.cpu.dcache.overall_misses::total 2348333 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8220967500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8220967500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 45275400067 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45275400067 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 31000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 31000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53496367567 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53496367567 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53496367567 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53496367567 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111663091 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111663091 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151105865 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151105865 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151105865 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151105865 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005557 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005557 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031570 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031570 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.032787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.012348 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.012348 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.012348 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.012348 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7598.426054 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7598.426054 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10145.111788 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10145.111788 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9298.327084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9298.327084 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 113496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 187500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 51 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 51 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151114412 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151114412 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151114412 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151114412 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005175 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005175 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.044877 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.044877 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.039216 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.039216 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015540 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015540 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015540 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015540 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14226.056057 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14226.056057 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25572.791619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25572.791619 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22780.571396 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22780.571396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22780.571396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22780.571396 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 267496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 204500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4934.608696 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18750 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2286.290598 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20450 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444730 # number of writebacks -system.cpu.dcache.writebacks::total 444730 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 410277 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 410277 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 991041 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 991041 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 444923 # number of writebacks +system.cpu.dcache.writebacks::total 444923 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367661 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 367661 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2620523462 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006449 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006449 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3517.450437 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3517.450437 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7394.522073 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7394.522073 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1883609 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1883609 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1883609 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1883609 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210220 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6787885842 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6787885842 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6787885842 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6787885842 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003075 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003075 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7915.148416 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7915.148416 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20133.134811 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20133.134811 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14606.273491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14606.273491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14606.273491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14606.273491 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 820.682242 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 617.081022 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.656803 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025045 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018832 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.700680 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 205851 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 205871 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 444730 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 444730 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233287 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.979487 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054735 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056672 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.979487 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054735 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056672 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.314136 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34280.499184 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34291.396414 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34703.396244 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34703.396244 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1002606996 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 988 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 210216 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 211204 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 444923 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 444923 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254508 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254508 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 988 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 464724 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 465712 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 988 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 464724 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 465712 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.976721 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020431 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083023 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083023 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976721 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.054710 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.056666 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976721 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.054710 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.056666 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35878.238342 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34692.433062 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34909.980989 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38759.133743 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38759.133743 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35878.238342 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38072.153235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37991.928609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35878.238342 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38072.153235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37991.928609 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 81496 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10187 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 917 # number of writebacks -system.cpu.l2cache.writebacks::total 917 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 955 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4287 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5242 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21141 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21141 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 955 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25428 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26383 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 955 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25428 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26383 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29726000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 133026000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 162752000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 668424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 668424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29726000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 801450000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 831176000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29726000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 801450000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 831176000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020401 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024830 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083092 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083092 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056672 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056672 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31126.701571 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31030.090973 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31047.691721 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31617.425855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31617.425855 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 920 # number of writebacks +system.cpu.l2cache.writebacks::total 920 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4295 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5260 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21130 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21130 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25425 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26390 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25425 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26390 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31552000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135966500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167518500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 754186996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 754186996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31552000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 890153496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 921705496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31552000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 890153496 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 921705496 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.976721 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020431 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976721 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054710 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056666 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976721 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054710 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056666 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32696.373057 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31656.926659 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31847.623574 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35692.711595 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35692.711595 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32696.373057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35010.953628 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34926.316635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32696.373057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35010.953628 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34926.316635 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 265a2a956..a9c226ca1 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index be37b32c1..fcee711f2 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:37 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:11:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 762853846000 because target called exit() +Exiting @ tick 764109115000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index a7b4a0a92..6b056dd7e 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.762854 # Number of seconds simulated -sim_ticks 762853846000 # Number of ticks simulated -final_tick 762853846000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.764109 # Number of seconds simulated +sim_ticks 764109115000 # Number of ticks simulated +final_tick 764109115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2331221 # Simulator instruction rate (inst/s) -host_op_rate 2331221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2954822927 # Simulator tick rate (ticks/s) -host_mem_usage 219024 # Number of bytes of host memory used -host_seconds 258.17 # Real time elapsed on the host +host_inst_rate 2465110 # Simulator instruction rate (inst/s) +host_op_rate 2465110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3129668646 # Simulator tick rate (ticks/s) +host_mem_usage 218984 # Number of bytes of host memory used +host_seconds 244.15 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25315 # Nu system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory system.physmem.num_writes::total 883 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 65690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2123814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2189505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 65690 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 65690 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 74080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 74080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 74080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 65690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2123814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2263584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 65582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2120325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2185908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 65582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 65582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 73958 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 73958 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 73958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 65582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2120325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2259866 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1525707692 # number of cpu cycles simulated +system.cpu.numCycles 1528218230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1525707692 # Number of busy cycles +system.cpu.num_busy_cycles 1528218230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.359193 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.286058 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.359193 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328789 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328789 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.286058 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328753 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328753 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44016000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44016000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44016000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44016000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44016000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44016000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44165000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44165000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44165000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44165000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44165000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44165000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55366.037736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55366.037736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55366.037736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55366.037736 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55553.459119 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55553.459119 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55553.459119 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55553.459119 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41780000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41780000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41780000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41780000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41780000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41780000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52553.459119 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52553.459119 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.177385 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.128141 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 571210000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.177385 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999555 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999555 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 590218000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.128141 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2990372000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2990372000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4448388000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4448388000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7438760000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7438760000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7438760000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7438760000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2991812000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2991812000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4452609000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4452609000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7444421000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7444421000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7444421000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7444421000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14860.320426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14860.320426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17502.106916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17502.106916 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16334.742367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16334.742367 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14867.476346 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14867.476346 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17518.714368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17518.714368 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16347.173333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16347.173333 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2388116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2388116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3690120000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3690120000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078236000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6078236000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078236000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6078236000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11867.476346 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11867.476346 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14518.714368 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14518.714368 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 903 # number of replacements -system.cpu.l2cache.tagsinuse 22842.001450 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22839.375690 # Cycle average of tags in use system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21648.658638 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 668.310399 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 525.032413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660665 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.020395 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016023 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697083 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21645.673483 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 668.235332 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 525.466875 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660574 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.020393 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016036 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697002 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits |