stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

1 files changed, 41 insertions, 5 deletions

diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
index 42a2fd6fd..f13bbbf22 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.793670                       # Nu
 sim_ticks                                793670137000                       # Number of ticks simulated
 final_tick                               793670137000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 904187                       # Simulator instruction rate (inst/s)
-host_op_rate                                   954854                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1262227313                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 287296                       # Number of bytes of host memory used
-host_seconds                                   628.79                       # Real time elapsed on the host
+host_inst_rate                                 583678                       # Simulator instruction rate (inst/s)
+host_op_rate                                   616385                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              814802699                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241980                       # Number of bytes of host memory used
+host_seconds                                   974.06                       # Real time elapsed on the host
 sim_insts                                   568539335                       # Number of instructions simulated
 sim_ops                                     600398272                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             38592                       # Number of bytes read from this memory
@@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks            201031                       # To
 system.physmem.bw_total::cpu.inst               48625                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data             2110539                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                2360195                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                      2360195                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                4941                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4941                       # Transaction distribution
+system.membus.trans_dist::Writeback              2493                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             21835                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            21835                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side        56045                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count                         56045                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side      1873216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size                    1873216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                1873216                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            49213000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          240984000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                69093329                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         190459                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        190459                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       418626                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       247748                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       247748                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side         1286                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side      1293754                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count                  1295040                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        41152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side     54796160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size              54837312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          54837312                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      847042500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        964500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     656346000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------