diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/00.gzip/ref/sparc/linux | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/00.gzip/ref/sparc/linux')
6 files changed, 723 insertions, 724 deletions
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 6dd839e0e..3fe84dba1 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index b261460cd..476c2fbae 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:35 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:22 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 388554296500 because target called exit() +Exiting @ tick 387353399000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 042ffd7cf..aefb16cc5 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,174 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.388554 # Number of seconds simulated -sim_ticks 388554296500 # Number of ticks simulated -final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387353 # Number of seconds simulated +sim_ticks 387353399000 # Number of ticks simulated +final_tick 387353399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160259 # Simulator instruction rate (inst/s) -host_op_rate 160764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44440455 # Simulator tick rate (ticks/s) -host_mem_usage 224388 # Number of bytes of host memory used -host_seconds 8743.26 # Real time elapsed on the host +host_inst_rate 249730 # Simulator instruction rate (inst/s) +host_op_rate 250517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69036992 # Simulator tick rate (ticks/s) +host_mem_usage 223172 # Number of bytes of host memory used +host_seconds 5610.81 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 85056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5902400 # Number of bytes read from this memory -system.physmem.bytes_read::total 5987456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 85056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 85056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3788160 # Number of bytes written to this memory -system.physmem.bytes_written::total 3788160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1329 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 92225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 93554 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59190 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59190 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 218904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15190670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15409574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 218904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 218904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9749371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9749371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9749371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 218904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15190670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 25158945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1679296 # Number of bytes read from this memory +system.physmem.bytes_read::total 1758080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163648 # Number of bytes written to this memory +system.physmem.bytes_written::total 163648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26239 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27470 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2557 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2557 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 203390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4335307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4538698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 422477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 422477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 422477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4335307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4961175 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 777108594 # number of cpu cycles simulated +system.cpu.numCycles 774706799 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98192290 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88412741 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3784661 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66025458 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65664289 # Number of BTB hits +system.cpu.BPredUnit.lookups 98185703 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88410338 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3780922 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66067142 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65660680 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1392 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 307 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165888791 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648818264 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98192290 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65665681 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330417282 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21685615 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 262756820 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2717 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162823525 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 752138 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 776762747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.128564 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.147845 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1350 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 222 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165873006 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648740209 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98185703 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65662030 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330401804 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21677633 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 260655576 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 134 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2710 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162813671 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 754240 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774625436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.134374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150186 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 446345465 57.46% 57.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74375625 9.58% 67.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37980087 4.89% 71.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9083330 1.17% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28159964 3.63% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18826619 2.42% 79.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11515688 1.48% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3871202 0.50% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146604767 18.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 444223632 57.35% 57.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74371089 9.60% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37975725 4.90% 71.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9081691 1.17% 73.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28157593 3.63% 76.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18825345 2.43% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11518334 1.49% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3870567 0.50% 81.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146601460 18.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 776762747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126356 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.121735 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217443439 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 213446803 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285373546 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42801949 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17697010 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642584513 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17697010 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241484414 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36505924 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52170824 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303041095 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 125863480 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631270043 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30873302 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 72930971 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3136079 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360952247 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755876290 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2721902713 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33973577 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774625436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126739 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.128212 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217582243 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 211191171 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285367331 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42792485 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17692206 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642537043 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17692206 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241610870 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34893000 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 51906533 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303032306 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 125490521 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631238728 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 30863889 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 72608286 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3100712 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360952696 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755863339 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2721765470 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34097869 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116181795 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2680713 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2696169 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271856221 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438705092 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180250261 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255265663 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83296081 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517040384 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2636529 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460865188 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 67073 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113729678 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136677669 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 392858 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 776762747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.880710 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.430803 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116182244 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2679261 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2694678 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271420357 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438695813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180248477 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255317958 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83005231 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517026367 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2634412 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460842230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78451 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113716292 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136734652 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 390741 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774625436 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.885869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.429732 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147116911 18.94% 18.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184456460 23.75% 42.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210881862 27.15% 69.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131212379 16.89% 86.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70768732 9.11% 95.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20345025 2.62% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7834706 1.01% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3973798 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 172874 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145113160 18.73% 18.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184290714 23.79% 42.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210981910 27.24% 69.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131056815 16.92% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70797961 9.14% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20401058 2.63% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7831654 1.01% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3987119 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 165045 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 776762747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774625436 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 106719 6.05% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 167382 9.50% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1159607 65.79% 81.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 328958 18.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 85311 4.91% 4.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 160602 9.25% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1164457 67.05% 81.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326416 18.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867175983 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867158495 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2649316 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2649765 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -194,86 +193,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419771639 28.73% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171268250 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419768740 28.73% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171265230 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460865188 # Type of FU issued -system.cpu.iq.rate 1.879873 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1762666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3682454836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624473314 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444449939 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17868026 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9170759 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8547404 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453439561 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9188293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215395742 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460842230 # Type of FU issued +system.cpu.iq.rate 1.885671 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1736786 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001189 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3680238914 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624378157 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444420049 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17886219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9235235 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8548145 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453389871 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9189145 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215326368 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36192248 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54154 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 246172 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13402119 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36182969 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 244807 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13400335 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3683 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 46778 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3669 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 64278 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17697010 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2543877 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 131664 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613864484 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4125995 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438705092 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180250261 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2550339 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45235 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9141 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 246172 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2357197 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1561193 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3918390 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455317466 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417050361 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5547722 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17692206 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 786779 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 100697 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613841065 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4120499 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438695813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180248477 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2548675 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 22528 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11302 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 244807 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2356307 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1558704 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3915011 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455294659 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417049506 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5547571 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94187571 # number of nop insts executed -system.cpu.iew.exec_refs 587627055 # number of memory reference insts executed -system.cpu.iew.exec_branches 89112581 # Number of branches executed -system.cpu.iew.exec_stores 170576694 # Number of stores executed -system.cpu.iew.exec_rate 1.872734 # Inst execution rate -system.cpu.iew.wb_sent 1453915806 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452997343 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154378236 # num instructions producing a value -system.cpu.iew.wb_consumers 1205398776 # num instructions consuming a value +system.cpu.iew.exec_nop 94180286 # number of nop insts executed +system.cpu.iew.exec_refs 587622925 # number of memory reference insts executed +system.cpu.iew.exec_branches 89107301 # Number of branches executed +system.cpu.iew.exec_stores 170573419 # Number of stores executed +system.cpu.iew.exec_rate 1.878510 # Inst execution rate +system.cpu.iew.wb_sent 1453892295 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452968194 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154379658 # num instructions producing a value +system.cpu.iew.wb_consumers 1205415324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.869748 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957673 # average fanout of values written-back +system.cpu.iew.wb_rate 1.875507 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957661 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 124237250 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124212585 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3784661 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 759066348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.962310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504596 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3780922 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756933841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.967838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.506392 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240497837 31.68% 31.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276436046 36.42% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43137006 5.68% 73.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54981228 7.24% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19702278 2.60% 83.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13356697 1.76% 85.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30450827 4.01% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10463438 1.38% 90.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70040991 9.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 238474723 31.51% 31.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276385043 36.51% 68.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43107077 5.69% 73.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54927770 7.26% 80.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19677668 2.60% 83.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13341628 1.76% 85.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30470034 4.03% 89.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10497412 1.39% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70052486 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 759066348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756933841 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108101 # Number of instructions committed system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,70 +283,70 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70040991 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70052486 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2302721032 # The number of ROB reads -system.cpu.rob.rob_writes 3245242057 # The number of ROB writes -system.cpu.timesIdled 11126 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 345847 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2300552365 # The number of ROB reads +system.cpu.rob.rob_writes 3245186964 # The number of ROB writes +system.cpu.timesIdled 3424 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 81363 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188958 # Number of Instructions Simulated system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated -system.cpu.cpi 0.554607 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.554607 # CPI: Total CPI of All Threads -system.cpu.ipc 1.803080 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.803080 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980619731 # number of integer regfile reads -system.cpu.int_regfile_writes 1276281052 # number of integer regfile writes -system.cpu.fp_regfile_reads 16978878 # number of floating regfile reads -system.cpu.fp_regfile_writes 10499994 # number of floating regfile writes -system.cpu.misc_regfile_reads 593300909 # number of misc regfile reads +system.cpu.cpi 0.552892 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552892 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808670 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808670 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980590719 # number of integer regfile reads +system.cpu.int_regfile_writes 1276263729 # number of integer regfile writes +system.cpu.fp_regfile_reads 16980710 # number of floating regfile reads +system.cpu.fp_regfile_writes 10502370 # number of floating regfile writes +system.cpu.misc_regfile_reads 593296241 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 200 # number of replacements -system.cpu.icache.tagsinuse 1048.828471 # Cycle average of tags in use -system.cpu.icache.total_refs 162821549 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 120519.281273 # Average number of references to valid blocks. +system.cpu.icache.replacements 213 # number of replacements +system.cpu.icache.tagsinuse 1045.821443 # Cycle average of tags in use +system.cpu.icache.total_refs 162811755 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1361 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119626.565026 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1048.828471 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.512123 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.512123 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162821549 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162821549 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162821549 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162821549 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162821549 # number of overall hits -system.cpu.icache.overall_hits::total 162821549 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1976 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1976 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1976 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1976 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1976 # number of overall misses -system.cpu.icache.overall_misses::total 1976 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67232500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67232500 # 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Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.510655 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.510655 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162811755 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162811755 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162811755 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162811755 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162811755 # number of overall hits +system.cpu.icache.overall_hits::total 162811755 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1916 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1916 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1916 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1916 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1916 # number of overall misses +system.cpu.icache.overall_misses::total 1916 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62211500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62211500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62211500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62211500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62211500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62211500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162813671 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162813671 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162813671 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162813671 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162813671 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162813671 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34024.544534 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34024.544534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34024.544534 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32469.467641 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 32469.467641 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 32469.467641 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 32469.467641 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 32469.467641 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 32469.467641 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1352 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1352 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1352 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1352 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47023000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47023000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47023000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47023000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 554 # 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mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34780.325444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32186.490455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32186.490455 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32186.490455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32186.490455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32186.490455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32186.490455 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 458031 # number of replacements -system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use -system.cpu.dcache.total_refs 365778673 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 462127 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 791.511150 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 131565000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.115790 # Average occupied blocks per requestor +system.cpu.dcache.replacements 458023 # number of replacements +system.cpu.dcache.tagsinuse 4095.115270 # Cycle average of tags in use +system.cpu.dcache.total_refs 365885511 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 462119 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.756043 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 131340000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.115270 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200803152 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200803152 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164974202 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164974202 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200904892 # 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number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365884192 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365884192 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365884192 # number of overall hits +system.cpu.dcache.overall_hits::total 365884192 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 767087 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 767087 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1867516 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1867516 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2675956 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2675956 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2675956 # 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number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28284531832 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28284531832 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28284531832 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28284531832 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201671979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201671979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368453310 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368453310 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003985 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011224 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368518795 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368518795 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368518795 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368518795 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003804 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011193 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011193 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007263 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007263 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.703875 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15844.705290 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 38142.857143 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15529.487014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15529.487014 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007149 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007149 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6625.936823 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6625.936823 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12423.915957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12423.915957 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9857.142857 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 9857.142857 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10735.785176 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10735.785176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10735.785176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10735.785176 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks -system.cpu.dcache.writebacks::total 413195 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603294 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 603294 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1610542 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1610542 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2213836 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2213836 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2213836 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2213836 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200048 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200048 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262072 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3602715222 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 246000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 246000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5156941222 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 462112 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 462112 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 462112 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 462112 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 667617500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 667617500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2577100353 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2577100353 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 48000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 48000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3244717853 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3244717853 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3244717853 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3244717853 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses @@ -504,100 +503,100 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7769.265376 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13747.043644 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 35142.857143 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3336.952936 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3336.952936 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9834.609276 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 442952 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 442952 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 262052 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 262052 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1362 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 462119 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 463481 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1362 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 462119 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 463481 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.903818 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022188 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.028149 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083190 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083190 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.903818 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056780 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059269 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.903818 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056780 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059269 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34233.956133 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34035.143050 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34078.306878 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34344.816514 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34344.816514 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34233.956133 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.427303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34289.807062 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34233.956133 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.427303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34289.807062 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,52 +605,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59190 # number of writebacks -system.cpu.l2cache.writebacks::total 59190 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1329 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32167 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33496 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60058 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60058 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 92225 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 93554 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1329 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 92225 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 93554 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41203500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 997353500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1038557000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1880936000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1880936000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41203500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2878289500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2919493000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41203500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.229160 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.403630 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31318.658630 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2557 # number of writebacks +system.cpu.l2cache.writebacks::total 2557 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1231 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5670 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21800 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21800 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26239 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27470 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1231 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26239 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27470 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38155500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 137662500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175818000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 681082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 681082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38155500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 818744500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 856900000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38155500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 818744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 856900000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022188 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028149 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083190 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083190 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059269 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30995.532088 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31012.052264 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31008.465608 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31242.293578 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31242.293578 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30995.532088 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31203.342353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31194.029851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30995.532088 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31203.342353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31194.029851 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index 577b4c1d7..e273f1b51 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index 4517a277e..a6ed8a59a 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:45 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:27 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2064258667000 because target called exit() +Exiting @ tick 2061521023000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 0ce23ef70..921624c02 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.064259 # Number of seconds simulated -sim_ticks 2064258667000 # Number of ticks simulated -final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.061521 # Number of seconds simulated +sim_ticks 2061521023000 # Number of ticks simulated +final_tick 2061521023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1371910 # Simulator instruction rate (inst/s) -host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1906915769 # Simulator tick rate (ticks/s) -host_mem_usage 223048 # Number of bytes of host memory used -host_seconds 1082.51 # Real time elapsed on the host +host_inst_rate 2065708 # Simulator instruction rate (inst/s) +host_op_rate 2071849 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2867468443 # Simulator tick rate (ticks/s) +host_mem_usage 221124 # Number of bytes of host memory used +host_seconds 718.93 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory -system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory -system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory +system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 161472 # Number of bytes written to this memory +system.physmem.bytes_written::total 161472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1027 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 31883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 843214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 31883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 31883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 31883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 921541 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4128517334 # number of cpu cycles simulated +system.cpu.numCycles 4123042046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1485108101 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 569365767 # nu system.cpu.num_load_insts 402515346 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4128517334 # Number of busy cycles +system.cpu.num_busy_cycles 4123042046 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.456939 # Cycle average of tags in use system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.442603 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.442603 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 906.456939 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.442606 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.442606 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses system.cpu.icache.overall_misses::total 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61824000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61824000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58632000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58632000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58632000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58632000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58632000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58632000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52964.769648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52964.769648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52964.769648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52964.769648 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107 system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55311000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 55311000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55311000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 55311000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55311000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 55311000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49964.769648 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49964.769648 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.226004 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.226955 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 566952000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.226004 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 453214 # n system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses system.cpu.dcache.overall_misses::total 453214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4019834000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4019834000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6156948000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6156948000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 392000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 392000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10176782000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10176782000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10176782000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10176782000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888312000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2888312000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554270000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4554270000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7442582000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7442582000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7442582000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7442582000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14927.757047 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14927.757047 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17534.767141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17534.767141 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16421.783087 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks -system.cpu.dcache.writebacks::total 407009 # number of writebacks +system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks +system.cpu.dcache.writebacks::total 435341 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 453214 system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3439376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3439376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5377764000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5377764000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 371000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 371000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8817140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses @@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74112 # number of replacements -system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use -system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2614 # number of replacements +system.cpu.l2cache.tagsinuse 22186.870278 # Cycle average of tags in use +system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 72.801131 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.002222 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.540872 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 162271 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 162275 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 407009 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 407009 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199710 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199710 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 361981 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 361985 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 361981 # number of overall hits -system.cpu.l2cache.overall_hits::total 361985 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1103 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 31215 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32318 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 60025 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 60025 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1103 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92343 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1103 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses -system.cpu.l2cache.overall_misses::total 92343 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57356000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1623180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1680536000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3121300000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3121300000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57356000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4744480000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 4801836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57356000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4744480000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4801836000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 20830.127393 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 857.488075 # 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