diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/00.gzip/ref/sparc/linux | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/00.gzip/ref/sparc/linux')
9 files changed, 603 insertions, 405 deletions
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index dcba73ec2..5612e55e7 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index a835cbd79..337dcecf7 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:17:40 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:56:12 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index e4d9fca07..3c7a99cbd 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.408816 # Nu sim_ticks 408816360000 # Number of ticks simulated final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175830 # Simulator instruction rate (inst/s) -host_tick_rate 51139829 # Simulator tick rate (ticks/s) -host_mem_usage 215728 # Number of bytes of host memory used -host_seconds 7994.10 # Real time elapsed on the host -sim_insts 1405604152 # Number of instructions simulated +host_inst_rate 218783 # Simulator instruction rate (inst/s) +host_op_rate 219472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63832966 # Simulator tick rate (ticks/s) +host_mem_usage 214000 # Number of bytes of host memory used +host_seconds 6404.47 # Real time elapsed on the host +sim_insts 1401188958 # Number of instructions simulated +sim_ops 1405604152 # Number of ops (including micro ops) simulated system.physmem.bytes_read 6021376 # Number of bytes read from this memory system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory system.physmem.bytes_written 3792448 # Number of bytes written to this memory @@ -237,7 +239,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.812578 # insts written-back per cycle system.cpu.iew.wb_fanout 0.959383 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions system.cpu.commit.commitSquashedInsts 179255835 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 5438120 # The number of times a branch was mispredicted @@ -258,7 +261,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 791834306 # Number of insts commited each cycle -system.cpu.commit.count 1489523295 # Number of instructions committed +system.cpu.commit.committedInsts 1485108101 # Number of instructions committed +system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 569360986 # Number of memory references committed system.cpu.commit.loads 402512844 # Number of loads committed @@ -273,12 +277,13 @@ system.cpu.rob.rob_reads 2392297077 # Th system.cpu.rob.rob_writes 3363039880 # The number of ROB writes system.cpu.timesIdled 11286 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 357787 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1405604152 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.581695 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.581695 # CPI: Total CPI of All Threads -system.cpu.ipc 1.719114 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.719114 # IPC: Total IPC of All Threads +system.cpu.committedInsts 1401188958 # Number of Instructions Simulated +system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated +system.cpu.cpi 0.583528 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.583528 # CPI: Total CPI of All Threads +system.cpu.ipc 1.713714 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.713714 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 2016058791 # number of integer regfile reads system.cpu.int_regfile_writes 1303867666 # number of integer regfile writes system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads @@ -291,26 +296,39 @@ system.cpu.icache.total_refs 170772098 # To system.cpu.icache.sampled_refs 1298 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 131565.560863 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1031.400456 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.503614 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 170772098 # number of ReadReq hits -system.cpu.icache.demand_hits 170772098 # number of demand (read+write) hits -system.cpu.icache.overall_hits 170772098 # number of overall hits -system.cpu.icache.ReadReq_misses 1798 # number of ReadReq misses -system.cpu.icache.demand_misses 1798 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1798 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 62741500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 62741500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 62741500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 170773896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 170773896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 170773896 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000011 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000011 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000011 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34895.161290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34895.161290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34895.161290 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1031.400456 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.503614 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.503614 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 170772098 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170772098 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170772098 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170772098 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170772098 # number of overall hits +system.cpu.icache.overall_hits::total 170772098 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1798 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1798 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1798 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1798 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1798 # number of overall misses +system.cpu.icache.overall_misses::total 1798 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62741500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62741500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62741500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62741500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62741500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62741500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170773896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170773896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170773896 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170773896 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170773896 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170773896 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34895.161290 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,27 +337,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 499 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 499 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 499 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45206000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45206000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45206000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34800.615858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 499 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 499 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 499 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 499 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 499 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 499 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1299 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1299 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1299 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1299 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1299 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1299 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45206000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45206000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45206000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45206000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45206000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45206000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34800.615858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 475353 # number of replacements system.cpu.dcache.tagsinuse 4095.165283 # Cycle average of tags in use @@ -347,38 +368,59 @@ system.cpu.dcache.total_refs 385593109 # To system.cpu.dcache.sampled_refs 479449 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 804.242180 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.165283 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 220654856 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 164936934 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 385591790 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 385591790 # number of overall hits -system.cpu.dcache.ReadReq_misses 815916 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1909882 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 2725798 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2725798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11966603000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 29861651909 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 268000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 41828254909 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 41828254909 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 221470772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 388317588 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 388317588 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003684 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.011447 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.007020 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.007020 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14666.464440 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15635.338680 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15345.324528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15345.324528 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4095.165283 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999796 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999796 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 220654856 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 220654856 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164936934 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164936934 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 385591790 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 385591790 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 385591790 # number of overall hits +system.cpu.dcache.overall_hits::total 385591790 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 815916 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 815916 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1909882 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1909882 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 2725798 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2725798 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2725798 # number of overall misses +system.cpu.dcache.overall_misses::total 2725798 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11966603000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11966603000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29861651909 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29861651909 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 268000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 268000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41828254909 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41828254909 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41828254909 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41828254909 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 221470772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 221470772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 388317588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 388317588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 388317588 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 388317588 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003684 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011447 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007020 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007020 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14666.464440 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15635.338680 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38285.714286 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -387,36 +429,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2153.846154 system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 426654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 603731 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1642625 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2246356 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2246356 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 212185 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 267257 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 479442 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 479442 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1589383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3625603341 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5214986841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5214986841 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000958 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001602 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001235 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001235 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7490.555412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13565.980839 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 426654 # number of writebacks +system.cpu.dcache.writebacks::total 426654 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603731 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 603731 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642625 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2246356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2246356 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2246356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2246356 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 212185 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 212185 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 267257 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 267257 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 479442 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 479442 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 479442 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 479442 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1589383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1589383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3625603341 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3625603341 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 247000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 247000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5214986841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5214986841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5214986841 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5214986841 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000958 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7490.555412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13565.980839 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35285.714286 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 75859 # number of replacements system.cpu.l2cache.tagsinuse 17814.801426 # Cycle average of tags in use @@ -424,36 +476,75 @@ system.cpu.l2cache.total_refs 464590 # To system.cpu.l2cache.sampled_refs 91380 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 5.084154 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2079.678027 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15735.123399 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.063467 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.480198 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 179822 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 426654 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 206842 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 386664 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 386664 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33662 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60422 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 94084 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 94084 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1145731000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2079178500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3224909500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3224909500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 213484 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 426654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 267264 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 480748 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 480748 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.157679 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.226076 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.195703 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.195703 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34036.331769 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.951309 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34276.917435 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34276.917435 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15735.123399 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 94.212469 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1985.465558 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.480198 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.002875 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.060592 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.543665 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 179801 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 179822 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 426654 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 426654 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 206842 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 206842 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 386643 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 386664 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 386643 # number of overall hits +system.cpu.l2cache.overall_hits::total 386664 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1278 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32384 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33662 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 60422 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 60422 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1278 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 92806 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 94084 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1278 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 92806 # number of overall misses +system.cpu.l2cache.overall_misses::total 94084 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 43747500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101983500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1145731000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079178500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2079178500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 43747500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3181162000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 3224909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 43747500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3181162000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3224909500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1299 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 212185 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 213484 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 426654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 426654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 267264 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 267264 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1299 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 479449 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 480748 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1299 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 479449 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 480748 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983834 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.152622 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.226076 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983834 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.193568 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983834 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.193568 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34231.220657 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34028.640687 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34410.951309 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,30 +553,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59257 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33662 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60422 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 94084 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 94084 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1043686000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2935836500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2935836500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157679 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226076 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.195703 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.195703 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871962 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.588693 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59257 # number of writebacks +system.cpu.l2cache.writebacks::total 59257 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1278 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32384 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33662 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60422 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60422 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 92806 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 94084 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 92806 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 94084 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39610000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1004076000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1043686000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1892150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1892150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39610000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2896226500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2935836500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39610000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2896226500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2935836500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.152622 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.226076 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30993.740219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.311265 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.588693 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini index b52495d06..12208533c 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout index d2df5cc09..dd6f18f54 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:18:03 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:56:17 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index afe2bae4f..317e75938 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.744764 # Nu sim_ticks 744764119000 # Number of ticks simulated final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3773289 # Simulator instruction rate (inst/s) -host_tick_rate 1886650577 # Simulator tick rate (ticks/s) -host_mem_usage 205844 # Number of bytes of host memory used -host_seconds 394.75 # Real time elapsed on the host -sim_insts 1489523295 # Number of instructions simulated +host_inst_rate 4631105 # Simulator instruction rate (inst/s) +host_op_rate 4644873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2322443893 # Simulator tick rate (ticks/s) +host_mem_usage 203508 # Number of bytes of host memory used +host_seconds 320.68 # Real time elapsed on the host +sim_insts 1485108101 # Number of instructions simulated +sim_ops 1489523295 # Number of ops (including micro ops) simulated system.physmem.bytes_read 7326269637 # Number of bytes read from this memory system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory system.physmem.bytes_written 614672063 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 49 # Nu system.cpu.numCycles 1489528239 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.committedInsts 1485108101 # Number of instructions committed +system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses system.cpu.num_func_calls 1207835 # number of times a function call or return occured diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index ea98a23a1..8f915a65c 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index b26fb3f41..31dd55bac 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:19:05 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:56:19 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 059312926..91253ef89 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.064259 # Nu sim_ticks 2064258667000 # Number of ticks simulated final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1766930 # Simulator instruction rate (inst/s) -host_tick_rate 2448703239 # Simulator tick rate (ticks/s) -host_mem_usage 214556 # Number of bytes of host memory used -host_seconds 843.00 # Real time elapsed on the host -sim_insts 1489523295 # Number of instructions simulated +host_inst_rate 2132645 # Simulator instruction rate (inst/s) +host_op_rate 2138986 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2964317062 # Simulator tick rate (ticks/s) +host_mem_usage 212372 # Number of bytes of host memory used +host_seconds 696.37 # Real time elapsed on the host +sim_insts 1485108101 # Number of instructions simulated +sim_ops 1489523295 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5909952 # Number of bytes read from this memory system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory system.physmem.bytes_written 3778240 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 49 # Nu system.cpu.numCycles 4128517334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.committedInsts 1485108101 # Number of instructions committed +system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses system.cpu.num_func_calls 1207835 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 1485111905 # To system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.442603 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits -system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1485111905 # number of overall hits -system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses -system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.442603 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.442603 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1485111905 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1485111905 # number of overall hits +system.cpu.icache.overall_hits::total 1485111905 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses +system.cpu.icache.overall_misses::total 1107 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61824000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61824000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61824000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61824000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61824000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61824000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1485113012 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1107 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1107 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 58503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 58503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use @@ -102,38 +116,59 @@ system.cpu.dcache.total_refs 568907765 # To system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999811 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 166587088 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 568906446 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 568906446 # number of overall hits -system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 259728 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 453214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 453214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4019834000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 6156948000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 392000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 10176782000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 10176782000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22454.694692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4095.226955 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 568906446 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 568906446 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 568906446 # number of overall hits +system.cpu.dcache.overall_hits::total 568906446 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses +system.cpu.dcache.overall_misses::total 453214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4019834000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4019834000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6156948000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6156948000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 392000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 392000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10176782000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10176782000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10176782000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10176782000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 569359660 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 569359660 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 407009 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 259728 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 453214 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 453214 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3439376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5377764000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 371000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8817140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8817140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks +system.cpu.dcache.writebacks::total 407009 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3439376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3439376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5377764000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5377764000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 371000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 371000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8817140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74112 # number of replacements system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use @@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs 427085 # To system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057187 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.483685 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 162275 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 407009 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 199710 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 361985 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 361985 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32318 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60025 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92343 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92343 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1680536000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3121300000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4801836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4801836000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 407009 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.166080 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.231101 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.203252 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.203252 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 72.801131 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.002222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.540872 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 4 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 162271 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 162275 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 407009 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 407009 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 199710 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 199710 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 361981 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 361985 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 361981 # number of overall hits +system.cpu.l2cache.overall_hits::total 361985 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1103 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 31215 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 32318 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 60025 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 60025 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1103 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 92343 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1103 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses +system.cpu.l2cache.overall_misses::total 92343 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1623180000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1680536000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3121300000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3121300000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4744480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4801836000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4744480000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4801836000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 407009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 407009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 453221 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 454328 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59035 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32318 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60025 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92343 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1292720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2401000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3693720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3693720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166080 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.231101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.203252 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.203252 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks +system.cpu.l2cache.writebacks::total 59035 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1103 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32318 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60025 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60025 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1103 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92343 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1103 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92343 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1248600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1292720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2401000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2401000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3693720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |