diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt | 1245 |
1 files changed, 678 insertions, 567 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index b2e32248a..29e9634dd 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.602332 # Number of seconds simulated -sim_ticks 602332345500 # Number of ticks simulated -final_tick 602332345500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.602519 # Number of seconds simulated +sim_ticks 602519213000 # Number of ticks simulated +final_tick 602519213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59375 # Simulator instruction rate (inst/s) -host_op_rate 109402 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40639301 # Simulator tick rate (ticks/s) -host_mem_usage 298404 # Number of bytes of host memory used -host_seconds 14821.42 # Real time elapsed on the host +host_inst_rate 94132 # Simulator instruction rate (inst/s) +host_op_rate 173444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64448799 # Simulator tick rate (ticks/s) +host_mem_usage 251596 # Number of bytes of host memory used +host_seconds 9348.80 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493927 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 57280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 57152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory system.physmem.bytes_read::total 1750464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 57280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 57280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162240 # Number of bytes written to this memory -system.physmem.bytes_written::total 162240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 57152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory +system.physmem.bytes_written::total 162112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 893 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory system.physmem.num_reads::total 27351 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2535 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2535 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2811046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2906143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 269353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 269353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 269353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2811046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3175496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2810387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2905242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 269057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 269057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 269057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2810387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3174299 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 27351 # Total number of read requests seen -system.physmem.writeReqs 2535 # Total number of write requests seen -system.physmem.cpureqs 29886 # Reqs generatd by CPU via cache - shady +system.physmem.writeReqs 2533 # Total number of write requests seen +system.physmem.cpureqs 29884 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 1750464 # Total number of bytes read from memory -system.physmem.bytesWritten 162240 # Total number of bytes written to memory +system.physmem.bytesWritten 162112 # Total number of bytes written to memory system.physmem.bytesConsumedRd 1750464 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162240 # bytesWritten derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1659 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1742 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1729 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1565 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1748 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1766 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1802 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1763 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1630 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 168 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 602332206500 # Total gap between requests +system.physmem.totGap 602519006000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -91,13 +91,13 @@ system.physmem.writePktSize::2 0 # Ca system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2535 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 26932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2533 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 26975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -127,8 +127,8 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see @@ -156,14 +156,82 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 88037750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 893262750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 9709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 196.647235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 83.287733 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 790.384353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 8486 87.40% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 125 1.29% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 100 1.03% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 90 0.93% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 83 0.85% 91.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 70 0.72% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 47 0.48% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 479 4.93% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 8 0.08% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3 0.03% 97.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.04% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2 0.02% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.05% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 2 0.02% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 8 0.08% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.03% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 9 0.09% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.05% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.02% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.04% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.04% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.03% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 4 0.04% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.01% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.01% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 5 0.05% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 7 0.07% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.02% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 4 0.04% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 9 0.09% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 13 0.13% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.03% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.05% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 4 0.04% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.05% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 4 0.04% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.02% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 60 0.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 9709 # Bytes accessed per row activation +system.physmem.totQLat 62966000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 815954750 # Sum of mem lat for all requests system.physmem.totBusLat 136755000 # Total cycles spent in databus access -system.physmem.totBankLat 668470000 # Total cycles spent in bank access -system.physmem.avgQLat 3218.81 # Average queueing delay per request -system.physmem.avgBankLat 24440.42 # Average bank access latency per request +system.physmem.totBankLat 616233750 # Total cycles spent in bank access +system.physmem.avgQLat 2302.15 # Average queueing delay per request +system.physmem.avgBankLat 22530.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32659.24 # Average memory access latency +system.physmem.avgMemAccLat 29832.72 # Average memory access latency system.physmem.avgRdBW 2.91 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.91 # Average consumed read bandwidth in MB/s @@ -171,146 +239,167 @@ system.physmem.avgConsumedWrBW 0.27 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.01 # Average write queue length over time -system.physmem.readRowHits 16404 # Number of row buffer hits during reads -system.physmem.writeRowHits 1020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 59.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.24 # Row buffer hit rate for writes -system.physmem.avgGap 20154326.66 # Average gap between requests -system.cpu.branchPred.lookups 155894666 # Number of BP lookups -system.cpu.branchPred.condPredicted 155894666 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25699129 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80742532 # Number of BTB lookups -system.cpu.branchPred.BTBHits 80542859 # Number of BTB hits +system.physmem.avgWrQLen 7.81 # Average write queue length over time +system.physmem.readRowHits 18284 # Number of row buffer hits during reads +system.physmem.writeRowHits 1888 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.54 # Row buffer hit rate for writes +system.physmem.avgGap 20161926.32 # Average gap between requests +system.membus.throughput 3174299 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5448 # Transaction distribution +system.membus.trans_dist::ReadResp 5448 # Transaction distribution +system.membus.trans_dist::Writeback 2533 # Transaction distribution +system.membus.trans_dist::ReadExReq 21903 # Transaction distribution +system.membus.trans_dist::ReadExResp 21903 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 57235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 57235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 57235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 57235 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1912576 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 54010000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 256633000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 156229699 # Number of BP lookups +system.cpu.branchPred.condPredicted 156229699 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25700090 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80130735 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79954590 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.752704 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 2586842 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5513 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.780178 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 2760708 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5575 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1204664695 # number of cpu cycles simulated +system.cpu.numCycles 1205038430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175314236 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1434822441 # Number of instructions fetch has processed -system.cpu.fetch.Branches 155894666 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83129701 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 393116244 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83893731 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 577823849 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 123 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 791 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 184597714 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11658023 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1204295068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.043367 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.243240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175276442 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1436709759 # Number of instructions fetch has processed +system.cpu.fetch.Branches 156229699 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 82715298 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 393071073 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83888584 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 578277772 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 906 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 184712777 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11835246 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1204659879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.045547 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.246119 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 818096949 67.93% 67.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26918487 2.24% 70.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 12895052 1.07% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20223867 1.68% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26382325 2.19% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18061341 1.50% 76.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31920988 2.65% 79.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 38294164 3.18% 82.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 211501895 17.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 818506882 67.95% 67.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26870857 2.23% 70.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 12535228 1.04% 71.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20195142 1.68% 72.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26380482 2.19% 75.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18063889 1.50% 76.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31357703 2.60% 79.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 38322925 3.18% 82.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212426771 17.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1204295068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129409 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.191055 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 284492311 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 500325603 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 268669661 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92767668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 58039825 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2310318754 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 58039825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 333414311 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124348906 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3625 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 298566996 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 389921405 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2218156227 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 243059098 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 121762189 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2583430749 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5648758417 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5648752173 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6244 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1204659879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129647 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.192252 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 284492310 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 500755512 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 268717714 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92660799 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 58033544 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2310812595 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 58033544 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 333444734 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124733131 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3847 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 298470128 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 389974495 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2217748571 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12521 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 243097280 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 121807098 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2582807342 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5647663149 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5647656949 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6200 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 696535489 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 103 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 737453259 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 525280959 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 216617119 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 339037703 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144743699 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1968663502 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 332 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1774132594 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 144752 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 346851970 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 707722705 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1204295068 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.473171 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.418728 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 695912082 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 105 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 105 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 737293343 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 525275195 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 216586351 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 339249104 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144696192 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1968455796 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 343 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1773948225 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 152074 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 346640912 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 707550278 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 294 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1204659879 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.472572 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.418644 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 354010440 29.40% 29.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 362491598 30.10% 59.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234089313 19.44% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 140647652 11.68% 90.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60236623 5.00% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39446291 3.28% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10873538 0.90% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1896665 0.16% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 602948 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 354366536 29.42% 29.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 362605011 30.10% 59.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234071294 19.43% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 140518579 11.66% 90.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60300441 5.01% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39440661 3.27% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10869049 0.90% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1880938 0.16% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 607370 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1204295068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1204659879 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 400252 14.21% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2198563 78.06% 92.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 217598 7.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 405736 14.35% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2202072 77.90% 92.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 219007 7.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812295 2.64% 2.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1058825283 59.68% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 18980 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 398 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812378 2.64% 2.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1058677272 59.68% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 18975 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 392 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.32% # Type of FU issued @@ -337,84 +426,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 476287231 26.85% 89.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192188407 10.83% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 476256932 26.85% 89.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192182276 10.83% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1774132594 # Type of FU issued -system.cpu.iq.rate 1.472719 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2816413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001587 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4755521042 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2315690389 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1716753140 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 379 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1840 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1730136533 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 179 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210301951 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1773948225 # Type of FU issued +system.cpu.iq.rate 1.472109 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2826815 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001594 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4755534756 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2315271702 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1716628380 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 462 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1729962441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210357388 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 106238837 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 40588 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180694 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 28431061 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 106233073 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38741 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 180751 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 28400293 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2329 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2345 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 48 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 58039825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1222123 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 102210 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1968663834 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63066910 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 525280959 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 216617119 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49147 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2813 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180694 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1387767 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24439207 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25826974 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1757694663 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 472697091 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 16437931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 58033544 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1572366 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 106573 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1968456139 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63007739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 525275195 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 216586351 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 94 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49655 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2783 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 180751 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1386811 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24440636 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25827447 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1757502391 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 472605363 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 16445834 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 664152329 # number of memory reference insts executed -system.cpu.iew.exec_branches 110147604 # Number of branches executed -system.cpu.iew.exec_stores 191455238 # Number of stores executed -system.cpu.iew.exec_rate 1.459074 # Inst execution rate -system.cpu.iew.wb_sent 1717478326 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1716753232 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1259860051 # num instructions producing a value -system.cpu.iew.wb_consumers 1819503625 # num instructions consuming a value +system.cpu.iew.exec_refs 664057082 # number of memory reference insts executed +system.cpu.iew.exec_branches 110136743 # Number of branches executed +system.cpu.iew.exec_stores 191451719 # Number of stores executed +system.cpu.iew.exec_rate 1.458462 # Inst execution rate +system.cpu.iew.wb_sent 1717351615 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1716628496 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1259714523 # num instructions producing a value +system.cpu.iew.wb_consumers 1819339484 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.425088 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692420 # average fanout of values written-back +system.cpu.iew.wb_rate 1.424543 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 347171319 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 346963425 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25699242 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1146255243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.414601 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.834752 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25700222 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1146626335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.414143 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.834829 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 413178457 36.05% 36.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 412793718 36.01% 72.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87651437 7.65% 79.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122127525 10.65% 90.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23936453 2.09% 92.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25493357 2.22% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16343741 1.43% 96.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12104723 1.06% 97.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32625832 2.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 413585484 36.07% 36.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 412792006 36.00% 72.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87637452 7.64% 79.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122098814 10.65% 90.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23946599 2.09% 92.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25447448 2.22% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16362955 1.43% 96.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12115407 1.06% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32640170 2.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1146255243 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1146626335 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -425,195 +514,217 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions. system.cpu.commit.function_calls 1061692 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32625832 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32640170 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3082294657 # The number of ROB reads -system.cpu.rob.rob_writes 3995391584 # The number of ROB writes -system.cpu.timesIdled 60284 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 369627 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3082443517 # The number of ROB reads +system.cpu.rob.rob_writes 3994969913 # The number of ROB writes +system.cpu.timesIdled 60378 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 378551 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.368898 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.368898 # CPI: Total CPI of All Threads -system.cpu.ipc 0.730515 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.730515 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3534938952 # number of integer regfile reads -system.cpu.int_regfile_writes 1966276795 # number of integer regfile writes -system.cpu.fp_regfile_reads 92 # number of floating regfile reads -system.cpu.misc_regfile_reads 906122047 # number of misc regfile reads +system.cpu.cpi 1.369323 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.369323 # CPI: Total CPI of All Threads +system.cpu.ipc 0.730288 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.730288 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3534639638 # number of integer regfile reads +system.cpu.int_regfile_writes 1966129317 # number of integer regfile writes +system.cpu.fp_regfile_reads 116 # number of floating regfile reads +system.cpu.misc_regfile_reads 905981948 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.tagsinuse 799.517991 # Cycle average of tags in use -system.cpu.icache.total_refs 184596362 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 200866.552775 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 93457946 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 204658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 204658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 428893 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246296 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1328951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1330805 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56250752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 56309952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56309952 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 868818500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1393500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 675040498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.icache.replacements 41 # number of replacements +system.cpu.icache.tagsinuse 797.090296 # Cycle average of tags in use +system.cpu.icache.total_refs 184711350 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 199687.945946 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 799.517991 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.390390 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.390390 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 184596362 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 184596362 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 184596362 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 184596362 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 184596362 # number of overall hits -system.cpu.icache.overall_hits::total 184596362 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1352 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1352 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1352 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1352 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1352 # number of overall misses -system.cpu.icache.overall_misses::total 1352 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65001000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65001000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65001000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65001000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65001000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65001000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 184597714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 184597714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 184597714 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 184597714 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 184597714 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 184597714 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48077.662722 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48077.662722 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48077.662722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48077.662722 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 797.090296 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.389204 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.389204 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 184711350 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 184711350 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 184711350 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 184711350 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 184711350 # number of overall hits +system.cpu.icache.overall_hits::total 184711350 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1427 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1427 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1427 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1427 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1427 # number of overall misses +system.cpu.icache.overall_misses::total 1427 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 89875000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 89875000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 89875000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 89875000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 89875000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 89875000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 184712777 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 184712777 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 184712777 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 184712777 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 184712777 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 184712777 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000008 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000008 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000008 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000008 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000008 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000008 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62981.779958 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62981.779958 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62981.779958 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62981.779958 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62981.779958 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62981.779958 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 295 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.250000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 73.750000 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.026621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088930 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.088930 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965405 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058792 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060652 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965405 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058792 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060652 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68823.628219 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 90366.410538 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -622,144 +733,144 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2535 # number of writebacks -system.cpu.l2cache.writebacks::total 2535 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 895 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4556 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5451 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21900 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21900 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 895 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74169.970631 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56350.865178 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56350.865178 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56406.215006 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60018.151410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59900.223027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56406.215006 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60018.151410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59900.223027 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 450025 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 999.884735 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 960887000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.296880 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999096 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999096 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 262033427 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 262033427 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939697 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939697 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 449973124 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 449973124 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 450577836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 450577836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 450430683 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 450430683 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 450430683 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 450430683 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000805 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000805 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001016 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.001016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14304.482843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14304.482843 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16702.214741 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16702.214741 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15594.973785 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15594.973785 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14697.916173 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14697.916173 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18214.973149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18214.973149 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16591.586003 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16591.586003 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.586003 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16591.586003 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.953488 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.702703 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 429005 # number of writebacks -system.cpu.dcache.writebacks::total 429005 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7496 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7496 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 71 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 71 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7567 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7567 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7567 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7567 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203910 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203910 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246323 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450233 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450233 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450233 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450233 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2529393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2529393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3622096999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3622096999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6151489999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6151489999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6151489999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6151489999 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 428893 # number of writebacks +system.cpu.dcache.writebacks::total 428893 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7460 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7460 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 70 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 70 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7530 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7530 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7530 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7530 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203738 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203738 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246291 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246291 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450029 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450029 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450029 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450029 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2608561002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2608561002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3994205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3994205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6602766502 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6602766502 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6602766502 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6602766502 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000777 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000777 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -768,14 +879,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000999 system.cpu.dcache.demand_mshr_miss_rate::total 0.000999 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000999 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12404.457849 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12404.457849 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14704.664197 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14704.664197 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12803.507456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12803.507456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16217.423698 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16217.423698 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |