diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
| commit | 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch) | |
| tree | 64b85031cb791a21af6059778384d358d992b817 /tests/long/se/00.gzip/ref/x86/linux | |
| parent | dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff) | |
| download | gem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz | |
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/00.gzip/ref/x86/linux')
9 files changed, 171 insertions, 166 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 0e20d1517..96720c6a8 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -31,22 +31,18 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -69,23 +65,15 @@ forwardComSize=5 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -97,7 +85,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -126,6 +113,24 @@ workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -514,7 +519,7 @@ egid=100 env= errout=cerr euid=100 -executable=/gem5/dist/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index c000af4ff..a29e79bee 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 4 2013 21:20:54 -gem5 started Jan 4 2013 22:11:32 -gem5 executing on u200540 +gem5 compiled Jan 23 2013 16:30:44 +gem5 started Jan 23 2013 18:48:34 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 6e46a8347..3548dbe1a 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.607446 # Nu sim_ticks 607445544000 # Number of ticks simulated final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35384 # Simulator instruction rate (inst/s) -host_op_rate 65197 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24424271 # Simulator tick rate (ticks/s) -host_mem_usage 239876 # Number of bytes of host memory used -host_seconds 24870.57 # Real time elapsed on the host +host_inst_rate 56942 # Simulator instruction rate (inst/s) +host_op_rate 104918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39304494 # Simulator tick rate (ticks/s) +host_mem_usage 295872 # Number of bytes of host memory used +host_seconds 15454.86 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory @@ -192,18 +192,19 @@ system.physmem.writeRowHits 1084 # Nu system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes system.physmem.avgGap 20320661.36 # Average gap between requests +system.cpu.branchPred.lookups 158385701 # Number of BP lookups +system.cpu.branchPred.condPredicted 158385701 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 26390414 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 84292336 # Number of BTB lookups +system.cpu.branchPred.BTBHits 84079165 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.747105 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1214891089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 158385701 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 158385701 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26390414 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84292336 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 84079165 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini index 6f8b69a5a..8a8a24651 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,11 +31,11 @@ system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts itb tracer workload +children=dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -43,6 +44,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -53,6 +55,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu.tracer width=1 @@ -83,6 +86,9 @@ int_master=system.membus.slave[5] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index c175f0374..6792b9773 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 00:35:29 +gem5 compiled Jan 23 2013 16:30:44 +gem5 started Jan 23 2013 18:52:14 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 5647e6e6c..a1cb93ee9 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.963993 # Nu sim_ticks 963992671500 # Number of ticks simulated final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 908989 # Simulator instruction rate (inst/s) -host_op_rate 1674860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 995719480 # Simulator tick rate (ticks/s) -host_mem_usage 267620 # Number of bytes of host memory used -host_seconds 968.14 # Real time elapsed on the host +host_inst_rate 911190 # Simulator instruction rate (inst/s) +host_op_rate 1678916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 998130396 # Simulator tick rate (ticks/s) +host_mem_usage 284224 # Number of bytes of host memory used +host_seconds 965.80 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493927 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 156174801..5736b9341 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,11 +31,11 @@ system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -42,6 +43,7 @@ dtb=system.cpu.dtb function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -50,6 +52,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -63,21 +66,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -102,21 +100,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -133,6 +126,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -152,21 +148,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index ad62c8d74..5f5879b0d 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 00:35:29 +gem5 compiled Jan 23 2013 16:30:44 +gem5 started Jan 23 2013 18:22:44 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 87bad38e6..088aad8da 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.800193 # Nu sim_ticks 1800193397000 # Number of ticks simulated final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 477976 # Simulator instruction rate (inst/s) -host_op_rate 880696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 977754272 # Simulator tick rate (ticks/s) -host_mem_usage 276196 # Number of bytes of host memory used -host_seconds 1841.15 # Real time elapsed on the host +host_inst_rate 575805 # Simulator instruction rate (inst/s) +host_op_rate 1060952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1177876462 # Simulator tick rate (ticks/s) +host_mem_usage 292800 # Number of bytes of host memory used +host_seconds 1528.34 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493927 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory @@ -135,106 +135,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53002.770083 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use -system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits -system.cpu.dcache.overall_hits::total 606786131 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses -system.cpu.dcache.overall_misses::total 442048 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks -system.cpu.dcache.writebacks::total 422980 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2532 # number of replacements system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks. @@ -370,5 +270,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.770083 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 437952 # number of replacements +system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use +system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits +system.cpu.dcache.overall_hits::total 606786131 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses +system.cpu.dcache.overall_misses::total 442048 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks +system.cpu.dcache.writebacks::total 422980 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |