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authorNilay Vaish <nilay@cs.wisc.edu>2012-02-10 09:51:37 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-02-10 09:51:37 -0600
commit26ca8b87470912d5e593a21fc968dd2ddf0e20b2 (patch)
treebf97df45e65f08107321f58d83688b08bbd3f675 /tests/long/se/00.gzip/ref/x86
parent6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6 (diff)
downloadgem5-26ca8b87470912d5e593a21fc968dd2ddf0e20b2.tar.xz
Regressions: Update stats due to O3 CPU changes
Diffstat (limited to 'tests/long/se/00.gzip/ref/x86')
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini43
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/o3-timing/simout12
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt722
3 files changed, 405 insertions, 372 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
index 6e971ebcf..3b035cefe 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -89,6 +98,7 @@ numRobs=1
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
@@ -149,7 +159,14 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.fuPool]
type=FUPool
@@ -446,9 +463,25 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
@@ -479,7 +512,7 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
@@ -490,7 +523,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
@@ -498,7 +531,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
+cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
egid=100
env=
errout=cerr
@@ -522,7 +555,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
index bff73f5f1..774f2864e 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,12 +1,12 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr
+Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 28 2012 12:11:40
-gem5 started Jan 28 2012 12:12:43
+gem5 compiled Feb 9 2012 12:45:55
+gem5 started Feb 9 2012 12:46:40
gem5 executing on ribera.cs.wisc.edu
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -42,4 +42,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 588785308000 because target called exit()
+Exiting @ tick 586834596000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
index f7c59f027..1e4919244 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.588785 # Number of seconds simulated
-sim_ticks 588785308000 # Number of ticks simulated
-final_tick 588785308000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.586835 # Number of seconds simulated
+sim_ticks 586834596000 # Number of ticks simulated
+final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 112730 # Simulator instruction rate (inst/s)
-host_tick_rate 40933847 # Simulator tick rate (ticks/s)
-host_mem_usage 244824 # Number of bytes of host memory used
-host_seconds 14383.83 # Real time elapsed on the host
+host_inst_rate 99458 # Simulator instruction rate (inst/s)
+host_tick_rate 35994653 # Simulator tick rate (ticks/s)
+host_mem_usage 253740 # Number of bytes of host memory used
+host_seconds 16303.38 # Real time elapsed on the host
sim_insts 1621493982 # Number of instructions simulated
-system.physmem.bytes_read 5878272 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 57216 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 3742528 # Number of bytes written to this memory
-system.physmem.num_reads 91848 # Number of read requests responded to by this memory
-system.physmem.num_writes 58477 # Number of write requests responded to by this memory
+system.physmem.bytes_read 5879616 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3743488 # Number of bytes written to this memory
+system.physmem.num_reads 91869 # Number of read requests responded to by this memory
+system.physmem.num_writes 58492 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 9983727 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 97176 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 6356354 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 16340082 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 10019205 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 97172 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 6379119 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 16398324 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 1177570617 # number of cpu cycles simulated
+system.cpu.numCycles 1173669193 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 141882222 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 141882222 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 7459322 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 135523268 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 134664780 # Number of BTB hits
+system.cpu.BPredUnit.lookups 140536614 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 140536614 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 7896314 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 133769291 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 132901689 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 141519405 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1135188232 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 141882222 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 134664780 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 328423216 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 56273795 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 658902879 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 135738609 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 998788 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1177479353 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.766783 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.096310 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 138231227 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1143529036 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 140536614 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 132901689 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 330118681 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 56348337 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 656952944 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 136534174 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2392311 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1173574785 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.778199 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.100517 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 852058955 72.36% 72.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 15948065 1.35% 73.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 17931063 1.52% 75.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 17495755 1.49% 76.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 23352779 1.98% 78.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 16626553 1.41% 80.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 22402886 1.90% 82.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28214099 2.40% 84.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 183449198 15.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 846464435 72.13% 72.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 17271965 1.47% 73.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 15892053 1.35% 74.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 19142892 1.63% 76.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 23218397 1.98% 78.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 16689415 1.42% 79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 22145456 1.89% 81.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 30830267 2.63% 84.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 181919905 15.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1177479353 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.120487 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.964009 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 241266448 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 565597424 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 225300633 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 96681345 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 48633503 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2058834896 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 48633503 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 289994325 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 136667782 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 3607 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 255841310 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 446338826 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2031094400 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 199 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 278357951 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 133112570 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2019296537 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 4928551600 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 4928548640 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2960 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1173574785 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.119741 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.974320 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 240018155 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 564065687 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 224667967 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 96551481 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 48271495 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2053347825 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 48271495 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 288250921 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 136396250 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 3594 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 255481832 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 445170693 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2022383034 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 772 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 278054588 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 132157059 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2011799289 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 4917261318 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 4917257566 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 3752 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 401301887 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 93 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 797995614 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 517349896 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 226176362 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 355062669 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 148977960 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1979799927 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 215 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1779311117 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 175082 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 358154503 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 654941515 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 165 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1177479353 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.511119 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.319645 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 393804639 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 92 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 795963127 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 515675644 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 225280197 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 353360778 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 147850226 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1972232230 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 190 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1776284004 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 173989 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 350598274 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 640215855 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1173574785 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.513567 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.313751 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 271443176 23.05% 23.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 420511572 35.71% 58.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 239784716 20.36% 79.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 159545639 13.55% 92.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 48751983 4.14% 96.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 21481111 1.82% 98.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 13897994 1.18% 99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1713551 0.15% 99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 349611 0.03% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 268099715 22.84% 22.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 420406461 35.82% 58.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 239398162 20.40% 79.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 159391711 13.58% 92.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 48358537 4.12% 96.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 24330955 2.07% 98.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 11625243 0.99% 99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1646303 0.14% 99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 317698 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1177479353 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1173574785 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 183781 6.86% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2344413 87.49% 94.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 151333 5.65% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 185497 7.34% 7.34% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.34% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2190114 86.61% 93.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 153108 6.05% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 26390474 1.48% 1.48% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1101178190 61.89% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 457060255 25.69% 89.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 194682198 10.94% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 26819156 1.51% 1.51% # Type of FU issued
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+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.34% # Type of FU issued
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+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.34% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 456429787 25.70% 89.04% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 194719417 10.96% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1779311117 # Type of FU issued
-system.cpu.iq.rate 1.511002 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2679527 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001506 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4738956161 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2338163322 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1758678242 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 1776284004 # Type of FU issued
+system.cpu.iq.rate 1.513445 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2528719 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4728845466 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2323038766 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1755173186 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 458 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1755600151 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 1751993548 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 207757708 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 207962564 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 98307771 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 75876 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 215687 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 37990305 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 96633519 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 76725 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 215178 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 37094140 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1126 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 1306 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 48633503 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1923683 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 157688 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1979800142 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 665872 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 517349896 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 226176362 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 48271495 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1965747 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 154206 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1972232420 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 7113535 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 515675644 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 225280197 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 85 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 70768 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 44 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 215687 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4604749 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3040457 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7645206 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1766024784 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 451208749 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 13286333 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents 69568 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 118 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 215178 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4620478 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3457907 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8078385 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1762068190 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 450602678 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 14215814 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 645051015 # number of memory reference insts executed
-system.cpu.iew.exec_branches 112022135 # Number of branches executed
-system.cpu.iew.exec_stores 193842266 # Number of stores executed
-system.cpu.iew.exec_rate 1.499719 # Inst execution rate
-system.cpu.iew.wb_sent 1764443624 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1758678254 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1332033031 # num instructions producing a value
-system.cpu.iew.wb_consumers 1982428848 # num instructions consuming a value
+system.cpu.iew.exec_refs 644481818 # number of memory reference insts executed
+system.cpu.iew.exec_branches 111935144 # Number of branches executed
+system.cpu.iew.exec_stores 193879140 # Number of stores executed
+system.cpu.iew.exec_rate 1.501333 # Inst execution rate
+system.cpu.iew.wb_sent 1756702193 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1755173198 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1327558450 # num instructions producing a value
+system.cpu.iew.wb_consumers 1975144997 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.493480 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.671920 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 358308768 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7459361 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1128845850 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.436418 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.651874 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1125303290 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.440940 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.651939 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 347283519 30.76% 30.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 441725058 39.13% 69.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 99623372 8.83% 78.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 136537223 12.10% 90.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 31770740 2.81% 93.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 26056867 2.31% 95.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 22501724 1.99% 97.93% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.count 1621493982 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 607228182 # Number of memory references committed
@@ -266,48 +266,48 @@ system.cpu.commit.branches 107161579 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
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-system.cpu.cpi_total 0.726226 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 1.376982 # IPC: Total IPC of All Threads
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+system.cpu.ipc_total 1.381560 # IPC: Total IPC of All Threads
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system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -317,59 +317,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -378,69 +378,69 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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-system.cpu.l2cache.ReadReq_miss_rate 0.154524 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.235270 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.197937 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.197937 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34102.361848 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34214.742061 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34174.179078 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34174.179078 # average overall miss latency
+system.cpu.l2cache.occ_blocks::0 1981.498209 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15990.088083 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.060471 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.487979 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 181345 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 409999 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 190815 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 372160 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 372160 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 33162 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 58707 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 91869 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 91869 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 1129684500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2008512000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 3138196500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 3138196500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 214507 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 409999 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 249522 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 464029 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 464029 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.154596 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.235278 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.197981 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.197981 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34065.632350 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34212.478921 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34159.471639 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34159.471639 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -449,27 +449,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 58477 # number of writebacks
+system.cpu.l2cache.writebacks 58492 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 33152 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 58696 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 91848 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 91848 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses 33162 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 58707 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 91869 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 91869 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1027873500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819617000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 2847490500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 2847490500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1028173500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819949000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 2848122500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 2848122500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154524 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235270 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.197937 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.197937 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871501 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.698514 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.204730 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.204730 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154596 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235278 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.197981 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.197981 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.568482 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.545080 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions