diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/00.gzip/ref/x86 | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/00.gzip/ref/x86')
9 files changed, 599 insertions, 392 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 3b035cefe..5b4602be4 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -442,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -494,20 +480,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -531,12 +510,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 774f2864e..dd2c66002 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 9 2012 12:45:55 -gem5 started Feb 9 2012 12:46:40 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:08:06 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 1e4919244..db3272b03 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.586835 # Nu sim_ticks 586834596000 # Number of ticks simulated final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99458 # Simulator instruction rate (inst/s) -host_tick_rate 35994653 # Simulator tick rate (ticks/s) -host_mem_usage 253740 # Number of bytes of host memory used -host_seconds 16303.38 # Real time elapsed on the host -sim_insts 1621493982 # Number of instructions simulated +host_inst_rate 106927 # Simulator instruction rate (inst/s) +host_op_rate 197018 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71302744 # Simulator tick rate (ticks/s) +host_mem_usage 220908 # Number of bytes of host memory used +host_seconds 8230.18 # Real time elapsed on the host +sim_insts 880025312 # Number of instructions simulated +sim_ops 1621493982 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5879616 # Number of bytes read from this memory system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory system.physmem.bytes_written 3743488 # Number of bytes written to this memory @@ -236,7 +238,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted @@ -257,7 +260,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 1125303290 # Number of insts commited each cycle -system.cpu.commit.count 1621493982 # Number of instructions committed +system.cpu.commit.committedInsts 880025312 # Number of instructions committed +system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed system.cpu.commit.loads 419042125 # Number of loads committed @@ -272,12 +276,13 @@ system.cpu.rob.rob_reads 3082456564 # Th system.cpu.rob.rob_writes 3992764754 # The number of ROB writes system.cpu.timesIdled 21723 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 94408 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1621493982 # Number of Instructions Simulated -system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.723820 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.723820 # CPI: Total CPI of All Threads -system.cpu.ipc 1.381560 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.381560 # IPC: Total IPC of All Threads +system.cpu.committedInsts 880025312 # Number of Instructions Simulated +system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated +system.cpu.cpi 1.333677 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.333677 # CPI: Total CPI of All Threads +system.cpu.ipc 0.749807 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.749807 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3268959976 # number of integer regfile reads system.cpu.int_regfile_writes 1746565098 # number of integer regfile writes system.cpu.fp_regfile_reads 12 # number of floating regfile reads @@ -288,26 +293,39 @@ system.cpu.icache.total_refs 136532946 # To system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 152721.416107 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 807.278486 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.394179 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 136532946 # number of ReadReq hits -system.cpu.icache.demand_hits 136532946 # number of demand (read+write) hits -system.cpu.icache.overall_hits 136532946 # number of overall hits -system.cpu.icache.ReadReq_misses 1228 # number of ReadReq misses -system.cpu.icache.demand_misses 1228 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 43195500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 43195500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 43195500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 136534174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 136534174 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 136534174 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35175.488599 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35175.488599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35175.488599 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 807.278486 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.394179 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.394179 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 136532946 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 136532946 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 136532946 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 136532946 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 136532946 # number of overall hits +system.cpu.icache.overall_hits::total 136532946 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1228 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1228 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1228 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1228 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1228 # number of overall misses +system.cpu.icache.overall_misses::total 1228 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 43195500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 43195500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 43195500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 43195500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 43195500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 43195500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 136534174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 136534174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 136534174 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 136534174 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 136534174 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 136534174 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35175.488599 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,27 +334,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 334 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 334 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 334 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 894 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 894 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 894 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 31569000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 31569000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 31569000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.080537 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 334 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 894 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 894 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 894 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 894 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 894 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 894 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31569000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31569000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31569000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31569000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31569000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31569000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35312.080537 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35312.080537 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35312.080537 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 459037 # number of replacements system.cpu.dcache.tagsinuse 4094.269422 # Cycle average of tags in use @@ -344,32 +365,49 @@ system.cpu.dcache.total_refs 430357004 # To system.cpu.dcache.sampled_refs 463133 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 929.229841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 414463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.269422 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999577 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 242420503 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 187936501 # number of WriteReq hits -system.cpu.dcache.demand_hits 430357004 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 430357004 # number of overall hits -system.cpu.dcache.ReadReq_misses 217102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 249556 # number of WriteReq misses -system.cpu.dcache.demand_misses 466658 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 466658 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2192767500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 3219007000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 5411774500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 5411774500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 242637605 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 430823662 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 430823662 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000895 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001326 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.001083 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.001083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10100.171809 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 12898.936511 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 11596.875013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 11596.875013 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.269422 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999577 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999577 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 242420503 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 242420503 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187936501 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187936501 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 430357004 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 430357004 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 430357004 # number of overall hits +system.cpu.dcache.overall_hits::total 430357004 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 217102 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 217102 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 249556 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 249556 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 466658 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 466658 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 466658 # number of overall misses +system.cpu.dcache.overall_misses::total 466658 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2192767500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2192767500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3219007000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3219007000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 5411774500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 5411774500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 5411774500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 5411774500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242637605 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242637605 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 430823662 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 430823662 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 430823662 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 430823662 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000895 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001326 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001083 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001083 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10100.171809 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12898.936511 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11596.875013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11596.875013 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,32 +416,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 409999 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3488 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 35 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3523 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3523 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213614 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249521 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 463135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 463135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1523998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2469759000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3993757500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3993757500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000880 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001075 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7134.356831 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9898.000569 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 409999 # number of writebacks +system.cpu.dcache.writebacks::total 409999 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3488 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 35 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3523 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3523 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3523 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3523 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 213614 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 213614 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249521 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249521 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 463135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1523998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1523998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2469759000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2469759000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3993757500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3993757500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3993757500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3993757500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000880 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001326 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7134.356831 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9898.000569 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73601 # number of replacements system.cpu.l2cache.tagsinuse 17971.586292 # Cycle average of tags in use @@ -411,36 +457,75 @@ system.cpu.l2cache.total_refs 452847 # To system.cpu.l2cache.sampled_refs 89223 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 5.075451 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1981.498209 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15990.088083 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.060471 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487979 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181345 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 409999 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 190815 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 372160 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 372160 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33162 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58707 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91869 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91869 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1129684500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2008512000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3138196500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3138196500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214507 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 409999 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464029 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464029 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154596 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235278 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197981 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197981 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34065.632350 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34212.478921 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34159.471639 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34159.471639 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15990.088083 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 59.987883 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1921.510326 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.487979 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001831 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.058640 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.548449 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 214507 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 409999 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 409999 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 249522 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 249522 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 894 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 463135 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 464029 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 894 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 463135 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 464029 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996644 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151072 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235278 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996644 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.196439 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996644 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.196439 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34280.022447 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34059.713055 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34212.478921 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,30 +534,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58492 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33162 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91869 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91869 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1028173500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819949000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2848122500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2848122500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154596 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235278 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197981 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197981 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.568482 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.545080 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 58492 # number of writebacks +system.cpu.l2cache.writebacks::total 58492 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 891 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33162 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58707 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58707 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 891 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90978 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91869 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 891 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90978 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91869 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27674500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1000499000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028173500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1819949000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1819949000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27674500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2820448000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2848122500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27674500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2820448000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2848122500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151072 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235278 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.044893 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.036782 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.545080 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini index 393d71365..6904b6f42 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index 3da3c7641..061803200 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:33:19 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:08:56 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 3a54bb2c8..2bdb7b9df 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.963993 # Nu sim_ticks 963992704000 # Number of ticks simulated final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2202720 # Simulator instruction rate (inst/s) -host_tick_rate 1309536712 # Simulator tick rate (ticks/s) -host_mem_usage 204800 # Number of bytes of host memory used -host_seconds 736.13 # Real time elapsed on the host -sim_insts 1621493983 # Number of instructions simulated +host_inst_rate 1632386 # Simulator instruction rate (inst/s) +host_op_rate 3007760 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1788140018 # Simulator tick rate (ticks/s) +host_mem_usage 210284 # Number of bytes of host memory used +host_seconds 539.10 # Real time elapsed on the host +sim_insts 880025313 # Number of instructions simulated +sim_ops 1621493983 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11334586825 # Number of bytes read from this memory system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory system.physmem.bytes_written 864451000 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 48 # Nu system.cpu.numCycles 1927985409 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1621493983 # Number of instructions executed +system.cpu.committedInsts 880025313 # Number of instructions committed +system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index f841786ec..9097a5047 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index c3d33da65..527d3d172 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:37:10 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:11:10 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 8e512b7b9..308cb734c 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.803259 # Nu sim_ticks 1803258587000 # Number of ticks simulated final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1279975 # Simulator instruction rate (inst/s) -host_tick_rate 1423455894 # Simulator tick rate (ticks/s) -host_mem_usage 213784 # Number of bytes of host memory used -host_seconds 1266.82 # Real time elapsed on the host -sim_insts 1621493983 # Number of instructions simulated +host_inst_rate 972144 # Simulator instruction rate (inst/s) +host_op_rate 1791227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1992018099 # Simulator tick rate (ticks/s) +host_mem_usage 219200 # Number of bytes of host memory used +host_seconds 905.24 # Real time elapsed on the host +sim_insts 880025313 # Number of instructions simulated +sim_ops 1621493983 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5725952 # Number of bytes read from this memory system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory system.physmem.bytes_written 3712448 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 48 # Nu system.cpu.numCycles 3606517174 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1621493983 # Number of instructions executed +system.cpu.committedInsts 880025313 # Number of instructions committed +system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 1186516018 # To system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits -system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1186516018 # number of overall hits -system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses -system.cpu.icache.demand_misses 722 # number of demand (read+write) misses -system.cpu.icache.overall_misses 722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 660.186297 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.322357 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.322357 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1186516018 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1186516018 # number of overall hits +system.cpu.icache.overall_hits::total 1186516018 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses +system.cpu.icache.overall_misses::total 722 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40432000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40432000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40432000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40432000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40432000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40432000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1186516740 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use @@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 606786134 # To system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits -system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 606786134 # number of overall hits -system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses -system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 442048 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.896939 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999731 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999731 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 606786134 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 606786134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 606786134 # number of overall hits +system.cpu.dcache.overall_hits::total 606786134 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses +system.cpu.dcache.overall_misses::total 442048 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4043270000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4043270000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5872734000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5872734000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9916004000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9916004000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9916004000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9916004000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 607228182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 607228182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 396372 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks +system.cpu.dcache.writebacks::total 396372 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3451292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3451292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5138568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5138568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8589860000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 71208 # number of replacements system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use @@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs 423014 # To system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 353302 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 89468 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16187.723361 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 48.180025 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1821.019706 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.494010 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001470 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.055573 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.551054 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 166833 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 166833 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 396372 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 396372 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 186469 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 186469 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 353302 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 353302 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 353302 # number of overall hits +system.cpu.l2cache.overall_hits::total 353302 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 30493 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 31215 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 58253 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 58253 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 88746 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 89468 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 88746 # number of overall misses +system.cpu.l2cache.overall_misses::total 89468 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1585636000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1623180000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4614792000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4652336000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4614792000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4652336000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 396372 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 396372 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 442048 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 442770 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58007 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks +system.cpu.l2cache.writebacks::total 58007 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30493 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58253 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58253 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 88746 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 89468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 88746 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 89468 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1219720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1248600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2330120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2330120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3549840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3578720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |