diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/long/se/00.gzip/ref | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/long/se/00.gzip/ref')
14 files changed, 2549 insertions, 2535 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 5dbf49847..695f11b1b 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -179,6 +179,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -211,6 +212,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -218,25 +220,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index fa0d94e1a..302800256 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:19:12 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 22:56:38 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -41,4 +41,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 269661304500 because target called exit() +Exiting @ tick 269668883500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index c659f4312..0e822db77 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269672 # Number of seconds simulated -sim_ticks 269671683500 # Number of ticks simulated -final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269669 # Number of seconds simulated +sim_ticks 269668883500 # Number of ticks simulated +final_tick 269668883500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149368 # Simulator instruction rate (inst/s) -host_op_rate 149368 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66926769 # Simulator tick rate (ticks/s) -host_mem_usage 224496 # Number of bytes of host memory used -host_seconds 4029.35 # Real time elapsed on the host +host_inst_rate 49435 # Simulator instruction rate (inst/s) +host_op_rate 49435 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22150100 # Simulator tick rate (ticks/s) +host_mem_usage 271532 # Number of bytes of host memory used +host_seconds 12174.61 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6040649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6240240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240648 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240648 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6040649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6480888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6040712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6240305 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240651 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240651 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6040712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6480955 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 72 # Tr system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269671631500 # Total gap between requests +system.physmem.totGap 269668831500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -92,9 +92,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 1014 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 16677 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1891 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 383646750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1095736750 # Sum of mem lat for all requests +system.physmem.totQLat 383236250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1095312500 # Sum of mem lat for all requests system.physmem.totBusLat 131400000 # Total cycles spent in databus access -system.physmem.totBankLat 580690000 # Total cycles spent in bank access -system.physmem.avgQLat 14598.43 # Average queueing delay per request -system.physmem.avgBankLat 22096.27 # Average bank access latency per request +system.physmem.totBankLat 580676250 # Total cycles spent in bank access +system.physmem.avgQLat 14582.81 # Average queueing delay per request +system.physmem.avgBankLat 22095.75 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41694.70 # Average memory access latency +system.physmem.avgMemAccLat 41678.56 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -176,36 +176,36 @@ system.physmem.readRowHits 16315 # Nu system.physmem.writeRowHits 296 # Number of row buffer hits during writes system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes -system.physmem.avgGap 9875187.91 # Average gap between requests -system.cpu.branchPred.lookups 86405403 # Number of BP lookups -system.cpu.branchPred.condPredicted 81476373 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44774039 # Number of BTB lookups -system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits +system.physmem.avgGap 9875085.38 # Average gap between requests +system.cpu.branchPred.lookups 86401588 # Number of BP lookups +system.cpu.branchPred.condPredicted 81471319 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 36340860 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 45048223 # Number of BTB lookups +system.cpu.branchPred.BTBHits 34648139 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.410930 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 76.913442 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517881 # DTB read hits +system.cpu.dtb.read_hits 114517866 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520512 # DTB read accesses -system.cpu.dtb.write_hits 39453501 # DTB write hits +system.cpu.dtb.read_accesses 114520497 # DTB read accesses +system.cpu.dtb.write_hits 39453488 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455803 # DTB write accesses -system.cpu.dtb.data_hits 153971382 # DTB hits +system.cpu.dtb.write_accesses 39455790 # DTB write accesses +system.cpu.dtb.data_hits 153971354 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153976315 # DTB accesses -system.cpu.itb.fetch_hits 24997849 # ITB hits +system.cpu.dtb.data_accesses 153976287 # DTB accesses +system.cpu.itb.fetch_hits 24966979 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 24997871 # ITB accesses +system.cpu.itb.fetch_accesses 24967001 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,34 +219,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539343368 # number of cpu cycles simulated +system.cpu.numCycles 539337768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49180751 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541064074 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 37213741 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49187847 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541069811 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004918920 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1004924657 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255159834 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 154928367 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 255160339 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 154930401 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 34118747 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2217126 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36335873 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26212045 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.092858 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412134920 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535764686 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535759851 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 296132 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50809772 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488533596 # Number of cycles cpu stages are processed. -system.cpu.activity 90.579328 # Percentage of cycles cpu is active +system.cpu.timesIdled 296128 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50805895 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488531873 # Number of cycles cpu stages are processed. +system.cpu.activity 90.579949 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -258,72 +258,72 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896132 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896123 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896132 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115907 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896123 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115918 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115907 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200616262 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338727106 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.803610 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228924009 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310419359 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.555053 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197778592 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341564776 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.329744 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 427964982 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111378386 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.650738 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192544683 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346798685 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.300167 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115918 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200608412 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338729356 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.804679 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228909431 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310428337 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.557315 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197773731 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564037 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.330265 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 427958956 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111378812 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.651031 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192540057 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346797711 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.300654 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.833784 # Cycle average of tags in use -system.cpu.icache.total_refs 24996815 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.833568 # Cycle average of tags in use +system.cpu.icache.total_refs 24965946 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29236.040936 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29199.936842 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.833784 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 729.833568 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24996815 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24996815 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24996815 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24996815 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24996815 # number of overall hits -system.cpu.icache.overall_hits::total 24996815 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses -system.cpu.icache.overall_misses::total 1034 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55838000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55838000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55838000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55838000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55838000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55838000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24997849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24997849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24997849 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24997849 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24997849 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24997849 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24965946 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24965946 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24965946 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24965946 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24965946 # number of overall hits +system.cpu.icache.overall_hits::total 24965946 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1033 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1033 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1033 # number of overall misses +system.cpu.icache.overall_misses::total 1033 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55677000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55677000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55677000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55677000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55677000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55677000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24966979 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24966979 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24966979 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24966979 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24966979 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24966979 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54001.934236 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54001.934236 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54001.934236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54001.934236 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53898.354308 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53898.354308 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53898.354308 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53898.354308 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -332,50 +332,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 179 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45946500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45946500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45946500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53901.754386 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53901.754386 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53738.596491 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53738.596491 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.116891 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22879.137372 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.482898 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.953897 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.680097 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21684.500481 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.953671 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.683220 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.698215 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -400,17 +400,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses system.cpu.l2cache.overall_misses::total 26294 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1198171500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1198171500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1668831500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1713912500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1668831500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1713912500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44941500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470659500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 515601000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1197956000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1197956000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44941500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1668615500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1713557000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44941500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1668615500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1713557000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -435,17 +435,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56178.333646 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56178.333646 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65182.646231 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65182.646231 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53438.168847 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.272727 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 103826.218284 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56168.229557 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56168.229557 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65169.126036 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65169.126036 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -467,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34644438 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418276481 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452920919 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932715801 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932715801 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34644438 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350992282 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1385636720 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34644438 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350992282 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1385636720 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34505688 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418277231 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452782919 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932478797 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932478797 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34505688 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350756028 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1385261716 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34505688 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350756028 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1385261716 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -489,51 +489,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41194.337693 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.359030 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91204.373540 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43731.986168 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43731.986168 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41029.355529 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.540848 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91176.584575 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43720.873828 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43720.873828 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.423689 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.423663 # Cycle average of tags in use +system.cpu.dcache.total_refs 151786149 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 333.306578 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.423689 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.423663 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120811 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665348 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665348 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786159 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786159 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786159 # number of overall hits -system.cpu.dcache.overall_hits::total 151786159 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393231 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393231 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785973 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785973 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179204 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179204 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179204 # number of overall misses -system.cpu.dcache.overall_misses::total 2179204 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23170641500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23170641500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29155322500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29155322500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29155322500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29155322500 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 114120800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37665349 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37665349 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151786149 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151786149 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151786149 # number of overall hits +system.cpu.dcache.overall_hits::total 151786149 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393242 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393242 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1785972 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1785972 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2179214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2179214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2179214 # number of overall misses +system.cpu.dcache.overall_misses::total 2179214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984700000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5984700000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23169621500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23169621500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29154321500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29154321500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29154321500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29154321500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -550,32 +550,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.679613 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.679613 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13378.886281 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13378.886281 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15218.872857 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15218.872857 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.115760 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.115760 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13378.365548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13378.365548 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 191067 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6052 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.423968 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.570886 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191999 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 191999 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531810 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1531810 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1723809 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1723809 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723809 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723809 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192010 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192010 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531809 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1531809 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1723819 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1723819 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1723819 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1723819 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -584,14 +584,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643678500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643678500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782203500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782203500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6425882000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6425882000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6425882000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6425882000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -600,14 +600,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.465711 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.465711 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.015333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.015333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index daf1db8c9..edcedb474 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -479,6 +479,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -511,6 +512,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -518,25 +520,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index 043586087..4407b6430 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:43:44 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 22:56:39 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -41,4 +41,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 133778696500 because target called exit() +Exiting @ tick 133696809500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 80e818735..1f1ca601b 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133774 # Number of seconds simulated -sim_ticks 133773851500 # Number of ticks simulated -final_tick 133773851500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133697 # Number of seconds simulated +sim_ticks 133696809500 # Number of ticks simulated +final_tick 133696809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 262576 # Simulator instruction rate (inst/s) -host_op_rate 262576 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62108832 # Simulator tick rate (ticks/s) -host_mem_usage 226536 # Number of bytes of host memory used -host_seconds 2153.86 # Real time elapsed on the host +host_inst_rate 77616 # Simulator instruction rate (inst/s) +host_op_rate 77616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18348551 # Simulator tick rate (ticks/s) +host_mem_usage 272684 # Number of bytes of host memory used +host_seconds 7286.51 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 1697664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory system.physmem.bytes_written::total 67072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26524 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26526 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 455934 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12233661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12689595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 455934 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 455934 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 501383 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 501383 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 501383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 455934 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12233661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13190979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26524 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 457154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12240711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12697865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 457154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 457154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 501672 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 501672 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 501672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 457154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12240711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13199537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26526 # Total number of read requests seen system.physmem.writeReqs 1048 # Total number of write requests seen -system.physmem.cpureqs 27572 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697536 # Total number of bytes read from memory +system.physmem.cpureqs 27574 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697664 # Total number of bytes read from memory system.physmem.bytesWritten 67072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1697664 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -47,22 +47,22 @@ system.physmem.perBankRdReqs::0 1631 # Tr system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1627 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1647 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1682 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis @@ -70,21 +70,21 @@ system.physmem.perBankWrReqs::7 56 # Tr system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133773818000 # Total gap between requests +system.physmem.totGap 133696776000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26524 # Categorize read packet sizes +system.physmem.readPktSize::6 26526 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 1048 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 8806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 9044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5069 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,7 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see @@ -147,7 +147,7 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -156,56 +156,56 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 654284750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1345973500 # Sum of mem lat for all requests -system.physmem.totBusLat 132545000 # Total cycles spent in databus access -system.physmem.totBankLat 559143750 # Total cycles spent in bank access -system.physmem.avgQLat 24681.61 # Average queueing delay per request -system.physmem.avgBankLat 21092.60 # Average bank access latency per request +system.physmem.totQLat 652146750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1350583000 # Sum of mem lat for all requests +system.physmem.totBusLat 132555000 # Total cycles spent in databus access +system.physmem.totBankLat 565881250 # Total cycles spent in bank access +system.physmem.avgQLat 24599.10 # Average queueing delay per request +system.physmem.avgBankLat 21345.15 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50774.21 # Average memory access latency -system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 50944.25 # Average memory access latency +system.physmem.avgRdBW 12.70 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.70 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.24 # Average write queue length over time -system.physmem.readRowHits 16966 # Number of row buffer hits during reads -system.physmem.writeRowHits 271 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes -system.physmem.avgGap 4851799.58 # Average gap between requests -system.cpu.branchPred.lookups 76502410 # Number of BP lookups -system.cpu.branchPred.condPredicted 70922676 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2717282 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43095322 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41949760 # Number of BTB hits +system.physmem.avgWrQLen 9.33 # Average write queue length over time +system.physmem.readRowHits 16975 # Number of row buffer hits during reads +system.physmem.writeRowHits 275 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 26.24 # Row buffer hit rate for writes +system.physmem.avgGap 4848653.66 # Average gap between requests +system.cpu.branchPred.lookups 76441752 # Number of BP lookups +system.cpu.branchPred.condPredicted 70864410 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2706781 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43062122 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41938047 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.341795 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1606512 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 241 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.389643 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1605813 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122629608 # DTB read hits -system.cpu.dtb.read_misses 28810 # DTB read misses +system.cpu.dtb.read_hits 122608255 # DTB read hits +system.cpu.dtb.read_misses 28801 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122658418 # DTB read accesses -system.cpu.dtb.write_hits 40760367 # DTB write hits -system.cpu.dtb.write_misses 25602 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40785969 # DTB write accesses -system.cpu.dtb.data_hits 163389975 # DTB hits -system.cpu.dtb.data_misses 54412 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163444387 # DTB accesses -system.cpu.itb.fetch_hits 65529846 # ITB hits +system.cpu.dtb.read_accesses 122637056 # DTB read accesses +system.cpu.dtb.write_hits 40754827 # DTB write hits +system.cpu.dtb.write_misses 25617 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 40780444 # DTB write accesses +system.cpu.dtb.data_hits 163363082 # DTB hits +system.cpu.dtb.data_misses 54418 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 163417500 # DTB accesses +system.cpu.itb.fetch_hits 65484737 # ITB hits system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65529887 # ITB accesses +system.cpu.itb.fetch_accesses 65484778 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,238 +219,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267547704 # number of cpu cycles simulated +system.cpu.numCycles 267393620 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67181660 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699454641 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76502410 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43556272 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117851527 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11664601 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73301689 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 67132788 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699091920 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76441752 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43543860 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117791826 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11623941 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73287443 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65529846 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 933458 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267250540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.617224 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.444995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65484737 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 927172 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267096777 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.617373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.445045 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149399013 55.90% 55.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10348526 3.87% 59.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11849388 4.43% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10578020 3.96% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7012807 2.62% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2871984 1.07% 71.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3578789 1.34% 73.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3106707 1.16% 74.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68505306 25.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149304951 55.90% 55.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10344865 3.87% 59.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11847519 4.44% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10566772 3.96% 68.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7010837 2.62% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2867971 1.07% 71.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3579531 1.34% 73.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3103336 1.16% 74.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68470995 25.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267250540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285939 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.614317 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84320129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57595253 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102753479 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13668133 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8913546 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3876280 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 932 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691464517 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3449 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8913546 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92299678 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12776720 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1189 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103108433 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50150974 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 681302234 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 431 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38477727 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5455282 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520934901 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 897390123 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 897387366 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2757 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267096777 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285877 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.614467 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84255179 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57589844 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102698571 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13670600 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8882583 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3874487 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 931 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691126555 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3231 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8882583 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92229912 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12770086 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1212 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103061748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50151236 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 680987279 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38480754 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5456693 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520711815 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 896998441 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 896995902 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2539 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 57080012 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 63 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112027328 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 127008438 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42384710 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14844783 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10088023 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621271293 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604725807 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299798 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 55080788 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30005964 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267250540 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.262767 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.823653 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 56856926 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 56 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 61 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112143528 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 126973457 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42377854 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14839100 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10235293 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621082747 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 48 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604577802 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299631 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 54891737 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29918454 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267096777 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.263516 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.822324 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52429829 19.62% 19.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55852855 20.90% 40.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53444845 20.00% 60.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36460113 13.64% 74.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31255141 11.70% 85.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23773948 8.90% 94.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10075913 3.77% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3406027 1.27% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 551869 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52289348 19.58% 19.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55783537 20.89% 40.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53427937 20.00% 60.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36631888 13.71% 74.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31292246 11.72% 85.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23678415 8.87% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10025583 3.75% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3414414 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 553409 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267250540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267096777 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2756472 71.14% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 40 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 728591 18.80% 89.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 389871 10.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2692091 70.58% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 42 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 729838 19.13% 89.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 392410 10.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439176954 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7066 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124356224 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41185515 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439064264 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7069 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124327148 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41179273 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604725807 # Type of FU issued -system.cpu.iq.rate 2.260254 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3874974 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006408 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480873086 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 676355161 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596602519 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3840 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2402 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1730 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608598846 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1935 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12280408 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604577802 # Type of FU issued +system.cpu.iq.rate 2.261003 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3814381 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006309 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480362706 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 675977802 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596495784 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3687 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2189 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1715 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608390320 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1863 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12281051 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12494396 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 35705 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5495 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2933389 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12459415 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35750 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5512 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2926533 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6442 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 54892 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6468 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 56300 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8913546 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1440408 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 191911 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 664145675 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1694595 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 127008438 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42384710 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 55 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 143753 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7490 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5495 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342563 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1811283 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3153846 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599598114 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122658565 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5127693 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8882583 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1439479 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 190555 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 663921502 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1696631 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 126973457 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42377854 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 142659 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7414 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5512 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1334753 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1804223 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3138976 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599473269 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122637223 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5104533 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42874327 # number of nop insts executed -system.cpu.iew.exec_refs 163462793 # number of memory reference insts executed -system.cpu.iew.exec_branches 66641793 # Number of branches executed -system.cpu.iew.exec_stores 40804228 # Number of stores executed -system.cpu.iew.exec_rate 2.241089 # Inst execution rate -system.cpu.iew.wb_sent 597543507 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596604249 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415969736 # num instructions producing a value -system.cpu.iew.wb_consumers 530347418 # num instructions consuming a value +system.cpu.iew.exec_nop 42838707 # number of nop insts executed +system.cpu.iew.exec_refs 163435917 # number of memory reference insts executed +system.cpu.iew.exec_branches 66623579 # Number of branches executed +system.cpu.iew.exec_stores 40798694 # Number of stores executed +system.cpu.iew.exec_rate 2.241913 # Inst execution rate +system.cpu.iew.wb_sent 597432372 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596497499 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415924305 # num instructions producing a value +system.cpu.iew.wb_consumers 530247239 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229899 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784334 # average fanout of values written-back +system.cpu.iew.wb_rate 2.230784 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784397 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62164646 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61940872 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2716416 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258336994 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.329736 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.693311 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2705903 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258214194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.330844 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.692748 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79521079 30.78% 30.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72557315 28.09% 58.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25650829 9.93% 68.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9136101 3.54% 72.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10241480 3.96% 76.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20967757 8.12% 84.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6801640 2.63% 87.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3711202 1.44% 88.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29749591 11.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79436879 30.76% 30.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72473576 28.07% 58.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25624236 9.92% 68.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9154468 3.55% 72.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10267531 3.98% 76.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21039855 8.15% 84.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6818360 2.64% 87.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3702360 1.43% 88.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29696929 11.50% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258336994 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258214194 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,192 +461,192 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29749591 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29696929 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892544623 # The number of ROB reads -system.cpu.rob.rob_writes 1336970755 # The number of ROB writes -system.cpu.timesIdled 34274 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 297164 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892250711 # The number of ROB reads +system.cpu.rob.rob_writes 1336492363 # The number of ROB writes +system.cpu.timesIdled 34289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 296843 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.473073 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.473073 # CPI: Total CPI of All Threads -system.cpu.ipc 2.113838 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.113838 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 845171662 # number of integer regfile reads -system.cpu.int_regfile_writes 490625638 # number of integer regfile writes -system.cpu.fp_regfile_reads 396 # number of floating regfile reads +system.cpu.cpi 0.472801 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.472801 # CPI: Total CPI of All Threads +system.cpu.ipc 2.115056 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.115056 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 844981893 # number of integer regfile reads +system.cpu.int_regfile_writes 490535855 # number of integer regfile writes +system.cpu.fp_regfile_reads 379 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 39 # number of replacements -system.cpu.icache.tagsinuse 824.684718 # Cycle average of tags in use -system.cpu.icache.total_refs 65528462 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 971 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67485.542739 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 825.626517 # Cycle average of tags in use +system.cpu.icache.total_refs 65483355 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 973 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67300.467626 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 824.684718 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.402678 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.402678 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65528462 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65528462 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65528462 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65528462 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65528462 # number of overall hits -system.cpu.icache.overall_hits::total 65528462 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses -system.cpu.icache.overall_misses::total 1383 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 72600500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 72600500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 72600500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 72600500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 72600500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 72600500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65529845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65529845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65529845 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65529845 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65529845 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65529845 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 825.626517 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.403138 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.403138 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65483355 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65483355 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65483355 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65483355 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65483355 # number of overall hits +system.cpu.icache.overall_hits::total 65483355 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses +system.cpu.icache.overall_misses::total 1381 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 73729000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 73729000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 73729000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 73729000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 73729000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 73729000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65484736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65484736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65484736 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65484736 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65484736 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65484736 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52494.938539 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52494.938539 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52494.938539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52494.938539 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53388.124547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53388.124547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53388.124547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53388.124547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53388.124547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53388.124547 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 971 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 971 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 971 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 971 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 971 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54205000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54205000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54205000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54205000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54205000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54205000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 408 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 408 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 408 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 408 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 408 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 408 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 973 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 973 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 973 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 973 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 973 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54179000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54179000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55823.892894 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55823.892894 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55823.892894 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55823.892894 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55823.892894 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55823.892894 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55682.425488 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55682.425488 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55682.425488 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55682.425488 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55682.425488 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55682.425488 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1081 # number of replacements -system.cpu.l2cache.tagsinuse 22920.644164 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547028 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23516 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.261949 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22922.098360 # Cycle average of tags in use +system.cpu.l2cache.total_refs 547070 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23518 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.261757 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21474.762913 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 815.139111 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 630.742140 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655358 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024876 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019249 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699483 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21473.132839 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 816.078621 # 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Number of misses that were no-allocate -system.cpu.dcache.replacements 460826 # number of replacements -system.cpu.dcache.tagsinuse 4090.898597 # Cycle average of tags in use -system.cpu.dcache.total_refs 146919615 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464922 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 316.009169 # Average number of references to valid blocks. +system.cpu.dcache.replacements 460841 # number of replacements +system.cpu.dcache.tagsinuse 4090.895658 # Cycle average of tags in use +system.cpu.dcache.total_refs 146899681 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464937 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 315.956099 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 301835000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.898597 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998755 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998755 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109271003 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109271003 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37648598 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37648598 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146919601 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146919601 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146919601 # number of overall hits -system.cpu.dcache.overall_hits::total 146919601 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1024794 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1024794 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802723 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802723 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2827517 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2827517 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2827517 # number of overall misses -system.cpu.dcache.overall_misses::total 2827517 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15336763000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15336763000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26197701326 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26197701326 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 20000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 20000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41534464326 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41534464326 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41534464326 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41534464326 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110295797 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110295797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4090.895658 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998754 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998754 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 109250298 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109250298 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37649372 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37649372 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146899670 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146899670 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146899670 # number of overall hits +system.cpu.dcache.overall_hits::total 146899670 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1022486 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1022486 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1801949 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1801949 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2824435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2824435 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2824435 # number of overall misses +system.cpu.dcache.overall_misses::total 2824435 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15308231000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15308231000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26204381408 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26204381408 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 48500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 48500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41512612408 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41512612408 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41512612408 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41512612408 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110272784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110272784 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149747118 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149747118 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149747118 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149747118 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009291 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009291 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045695 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045695 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.125000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018882 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018882 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018882 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018882 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14965.703351 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14965.703351 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14532.294382 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14532.294382 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14689.377403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14689.377403 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 303569 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2051 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17829 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 149724105 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149724105 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149724105 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149724105 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009272 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009272 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045675 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045675 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.312500 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.312500 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018864 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018864 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018864 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018864 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14971.580051 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14971.580051 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14542.243653 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14542.243653 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9700 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9700 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14697.669590 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14697.669590 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14697.669590 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14697.669590 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 306629 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2099 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 18462 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.026698 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 186.454545 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.608656 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 190.818182 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444903 # number of writebacks -system.cpu.dcache.writebacks::total 444903 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814423 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 814423 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548172 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1548172 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2362595 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2362595 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2362595 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2362595 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210371 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210371 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254551 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254551 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464922 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464922 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464922 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464922 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2696208000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2696208000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4103693497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4103693497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6799901497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6799901497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6799901497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6799901497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 444926 # number of writebacks +system.cpu.dcache.writebacks::total 444926 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 812044 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 812044 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547454 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1547454 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2359498 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2359498 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2359498 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2359498 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210442 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210442 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254495 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254495 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464937 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464937 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464937 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464937 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4104342498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4104342498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6802118498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6802118498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6802118498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6802118498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12816.443331 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12816.443331 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16121.301810 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16121.301810 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12819.570238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12819.570238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16127.399352 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16127.399352 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 67f052df7..e1addb169 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 385dec7c7..67d73bf07 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:48:55 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 01:22:50 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164543008000 because target called exit() +Exiting @ tick 164562530500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index aa7b7ad18..595117ec0 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,99 +1,99 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164572 # Number of seconds simulated -sim_ticks 164572262000 # Number of ticks simulated -final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164563 # Number of seconds simulated +sim_ticks 164562530500 # Number of ticks simulated +final_tick 164562530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185108 # Simulator instruction rate (inst/s) -host_op_rate 195599 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53440170 # Simulator tick rate (ticks/s) -host_mem_usage 241944 # Number of bytes of host memory used -host_seconds 3079.56 # Real time elapsed on the host +host_inst_rate 62422 # Simulator instruction rate (inst/s) +host_op_rate 65960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18020016 # Simulator tick rate (ticks/s) +host_mem_usage 288128 # Number of bytes of host memory used +host_seconds 9132.21 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1701952 # Number of bytes read from this memory -system.physmem.bytes_read::total 1749376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162432 # Number of bytes written to this memory -system.physmem.bytes_written::total 162432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 741 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26593 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27334 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2538 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2538 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 288165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10341670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10629835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 288165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 288165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 986995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 986995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 986995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 288165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10341670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11616830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27336 # Total number of read requests seen -system.physmem.writeReqs 2538 # Total number of write requests seen -system.physmem.cpureqs 29874 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1749376 # Total number of bytes read from memory -system.physmem.bytesWritten 162432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1749376 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162432 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1701120 # Number of bytes read from this memory +system.physmem.bytes_read::total 1748096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory +system.physmem.bytes_written::total 162368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26580 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27314 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 285460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10337226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10622685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 285460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 285460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 986664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 986664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 986664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 285460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10337226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11609350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27315 # Total number of read requests seen +system.physmem.writeReqs 2537 # Total number of write requests seen +system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1748096 # Total number of bytes read from memory +system.physmem.bytesWritten 162368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1748096 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1691 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1742 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1759 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1740 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1680 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 163 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164572246000 # Total gap between requests +system.physmem.totGap 164562514500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27336 # Categorize read packet sizes +system.physmem.readPktSize::6 27315 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2538 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2537 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 14709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3454 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -131,7 +131,7 @@ system.physmem.wrQLenPdf::3 111 # Wh system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see @@ -156,36 +156,36 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 921339250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1672034250 # Sum of mem lat for all requests -system.physmem.totBusLat 136675000 # Total cycles spent in databus access -system.physmem.totBankLat 614020000 # Total cycles spent in bank access -system.physmem.avgQLat 33704.25 # Average queueing delay per request -system.physmem.avgBankLat 22461.95 # Average bank access latency per request -system.physmem.avgBusLat 4999.82 # Average bus latency per request -system.physmem.avgMemAccLat 61166.02 # Average memory access latency -system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 922192000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1672085750 # Sum of mem lat for all requests +system.physmem.totBusLat 136575000 # Total cycles spent in databus access +system.physmem.totBankLat 613318750 # Total cycles spent in bank access +system.physmem.avgQLat 33761.38 # Average queueing delay per request +system.physmem.avgBankLat 22453.55 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 61214.93 # Average memory access latency +system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 7.98 # Average write queue length over time -system.physmem.readRowHits 16887 # Number of row buffer hits during reads +system.physmem.avgWrQLen 5.61 # Average write queue length over time +system.physmem.readRowHits 16878 # Number of row buffer hits during reads system.physmem.writeRowHits 1046 # Number of row buffer hits during writes -system.physmem.readRowHitRate 61.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes -system.physmem.avgGap 5508878.82 # Average gap between requests -system.cpu.branchPred.lookups 85156760 # Number of BP lookups -system.cpu.branchPred.condPredicted 79937555 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2342179 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47221599 # Number of BTB lookups -system.cpu.branchPred.BTBHits 46882126 # Number of BTB hits +system.physmem.readRowHitRate 61.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.23 # Row buffer hit rate for writes +system.physmem.avgGap 5512612.71 # Average gap between requests +system.cpu.branchPred.lookups 85150983 # Number of BP lookups +system.cpu.branchPred.condPredicted 79934550 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2340692 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 47125153 # Number of BTB lookups +system.cpu.branchPred.BTBHits 46874770 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.281107 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1427254 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1090 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.468685 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1426734 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1006 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,134 +229,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329144525 # number of cpu cycles simulated +system.cpu.numCycles 329125062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 68500133 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666893560 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85156760 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48309380 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129633878 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13101459 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119325440 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 68488081 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666859732 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85150983 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48301504 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129623989 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13095310 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119330996 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 311 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 265 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67084243 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755399 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328191292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.165364 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 67073182 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755353 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328169942 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193997 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198557643 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20911639 6.37% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4968720 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14346044 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8890886 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9446619 2.88% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4399795 1.34% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5788532 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60881414 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198546194 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20910126 6.37% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4967453 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14343462 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8888191 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9444820 2.88% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4399595 1.34% 79.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788141 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60881960 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328191292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258721 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.026142 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92969239 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96174869 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107931491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20385682 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10730011 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4738020 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1580 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703286632 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5586 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10730011 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107159029 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14373843 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39888 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114052351 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81836170 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694854437 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59359193 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20344162 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721334030 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230715755 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230715627 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328169942 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258719 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026159 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92898933 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96237751 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107895398 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20412735 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10725125 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4735181 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1555 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703255584 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5767 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10725125 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107098247 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14386106 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39798 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114033717 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81886949 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694825042 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59412332 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20333868 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 677 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721309974 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230585653 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230585525 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93916657 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1707 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1652 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170570480 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172204690 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80467392 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21722432 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29158581 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 680011931 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2919 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645607270 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1367531 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77472778 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193408701 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 215 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328191292 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93892601 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1652 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1598 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170754110 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172203089 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80461729 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21612175 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28771400 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 679988719 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2878 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645594653 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1373062 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77449325 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193321568 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 174 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328169942 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.725062 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85141419 25.94% 46.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76162032 23.21% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40819070 12.44% 82.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14914631 4.54% 95.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68186439 20.78% 20.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85247300 25.98% 46.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75946350 23.14% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40813735 12.44% 82.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28838397 8.79% 91.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14924394 4.55% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5564389 1.70% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6539948 1.99% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2108990 0.64% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328191292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328169942 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 216791 5.75% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2693843 71.39% 77.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 862775 22.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 216923 5.73% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2702396 71.39% 77.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 865914 22.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403382320 62.48% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403371824 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165566556 25.65% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76651819 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165561293 25.64% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76654974 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645607270 # Type of FU issued -system.cpu.iq.rate 1.961470 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3773409 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005845 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624546736 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757499752 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637553210 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645594653 # Type of FU issued +system.cpu.iq.rate 1.961548 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3785233 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005863 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624517507 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757453052 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637549292 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649380659 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649379866 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30362769 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30368159 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23252097 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 121645 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12371 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10246379 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23250496 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123413 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12359 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10240716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12896 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35853 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12899 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 36224 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10730011 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 795888 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 91006 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 680017934 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 687807 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172204690 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80467392 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1591 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32670 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15237 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12371 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1357657 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460843 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2818500 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641514820 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163491606 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4092450 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10725125 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 795867 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 92517 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 679994676 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 687635 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172203089 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80461729 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1550 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32824 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16429 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12359 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1356301 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1461196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2817497 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641509024 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163485499 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4085629 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3084 # number of nop insts executed -system.cpu.iew.exec_refs 239364786 # number of memory reference insts executed -system.cpu.iew.exec_branches 74674061 # Number of branches executed -system.cpu.iew.exec_stores 75873180 # Number of stores executed -system.cpu.iew.exec_rate 1.949037 # Inst execution rate -system.cpu.iew.wb_sent 638961643 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637553226 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418732313 # num instructions producing a value -system.cpu.iew.wb_consumers 650059572 # num instructions consuming a value +system.cpu.iew.exec_nop 3079 # number of nop insts executed +system.cpu.iew.exec_refs 239366742 # number of memory reference insts executed +system.cpu.iew.exec_branches 74672084 # Number of branches executed +system.cpu.iew.exec_stores 75881243 # Number of stores executed +system.cpu.iew.exec_rate 1.949135 # Inst execution rate +system.cpu.iew.wb_sent 638953926 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637549308 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418527294 # num instructions producing a value +system.cpu.iew.wb_consumers 649860425 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937001 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644145 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937103 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644026 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77666777 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77643008 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2340669 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317461281 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897428 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237399 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2339215 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317444817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897526 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237559 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93255759 29.38% 29.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104348924 32.87% 62.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42985847 13.54% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8791848 2.77% 78.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25959048 8.18% 86.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12901404 4.06% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7629324 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1168492 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20420635 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93252713 29.38% 29.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104341557 32.87% 62.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42984071 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8786627 2.77% 78.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25947006 8.17% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12913913 4.07% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7624115 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1170537 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20424278 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317461281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317444817 # Number of insts commited each cycle system.cpu.commit.committedInsts 570051636 # Number of instructions committed system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,69 +472,69 @@ system.cpu.commit.branches 70892524 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20420635 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20424278 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 977066653 # The number of ROB reads -system.cpu.rob.rob_writes 1370815087 # The number of ROB writes -system.cpu.timesIdled 44013 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 953233 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977022777 # The number of ROB reads +system.cpu.rob.rob_writes 1370762747 # The number of ROB writes +system.cpu.timesIdled 43954 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 955120 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570051585 # Number of Instructions Simulated system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated -system.cpu.cpi 0.577394 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577394 # CPI: Total CPI of All Threads -system.cpu.ipc 1.731919 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.731919 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204307958 # number of integer regfile reads -system.cpu.int_regfile_writes 663049374 # number of integer regfile writes +system.cpu.cpi 0.577360 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577360 # CPI: Total CPI of All Threads +system.cpu.ipc 1.732021 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.732021 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204272502 # number of integer regfile reads +system.cpu.int_regfile_writes 663034338 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234758339 # number of misc regfile reads +system.cpu.misc_regfile_reads 234758554 # number of misc regfile reads system.cpu.misc_regfile_writes 2656 # number of misc regfile writes -system.cpu.icache.replacements 66 # number of replacements -system.cpu.icache.tagsinuse 690.513263 # Cycle average of tags in use -system.cpu.icache.total_refs 67083102 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 830 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 80823.014458 # Average number of references to valid blocks. +system.cpu.icache.replacements 49 # number of replacements +system.cpu.icache.tagsinuse 688.587828 # Cycle average of tags in use +system.cpu.icache.total_refs 67072069 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 83009.986386 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 690.513263 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.337165 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.337165 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67083102 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67083102 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67083102 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67083102 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67083102 # number of overall hits -system.cpu.icache.overall_hits::total 67083102 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses -system.cpu.icache.overall_misses::total 1141 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 54478999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 54478999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 54478999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 54478999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 54478999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 54478999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67084243 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67084243 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67084243 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67084243 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67084243 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67084243 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 688.587828 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.336225 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.336225 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67072069 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67072069 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67072069 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67072069 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67072069 # number of overall hits +system.cpu.icache.overall_hits::total 67072069 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1113 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1113 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1113 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1113 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1113 # number of overall misses +system.cpu.icache.overall_misses::total 1113 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54408499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54408499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54408499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54408499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54408499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54408499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67073182 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67073182 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67073182 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67073182 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67073182 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67073182 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47746.712533 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47746.712533 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47746.712533 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47746.712533 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48884.545373 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48884.545373 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48884.545373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48884.545373 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -543,124 +543,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 41.142857 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 832 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 832 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 832 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 832 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 832 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 832 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42177999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42177999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42177999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42177999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42177999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42177999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 304 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 304 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 304 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 304 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 304 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 304 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 809 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 809 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 809 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 809 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 809 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 809 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42322999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42322999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42322999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42322999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42322999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42322999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50694.710337 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50694.710337 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 658692196 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310573848 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310573848 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31595584 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937670460 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969266044 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31595584 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937670460 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969266044 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.907293 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024244 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027846 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088165 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088165 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.907293 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059772 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061311 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.907293 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059772 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061311 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43045.754768 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130945.210274 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 119263.479269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60140.136197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60140.136197 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43045.754768 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72896.823295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72094.674867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43045.754768 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72896.823295 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72094.674867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440669 # number of replacements -system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use -system.cpu.dcache.total_refs 197567614 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444765 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 444.206747 # Average number of references to valid blocks. +system.cpu.dcache.replacements 440610 # number of replacements +system.cpu.dcache.tagsinuse 4091.483802 # Cycle average of tags in use +system.cpu.dcache.total_refs 197562457 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444706 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.254085 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 314058000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.484070 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4091.483802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998897 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998897 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131523721 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131523721 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66041240 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66041240 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1324 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1324 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 131512310 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131512310 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66047494 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66047494 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1326 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1326 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197564961 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197564961 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197564961 # number of overall hits -system.cpu.dcache.overall_hits::total 197564961 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341919 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341919 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3376291 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3376291 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 197559804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197559804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197559804 # number of overall hits +system.cpu.dcache.overall_hits::total 197559804 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 341685 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 341685 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3370037 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3370037 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3718210 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses -system.cpu.dcache.overall_misses::total 3718210 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073533500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5073533500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45778762266 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45778762266 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45778762266 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45778762266 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3711722 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3711722 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3711722 # number of overall misses +system.cpu.dcache.overall_misses::total 3711722 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5064964500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5064964500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 40707637762 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40707637762 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 338000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45772602262 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45772602262 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45772602262 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45772602262 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131853995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131853995 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1348 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1348 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201283171 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201283171 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201283171 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201283171 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002593 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002593 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048637 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048637 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016345 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016345 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018473 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.407635 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.407635 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12312.043232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12312.043232 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.930261 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 201271526 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201271526 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201271526 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201271526 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002591 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002591 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048547 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048547 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016320 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016320 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018441 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018441 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018441 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018441 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14823.490935 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14823.490935 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12079.285112 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12079.285112 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15363.636364 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15363.636364 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12331.904777 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12331.904777 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 146535 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 32 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5250 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.911429 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421643 # number of writebacks -system.cpu.dcache.writebacks::total 421643 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144320 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144320 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3129122 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3129122 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 421641 # number of writebacks +system.cpu.dcache.writebacks::total 421641 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144151 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144151 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3122863 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3122863 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3273442 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3273442 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3273442 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3273442 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197599 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197599 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247169 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247169 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444768 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836404500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836404500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932827321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6932827321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932827321 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6932827321 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 3267014 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3267014 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3267014 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3267014 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197534 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197534 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247174 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247174 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444708 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444708 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444708 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444708 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2832398000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2832398000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097760821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097760821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6930158821 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6930158821 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6930158821 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6930158821 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.346429 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.346429 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14338.787247 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14338.787247 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16578.446038 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16578.446038 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 3e0d99c0f..d23b0a96e 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -496,7 +496,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -523,6 +523,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 677217bc4..497cf6063 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:20:14 -gem5 started Feb 13 2013 14:16:35 -gem5 executing on u200540-lin +gem5 compiled Mar 26 2013 15:04:14 +gem5 started Mar 26 2013 23:39:12 +gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 387315507500 because target called exit() +Exiting @ tick 387290918500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 4f3b9b27a..fc36793dc 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387321 # Number of seconds simulated -sim_ticks 387320726500 # Number of ticks simulated -final_tick 387320726500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387291 # Number of seconds simulated +sim_ticks 387290918500 # Number of ticks simulated +final_tick 387290918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176162 # Simulator instruction rate (inst/s) -host_op_rate 176717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48695201 # Simulator tick rate (ticks/s) -host_mem_usage 235496 # Number of bytes of host memory used -host_seconds 7953.98 # Real time elapsed on the host +host_inst_rate 75176 # Simulator instruction rate (inst/s) +host_op_rate 75413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20778674 # Simulator tick rate (ticks/s) +host_mem_usage 280588 # Number of bytes of host memory used +host_seconds 18638.87 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678784 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76480 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678656 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26231 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1198 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26229 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27427 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4334351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418547 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418547 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4334351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4950357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27427 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4334354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4532324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197970 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197970 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418579 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418579 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4334354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4950904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27428 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29960 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755264 # Total number of bytes read from memory +system.physmem.cpureqs 29961 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755328 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755264 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755328 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -48,16 +48,16 @@ system.physmem.perBankRdReqs::1 1716 # Tr system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1708 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1770 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 154 # Tr system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387320698500 # Total gap between requests +system.physmem.totGap 387290890500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27427 # Categorize read packet sizes +system.physmem.readPktSize::6 27428 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,9 +92,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 2533 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 7983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5144 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 712904000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1439226500 # Sum of mem lat for all requests -system.physmem.totBusLat 137135000 # Total cycles spent in databus access -system.physmem.totBankLat 589187500 # Total cycles spent in bank access -system.physmem.avgQLat 25992.78 # Average queueing delay per request -system.physmem.avgBankLat 21482.03 # Average bank access latency per request +system.physmem.totQLat 716281750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1441798000 # Sum of mem lat for all requests +system.physmem.totBusLat 137140000 # Total cycles spent in databus access +system.physmem.totBankLat 588376250 # Total cycles spent in bank access +system.physmem.avgQLat 26114.98 # Average queueing delay per request +system.physmem.avgBankLat 21451.66 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52474.81 # Average memory access latency +system.physmem.avgMemAccLat 52566.65 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s @@ -171,252 +171,252 @@ system.physmem.avgConsumedWrBW 0.42 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 16.63 # Average write queue length over time -system.physmem.readRowHits 17586 # Number of row buffer hits during reads -system.physmem.writeRowHits 1048 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes -system.physmem.avgGap 12927927.19 # Average gap between requests -system.cpu.branchPred.lookups 97754812 # Number of BP lookups -system.cpu.branchPred.condPredicted 88045070 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3614513 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65790839 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65487235 # Number of BTB hits +system.physmem.avgWrQLen 17.33 # Average write queue length over time +system.physmem.readRowHits 17584 # Number of row buffer hits during reads +system.physmem.writeRowHits 1051 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.49 # Row buffer hit rate for writes +system.physmem.avgGap 12926500.80 # Average gap between requests +system.cpu.branchPred.lookups 97760274 # Number of BP lookups +system.cpu.branchPred.condPredicted 88050389 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3615826 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65794197 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65495164 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.538531 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.545502 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774641454 # number of cpu cycles simulated +system.cpu.numCycles 774581838 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164855086 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642226882 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97754812 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65488562 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329193327 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20835132 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263364086 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2508 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 164861421 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642294018 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97760274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65496491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329212106 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20844019 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263270886 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2530 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161933823 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 733897 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774407665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126639 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146663 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161941896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 736850 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774347981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146753 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445214338 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74055584 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37896707 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077649 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28106182 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18772378 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11485240 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3791473 0.49% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146008114 18.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445135875 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74066133 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37898132 4.89% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9078559 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28105360 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18771878 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11487710 1.48% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3792341 0.49% 81.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146011993 18.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774407665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126194 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.119983 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215996576 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214396476 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284196048 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42825985 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16992580 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636523781 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16992580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239852916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36748965 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52423247 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302028125 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126361832 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625670094 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 774347981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120233 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 216009984 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214299096 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284224623 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42813319 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17000959 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636588191 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17000959 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239857670 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36775472 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52409372 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302053149 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126251359 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625741176 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30926636 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73309992 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3198488 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356344294 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746400105 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712277962 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34122143 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 30927043 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73283464 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3120923 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356412040 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746512805 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712406209 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34106596 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111573855 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2642593 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2663144 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271720784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436941817 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179749373 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254480906 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83188791 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512511277 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2608080 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459319933 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 52996 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109213691 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130186216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 364409 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774407665 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884434 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431122 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111641601 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2643056 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663342 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271532800 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436949673 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179753673 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254530912 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83488154 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512578374 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2608372 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459383903 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 52245 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109279211 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130205744 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 364701 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774347981 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145648239 18.81% 18.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184522685 23.83% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209864984 27.10% 69.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131209019 16.94% 86.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70693972 9.13% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20392101 2.63% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8014841 1.03% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3879808 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182016 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145644273 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184515384 23.83% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209689604 27.08% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131356597 16.96% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70636694 9.12% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20383529 2.63% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8079794 1.04% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3860513 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181593 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774407665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774347981 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 140362 8.20% 8.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95230 5.57% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1159729 67.79% 81.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 315506 18.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 108798 6.48% 6.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95504 5.69% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1157743 69.01% 81.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315646 18.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866449380 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866498027 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644870 0.18% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419102646 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171123037 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644895 0.18% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419117526 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171123455 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459319933 # Type of FU issued -system.cpu.iq.rate 1.883865 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1710827 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001172 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676966203 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615362108 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443197913 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17845151 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9210352 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8546882 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451899562 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9131198 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215327027 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459383903 # Type of FU issued +system.cpu.iq.rate 1.884093 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1677691 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001150 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3677006053 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615499463 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443256661 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17839670 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9205608 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8545927 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451932919 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9128675 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215271062 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34428974 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58580 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245871 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12901231 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34436830 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58273 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245758 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12905531 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3337 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 100836 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3343 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 99974 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16992580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3019126 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 247748 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608802731 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4125538 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436941817 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179749373 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2524925 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 149083 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1915 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245871 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2268919 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473448 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3742367 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454001167 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416555573 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5318766 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17000959 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3021185 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 246438 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608872021 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125769 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436949673 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179753673 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2525299 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 148197 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1793 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245758 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2269874 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473729 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3743603 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454064480 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416571691 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5319423 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93683374 # number of nop insts executed -system.cpu.iew.exec_refs 587003910 # number of memory reference insts executed -system.cpu.iew.exec_branches 89035290 # Number of branches executed -system.cpu.iew.exec_stores 170448337 # Number of stores executed -system.cpu.iew.exec_rate 1.876999 # Inst execution rate -system.cpu.iew.wb_sent 1452626666 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451744795 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153395564 # num instructions producing a value -system.cpu.iew.wb_consumers 1204642088 # num instructions consuming a value +system.cpu.iew.exec_nop 93685275 # number of nop insts executed +system.cpu.iew.exec_refs 587019661 # number of memory reference insts executed +system.cpu.iew.exec_branches 89035299 # Number of branches executed +system.cpu.iew.exec_stores 170447970 # Number of stores executed +system.cpu.iew.exec_rate 1.877225 # Inst execution rate +system.cpu.iew.wb_sent 1452686018 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451802588 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153472607 # num instructions producing a value +system.cpu.iew.wb_consumers 1204727325 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874086 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957459 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874305 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957455 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119183948 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119253312 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3614513 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757415085 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966588 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509597 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3615826 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757347022 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966765 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509958 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240000251 31.69% 31.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275796766 36.41% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42566622 5.62% 73.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54725654 7.23% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19677570 2.60% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13283245 1.75% 85.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30556171 4.03% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10517669 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70291137 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240030131 31.69% 31.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275730182 36.41% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42558160 5.62% 73.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54684817 7.22% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19637761 2.59% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13291596 1.76% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30564343 4.04% 89.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10573009 1.40% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70277023 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757415085 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757347022 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -427,70 +427,70 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70291137 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70277023 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295766308 # The number of ROB reads -system.cpu.rob.rob_writes 3234429823 # The number of ROB writes -system.cpu.timesIdled 26016 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 233789 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295781723 # The number of ROB reads +system.cpu.rob.rob_writes 3234577019 # The number of ROB writes +system.cpu.timesIdled 25986 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 233857 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552846 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552846 # CPI: Total CPI of All Threads -system.cpu.ipc 1.808823 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.808823 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979081340 # number of integer regfile reads -system.cpu.int_regfile_writes 1275150411 # number of integer regfile writes -system.cpu.fp_regfile_reads 16965180 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491866 # number of floating regfile writes -system.cpu.misc_regfile_reads 592655969 # number of misc regfile reads +system.cpu.cpi 0.552803 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552803 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808962 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808962 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979163604 # number of integer regfile reads +system.cpu.int_regfile_writes 1275210426 # number of integer regfile writes +system.cpu.fp_regfile_reads 16962684 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491940 # number of floating regfile writes +system.cpu.misc_regfile_reads 592672173 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 200 # number of replacements -system.cpu.icache.tagsinuse 1035.615179 # Cycle average of tags in use -system.cpu.icache.total_refs 161931886 # Total number of references to valid blocks. +system.cpu.icache.replacements 197 # number of replacements +system.cpu.icache.tagsinuse 1035.819290 # Cycle average of tags in use +system.cpu.icache.total_refs 161939953 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121025.325859 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 121031.355007 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.615179 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505671 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505671 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161931886 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161931886 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161931886 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161931886 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161931886 # number of overall hits -system.cpu.icache.overall_hits::total 161931886 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1937 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1937 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1937 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1937 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1937 # number of overall misses -system.cpu.icache.overall_misses::total 1937 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 85579500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 85579500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 85579500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 85579500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 85579500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 85579500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161933823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161933823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161933823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161933823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161933823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161933823 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.819290 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505771 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505771 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161939953 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161939953 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161939953 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161939953 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161939953 # number of overall hits +system.cpu.icache.overall_hits::total 161939953 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses +system.cpu.icache.overall_misses::total 1943 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 84888000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 84888000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 84888000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 84888000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 84888000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 84888000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161941896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161941896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161941896 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161941896 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161941896 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161941896 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44181.466185 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44181.466185 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44181.466185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44181.466185 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43689.140504 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43689.140504 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43689.140504 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43689.140504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43689.140504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43689.140504 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -499,120 +499,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62434000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62434000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62434000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62434000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62434000 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5647 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21781 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21781 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1199 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26229 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1199 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26229 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27428 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44804000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389435638 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022148 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027932 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083000 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083000 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.895444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056619 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059037 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.895444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056619 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059037 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37367.806505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87552.976169 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76897.403577 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60713.091869 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60713.091869 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37367.806505 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65264.687636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64045.190754 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37367.806505 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65264.687636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64045.190754 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459222 # number of replacements -system.cpu.dcache.tagsinuse 4093.797620 # Cycle average of tags in use -system.cpu.dcache.total_refs 365142346 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463318 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 788.103087 # Average number of references to valid blocks. +system.cpu.dcache.replacements 459155 # number of replacements +system.cpu.dcache.tagsinuse 4093.797450 # Cycle average of tags in use +system.cpu.dcache.total_refs 365215439 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463251 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 788.374853 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 340173000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.797620 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.797450 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999462 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999462 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200185442 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200185442 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955585 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955585 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200258461 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200258461 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955659 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955659 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # 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number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46656274682 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46656274682 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201108514 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201108514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46662379136 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46662379136 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46662379136 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46662379136 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201181055 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201181055 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 367955330 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 367955330 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 367955330 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 367955330 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004590 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004590 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368027871 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368027871 # 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miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.685000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.685000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16875.796073 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16875.796073 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.007645 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007645 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007645 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007645 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15978.391904 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15978.391904 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16878.985000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16878.985000 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16578.269888 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16578.269888 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 588860 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35662 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.512254 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16583.691711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16583.691711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16583.691711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16583.691711 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 590874 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35646 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.576166 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443982 # number of writebacks -system.cpu.dcache.writebacks::total 443982 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722195 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 722195 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628797 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628797 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2350992 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2350992 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2350992 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2350992 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200877 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200877 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262434 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262434 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443878 # number of writebacks +system.cpu.dcache.writebacks::total 443878 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721765 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 721765 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628742 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628742 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2350507 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2350507 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4360853500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970194000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6970194000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970194000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6970194000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6972711500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6972711500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6972711500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6972711500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -785,16 +785,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13008.221449 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13008.221449 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16602.808706 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16602.808706 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.382689 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.382689 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16618.156355 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16618.156355 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 0f028aec2..bf240d79b 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:30:24 +gem5 compiled Mar 26 2013 15:13:59 +gem5 started Mar 27 2013 00:17:33 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -42,4 +42,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 607412415000 because target called exit() +Exiting @ tick 607388314000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index a8d281c59..a7b0854c3 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.607412 # Number of seconds simulated -sim_ticks 607412415000 # Number of ticks simulated -final_tick 607412415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607388 # Number of seconds simulated +sim_ticks 607388314000 # Number of ticks simulated +final_tick 607388314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59004 # Simulator instruction rate (inst/s) -host_op_rate 108719 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40726098 # Simulator tick rate (ticks/s) -host_mem_usage 295644 # Number of bytes of host memory used -host_seconds 14914.57 # Real time elapsed on the host +host_inst_rate 39851 # Simulator instruction rate (inst/s) +host_op_rate 73427 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27504625 # Simulator tick rate (ticks/s) +host_mem_usage 294932 # Number of bytes of host memory used +host_seconds 22083.13 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493927 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693248 # Number of bytes read from this memory -system.physmem.bytes_read::total 1750912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 57664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 57664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory -system.physmem.bytes_written::total 162176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 901 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26457 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27358 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94934 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2787641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2882575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94934 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94934 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 266995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 266995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 266995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94934 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2787641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3149570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27360 # Total number of read requests seen -system.physmem.writeReqs 2534 # Total number of write requests seen +system.physmem.bytes_read::cpu.inst 57920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693120 # Number of bytes read from this memory +system.physmem.bytes_read::total 1751040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 57920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57920 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory +system.physmem.bytes_written::total 162112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27360 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 95359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2787541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2882900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 95359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 95359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 266900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 266900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 266900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 95359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2787541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3149800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27361 # Total number of read requests seen +system.physmem.writeReqs 2533 # Total number of write requests seen system.physmem.cpureqs 29894 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1750912 # Total number of bytes read from memory -system.physmem.bytesWritten 162176 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1750912 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() +system.physmem.bytesRead 1751040 # Total number of bytes read from memory +system.physmem.bytesWritten 162112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1751040 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1742 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1710 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1656 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1655 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1713 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1717 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1739 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1751 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1735 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 161 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis @@ -77,26 +77,26 @@ system.physmem.perBankWrReqs::14 164 # Tr system.physmem.perBankWrReqs::15 159 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 607412402000 # Total gap between requests +system.physmem.totGap 607388300000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27360 # Categorize read packet sizes +system.physmem.readPktSize::6 27361 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2534 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 26889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2533 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 26894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -127,7 +127,7 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 88987000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 893982000 # Sum of mem lat for all requests -system.physmem.totBusLat 136800000 # Total cycles spent in databus access -system.physmem.totBankLat 668195000 # Total cycles spent in bank access -system.physmem.avgQLat 3252.45 # Average queueing delay per request -system.physmem.avgBankLat 24422.33 # Average bank access latency per request +system.physmem.totQLat 89920500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 894824250 # Sum of mem lat for all requests +system.physmem.totBusLat 136805000 # Total cycles spent in databus access +system.physmem.totBankLat 668098750 # Total cycles spent in bank access +system.physmem.avgQLat 3286.45 # Average queueing delay per request +system.physmem.avgBankLat 24417.92 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32674.78 # Average memory access latency +system.physmem.avgMemAccLat 32704.37 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s @@ -171,250 +171,250 @@ system.physmem.avgConsumedWrBW 0.27 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 13.09 # Average write queue length over time -system.physmem.readRowHits 16427 # Number of row buffer hits during reads -system.physmem.writeRowHits 1022 # Number of row buffer hits during writes -system.physmem.readRowHitRate 60.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.33 # Row buffer hit rate for writes -system.physmem.avgGap 20318873.42 # Average gap between requests -system.cpu.branchPred.lookups 158382296 # Number of BP lookups -system.cpu.branchPred.condPredicted 158382296 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 26387252 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 83381183 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83179505 # Number of BTB hits +system.physmem.avgWrQLen 12.62 # Average write queue length over time +system.physmem.readRowHits 16432 # Number of row buffer hits during reads +system.physmem.writeRowHits 1027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 60.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.54 # Row buffer hit rate for writes +system.physmem.avgGap 20318067.17 # Average gap between requests +system.cpu.branchPred.lookups 158363276 # Number of BP lookups +system.cpu.branchPred.condPredicted 158363276 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 26388177 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 84556073 # Number of BTB lookups +system.cpu.branchPred.BTBHits 84327975 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.758125 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.730241 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1214824831 # number of cpu cycles simulated +system.cpu.numCycles 1214776629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 179163349 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1457867613 # Number of instructions fetch has processed -system.cpu.fetch.Branches 158382296 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83179505 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 399005833 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88132062 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574704368 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 361 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 186835049 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10712979 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214462855 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.059159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.252870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 179085869 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1458535582 # Number of instructions fetch has processed +system.cpu.fetch.Branches 158363276 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84327975 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 399051382 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88177914 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574644515 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 339 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 188128638 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12060508 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214415274 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.253551 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 822674810 67.74% 67.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26926688 2.22% 69.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13135389 1.08% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20566511 1.69% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26637257 2.19% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18247973 1.50% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31504454 2.59% 79.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39098170 3.22% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215671603 17.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822580385 67.73% 67.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26905566 2.22% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13181581 1.09% 71.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20540967 1.69% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26638083 2.19% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18230799 1.50% 76.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31362370 2.58% 79.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39059510 3.22% 82.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215916013 17.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214462855 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130375 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.200064 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 288324734 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497934423 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 274040429 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92574368 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 61588901 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2343698812 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 61588901 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 336957337 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124218348 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2659 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 304046563 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387649047 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2248109589 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 354 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242721119 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120169480 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2618670353 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5724257672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5724251768 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5904 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1214415274 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130364 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.200662 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 288243803 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497890873 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274138871 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92508603 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 61633124 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2344113948 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 61633124 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 336916939 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124193279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2662 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 304031533 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387637737 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2248223321 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 352 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242707605 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120173474 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2618640021 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5724414358 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5724407502 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6856 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 731775093 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 91 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731348064 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 531825278 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219280996 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 342077982 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144753457 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1993869707 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 294 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1783892793 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 265772 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 371981386 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 760150327 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 245 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214462855 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.468874 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.421634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 731744761 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 86 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 731270344 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 531930252 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219281722 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 342004102 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144706308 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1994081706 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 268 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1783937479 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 271890 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 372188972 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 760599366 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 219 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1214415274 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.468968 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.421626 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360357006 29.67% 29.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 364326915 30.00% 59.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234272776 19.29% 78.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141367539 11.64% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60718828 5.00% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39723200 3.27% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11050512 0.91% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2045307 0.17% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 600772 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360308657 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364274837 30.00% 59.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234367873 19.30% 78.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141282709 11.63% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60755557 5.00% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39735013 3.27% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11052402 0.91% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2038744 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 599482 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214462855 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214415274 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 450048 15.52% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2249912 77.59% 93.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 199796 6.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 457362 15.66% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2260297 77.38% 93.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 203472 6.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812279 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065698440 59.74% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 478836274 26.84% 89.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192545800 10.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812177 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065743062 59.74% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478833230 26.84% 89.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192549010 10.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1783892793 # Type of FU issued -system.cpu.iq.rate 1.468436 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2899756 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4785413585 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2366027132 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1724688067 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 384 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1824 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1739980085 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 185 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209981192 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1783937479 # Type of FU issued +system.cpu.iq.rate 1.468531 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2921131 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001637 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4785482838 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2366447244 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1724674774 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 415 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2104 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740046229 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 204 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210002024 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 112783156 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38868 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 181899 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31094938 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 112888130 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 39196 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 182689 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31095664 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2165 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 66 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 61588901 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1215520 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 110006 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1993870001 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63340037 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 531825278 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219280996 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 53594 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2844 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 181899 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2045614 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24471458 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26517072 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766151616 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474571020 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17741177 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 61633124 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1215598 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 109803 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1994081974 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63261504 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 531930252 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219281722 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 80 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 53150 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2875 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 182689 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2045744 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24472235 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26517979 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766179614 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474605200 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17757865 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666290065 # number of memory reference insts executed -system.cpu.iew.exec_branches 110357109 # Number of branches executed -system.cpu.iew.exec_stores 191719045 # Number of stores executed -system.cpu.iew.exec_rate 1.453832 # Inst execution rate -system.cpu.iew.wb_sent 1725806864 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1724688166 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267103836 # num instructions producing a value -system.cpu.iew.wb_consumers 1828916065 # num instructions consuming a value +system.cpu.iew.exec_refs 666327456 # number of memory reference insts executed +system.cpu.iew.exec_branches 110355440 # Number of branches executed +system.cpu.iew.exec_stores 191722256 # Number of stores executed +system.cpu.iew.exec_rate 1.453913 # Inst execution rate +system.cpu.iew.wb_sent 1725787981 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1724674882 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267085899 # num instructions producing a value +system.cpu.iew.wb_consumers 1828860280 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.419701 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692817 # average fanout of values written-back +system.cpu.iew.wb_rate 1.419747 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692828 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 372377336 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 372589426 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26387302 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1152873954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.406480 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.829955 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26388224 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1152782150 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.406592 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.830218 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 418181253 36.27% 36.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 415089887 36.00% 72.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86977349 7.54% 79.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122167535 10.60% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24171647 2.10% 92.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25387316 2.20% 94.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16411129 1.42% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12045909 1.04% 97.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32441929 2.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 418160632 36.27% 36.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 415035897 36.00% 72.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86967576 7.54% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122159323 10.60% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24161943 2.10% 92.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25351733 2.20% 94.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16436685 1.43% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12048526 1.05% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32459835 2.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1152873954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152782150 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -425,195 +425,195 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32441929 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32459835 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3114303288 # The number of ROB reads -system.cpu.rob.rob_writes 4049366814 # The number of ROB writes -system.cpu.timesIdled 58967 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 361976 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3114405668 # The number of ROB reads +system.cpu.rob.rob_writes 4049835519 # The number of ROB writes +system.cpu.timesIdled 58880 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 361355 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.380443 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.380443 # CPI: Total CPI of All Threads -system.cpu.ipc 0.724405 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.724405 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3542727713 # number of integer regfile reads -system.cpu.int_regfile_writes 1974483700 # number of integer regfile writes -system.cpu.fp_regfile_reads 99 # number of floating regfile reads -system.cpu.misc_regfile_reads 910779890 # number of misc regfile reads +system.cpu.cpi 1.380388 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.380388 # CPI: Total CPI of All Threads +system.cpu.ipc 0.724434 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.724434 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3542838094 # number of integer regfile reads +system.cpu.int_regfile_writes 1974489722 # number of integer regfile writes +system.cpu.fp_regfile_reads 108 # number of floating regfile reads +system.cpu.misc_regfile_reads 910800153 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 814.738585 # Cycle average of tags in use -system.cpu.icache.total_refs 186833677 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 918 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 203522.523965 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 816.521748 # Cycle average of tags in use +system.cpu.icache.total_refs 188127242 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 922 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 204042.561822 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 814.738585 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.397822 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.397822 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 186833682 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 186833682 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 186833682 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 186833682 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 186833682 # number of overall hits -system.cpu.icache.overall_hits::total 186833682 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1367 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1367 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1367 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1367 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1367 # number of overall misses -system.cpu.icache.overall_misses::total 1367 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65166500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65166500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65166500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65166500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65166500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 186835049 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 186835049 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 186835049 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 186835049 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 186835049 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 186835049 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 816.521748 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.398692 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.398692 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 188127247 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 188127247 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 188127247 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 188127247 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 188127247 # number of overall hits +system.cpu.icache.overall_hits::total 188127247 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1391 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1391 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1391 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1391 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1391 # number of overall misses +system.cpu.icache.overall_misses::total 1391 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66285000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66285000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66285000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66285000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66285000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66285000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 188128638 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 188128638 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 188128638 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 188128638 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 188128638 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 188128638 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47671.177762 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47671.177762 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47671.177762 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47671.177762 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47671.177762 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47671.177762 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 146 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47652.767793 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47652.767793 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47652.767793 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47652.767793 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47652.767793 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47652.767793 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 175 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 444 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 444 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 444 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 444 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 308563497 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 860769620 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 860769620 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35335231 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1133997886 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1169333117 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35335231 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1133997886 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1169333117 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022376 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026678 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088897 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088897 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058781 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060659 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058781 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060659 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39217.792453 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59918.479386 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56503.112434 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39306.343669 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39306.343669 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39217.792453 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42858.682717 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42738.783516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39217.792453 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42858.682717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42738.783516 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27361 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27361 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35849736 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273446014 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 309295750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 860917120 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 860917120 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088892 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981562 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058765 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060651 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981562 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058765 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060651 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39612.967956 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60005.708580 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56626.830831 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39313.079136 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39313.079136 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39612.967956 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42877.348579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42769.375023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39612.967956 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42877.348579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42769.375023 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 446028 # number of replacements -system.cpu.dcache.tagsinuse 4092.714418 # Cycle average of tags in use -system.cpu.dcache.total_refs 452315129 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 450124 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1004.867834 # Average number of references to valid blocks. +system.cpu.dcache.replacements 446101 # number of replacements +system.cpu.dcache.tagsinuse 4092.714287 # Cycle average of tags in use +system.cpu.dcache.total_refs 452328275 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 450197 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1004.734094 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4092.714418 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4092.714287 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264375496 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264375496 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939628 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939628 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452315124 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452315124 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452315124 # number of overall hits -system.cpu.dcache.overall_hits::total 452315124 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 211166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 211166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246430 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246430 # 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number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452785941 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452785941 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses @@ -718,48 +718,48 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001011 system.cpu.dcache.demand_miss_rate::total 0.001011 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14308.475323 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14308.475323 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16708.016475 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16708.016475 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15600.704552 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15600.704552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15600.704552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15600.704552 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.461463 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.461463 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16709.227585 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16709.227585 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15600.238817 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15600.238817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15600.238817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15600.238817 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 388 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.473684 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.023256 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428982 # number of writebacks -system.cpu.dcache.writebacks::total 428982 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7377 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7377 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 87 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 87 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7464 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7464 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7464 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7464 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203789 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203789 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246343 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246343 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450132 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450132 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450132 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450132 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528052500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528052500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3623861000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3623861000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6151913500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6151913500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6151913500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6151913500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 429059 # number of writebacks +system.cpu.dcache.writebacks::total 429059 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7389 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7389 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 79 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 79 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7468 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7468 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7468 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7468 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203848 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203848 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246356 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246356 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450204 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450204 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450204 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450204 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2529010500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2529010500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3624235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3624235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6153246000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6153246000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6153246000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6153246000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -768,14 +768,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.245131 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.245131 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14710.631112 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14710.631112 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13666.909929 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13666.909929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13666.909929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13666.909929 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12406.354244 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12406.354244 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14711.375002 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14711.375002 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13667.683983 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13667.683983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13667.683983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13667.683983 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |