regressions: stats update due to decoder changes

1 files changed, 132 insertions, 132 deletions

diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
index d2efc8854..8b98b78ac 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.164568                       # Nu
 sim_ticks                                164568389500                       # Number of ticks simulated
 final_tick                               164568389500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 155967                       # Simulator instruction rate (inst/s)
-host_op_rate                                   164807                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               45026221                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230908                       # Number of bytes of host memory used
-host_seconds                                  3654.95                       # Real time elapsed on the host
+host_inst_rate                                 195675                       # Simulator instruction rate (inst/s)
+host_op_rate                                   206765                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56489453                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277972                       # Number of bytes of host memory used
+host_seconds                                  2913.26                       # Real time elapsed on the host
 sim_insts                                   570052720                       # Number of instructions simulated
 sim_ops                                     602360926                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             47104                       # Number of bytes read from this memory
@@ -502,7 +502,7 @@ system.cpu.ipc_total                         1.731963                       # IP
 system.cpu.int_regfile_reads               3204362065                       # number of integer regfile reads
 system.cpu.int_regfile_writes               663044095                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               901644614                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               234776328                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   3110                       # number of misc regfile writes
 system.cpu.icache.replacements                     60                       # number of replacements
 system.cpu.icache.tagsinuse                685.359263                       # Cycle average of tags in use
@@ -588,6 +588,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47143.901220
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47143.901220                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 47143.901220                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 440681                       # number of replacements
+system.cpu.dcache.tagsinuse               4091.500678                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                197565955                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 444777                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 444.191033                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              320845000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4091.500678                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.998902                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.998902                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    131517978                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       131517978                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     66044747                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       66044747                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         1676                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         1676                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         1554                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         1554                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     197562725                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        197562725                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    197562725                       # number of overall hits
+system.cpu.dcache.overall_hits::total       197562725                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       342017                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        342017                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3372784                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3372784                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           22                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           22                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      3714801                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3714801                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3714801                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3714801                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5159651000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5159651000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  40250551202                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  40250551202                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       339000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       339000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  45410202202                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  45410202202                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  45410202202                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  45410202202                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    131859995                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    131859995                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         1698                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         1698                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         1554                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         1554                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    201277526                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    201277526                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    201277526                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    201277526                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002594                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002594                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.048587                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.048587                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.012956                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.012956                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.018456                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.018456                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.018456                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.018456                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.948944                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.948944                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.924972                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.924972                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127807                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12224.127807                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127807                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12224.127807                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       131795                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           20                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              5078                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    25.954116                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           10                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       421636                       # number of writebacks
+system.cpu.dcache.writebacks::total            421636                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       144398                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       144398                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3125625                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3125625                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           22                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           22                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3270023                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3270023                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3270023                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3270023                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       197619                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       197619                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       247159                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       247159                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       444778                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       444778                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       444778                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       444778                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2875780500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2875780500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4060483756                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4060483756                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6936264256                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6936264256                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6936264256                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6936264256                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001499                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001499                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003560                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.003560                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002210                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002210                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002210                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002210                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                  2559                       # number of replacements
 system.cpu.l2cache.tagsinuse             22365.188889                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  517231                       # Total number of references to valid blocks.
@@ -735,131 +861,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37150.370924
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.918108                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.125531                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 440681                       # number of replacements
-system.cpu.dcache.tagsinuse               4091.500678                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                197565955                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 444777                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 444.191033                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              320845000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4091.500678                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.998902                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.998902                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    131517978                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       131517978                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     66044747                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       66044747                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         1676                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         1676                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         1554                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         1554                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     197562725                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        197562725                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    197562725                       # number of overall hits
-system.cpu.dcache.overall_hits::total       197562725                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       342017                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        342017                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3372784                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3372784                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           22                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           22                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3714801                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3714801                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3714801                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3714801                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5159651000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5159651000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  40250551202                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  40250551202                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       339000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       339000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  45410202202                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  45410202202                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  45410202202                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  45410202202                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    131859995                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    131859995                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     69417531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     69417531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         1698                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         1698                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         1554                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         1554                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    201277526                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    201277526                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    201277526                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    201277526                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002594                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002594                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.048587                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.048587                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.012956                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.012956                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.018456                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.018456                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.018456                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.018456                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.948944                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.948944                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.924972                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.924972                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127807                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12224.127807                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127807                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12224.127807                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       131795                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           20                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              5078                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    25.954116                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           10                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       421636                       # number of writebacks
-system.cpu.dcache.writebacks::total            421636                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       144398                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       144398                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3125625                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3125625                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           22                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           22                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3270023                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3270023                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3270023                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3270023                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       197619                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       197619                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       247159                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       247159                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       444778                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       444778                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       444778                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       444778                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2875780500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2875780500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4060483756                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4060483756                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6936264256                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6936264256                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6936264256                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6936264256                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001499                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001499                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003560                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.003560                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002210                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002210                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002210                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002210                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------