diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-01-08 08:54:16 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-01-08 08:54:16 -0500 |
| commit | fbeced6135151cc70f83b95603589bcca53f3efc (patch) | |
| tree | cb8a877be1970b24d2eca0851fa5bfe5f5bca340 /tests/long/se/00.gzip/ref | |
| parent | 25efbb5bdcc037826aac4ee2c9604dabb70e0ee5 (diff) | |
| download | gem5-fbeced6135151cc70f83b95603589bcca53f3efc.tar.xz | |
stats: update stats for previous six changes
Diffstat (limited to 'tests/long/se/00.gzip/ref')
| -rw-r--r-- | tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt | 1190 |
1 files changed, 597 insertions, 593 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 650fe9ea1..3adbcac4f 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164568 # Number of seconds simulated -sim_ticks 164568389500 # Number of ticks simulated -final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164543 # Number of seconds simulated +sim_ticks 164543008000 # Number of ticks simulated +final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61098 # Simulator instruction rate (inst/s) -host_op_rate 64561 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17638362 # Simulator tick rate (ticks/s) -host_mem_usage 233000 # Number of bytes of host memory used -host_seconds 9330.14 # Real time elapsed on the host -sim_insts 570052720 # Number of instructions simulated -sim_ops 602360926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1702080 # Number of bytes read from this memory -system.physmem.bytes_read::total 1749184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory -system.physmem.bytes_written::total 162368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 736 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26595 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27331 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 286228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10342691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10628919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 286228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 286228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 986629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 986629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 986629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 286228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10342691 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11615548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27332 # Total number of read requests seen -system.physmem.writeReqs 2537 # Total number of write requests seen -system.physmem.cpureqs 29869 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1749184 # Total number of bytes read from memory -system.physmem.bytesWritten 162368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1749184 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() +host_inst_rate 153982 # Simulator instruction rate (inst/s) +host_op_rate 162709 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44446364 # Simulator tick rate (ticks/s) +host_mem_usage 244392 # Number of bytes of host memory used +host_seconds 3702.06 # Real time elapsed on the host +sim_insts 570051585 # Number of instructions simulated +sim_ops 602359791 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1700992 # Number of bytes read from this memory +system.physmem.bytes_read::total 1747904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162560 # Number of bytes written to this memory +system.physmem.bytes_written::total 162560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26578 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2540 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2540 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 285105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10337674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10622779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 285105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 285105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 987948 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 987948 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 987948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 285105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10337674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11610727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27312 # Total number of read requests seen +system.physmem.writeReqs 2540 # Total number of write requests seen +system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1747904 # Total number of bytes read from memory +system.physmem.bytesWritten 162560 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1747904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162560 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1706 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1733 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1745 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1741 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1718 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 157 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 164 # Tr system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164568372500 # Total gap between requests +system.physmem.totGap 164542992000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27332 # Categorize read packet sizes +system.physmem.readPktSize::6 27312 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2537 # categorize write packet sizes +system.physmem.writePktSize::6 2540 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 785 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -145,9 +145,9 @@ system.physmem.wrQLenPdf::3 111 # Wh system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 953339495 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1657961495 # Sum of mem lat for all requests -system.physmem.totBusLat 109328000 # Total cycles spent in databus access -system.physmem.totBankLat 595294000 # Total cycles spent in bank access -system.physmem.avgQLat 34879.98 # Average queueing delay per request -system.physmem.avgBankLat 21780.11 # Average bank access latency per request +system.physmem.totQLat 954202972 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1658730972 # Sum of mem lat for all requests +system.physmem.totBusLat 109248000 # Total cycles spent in databus access +system.physmem.totBankLat 595280000 # Total cycles spent in bank access +system.physmem.avgQLat 34937.13 # Average queueing delay per request +system.physmem.avgBankLat 21795.55 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 60660.09 # Average memory access latency -system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 60732.68 # Average memory access latency +system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 6.05 # Average write queue length over time -system.physmem.readRowHits 17765 # Number of row buffer hits during reads -system.physmem.writeRowHits 1091 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes -system.physmem.avgGap 5509671.31 # Average gap between requests +system.physmem.avgWrQLen 7.51 # Average write queue length over time +system.physmem.readRowHits 17750 # Number of row buffer hits during reads +system.physmem.writeRowHits 1096 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes +system.physmem.avgGap 5511958.73 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,141 +235,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329136780 # number of cpu cycles simulated +system.cpu.numCycles 329086017 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85146783 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 79928286 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2342158 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47212748 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46871026 # Number of BTB hits +system.cpu.BPredUnit.lookups 85130885 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 79914937 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2339051 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47115734 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46860934 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68501012 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119329476 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67084221 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755002 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328178875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1427305 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 879 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48288239 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129602885 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13082707 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119327277 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 198 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67069040 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 754631 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328130780 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193984 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198558186 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8890662 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9436402 2.88% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4398507 1.34% 79.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5788329 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60883054 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198528126 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20911347 6.37% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4965496 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14342607 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8889042 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9432606 2.87% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4398382 1.34% 79.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5787527 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60875647 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328178875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96199179 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4737184 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1561 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703240498 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5895 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10725676 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114043085 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694816428 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 328130780 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258689 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92913811 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96211222 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107901766 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20387668 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10716313 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4735353 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1507 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703148359 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5732 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10716313 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107108772 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14420824 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39598 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114018818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81826455 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694730633 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721301805 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230529005 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230528877 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 59350869 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20332423 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 690 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721206841 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230143140 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230143012 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93882616 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172202980 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80458110 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21583677 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28704390 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 679987725 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3320 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645601186 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1370428 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328178875 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 93789468 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1631 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1577 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170614097 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172186244 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80451329 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21497797 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28523197 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 679922328 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2842 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645571900 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1371428 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77382290 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193030922 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 138 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328130780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967423 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.726248 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68164684 20.77% 20.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28810425 8.78% 91.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14904242 4.54% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5586841 1.70% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6537919 1.99% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2116297 0.64% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68155781 20.77% 20.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85368264 26.02% 46.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75828661 23.11% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40814489 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28806063 8.78% 91.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14910916 4.54% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5593541 1.70% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6461751 1.97% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2191314 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328178875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328130780 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2691247 71.35% 77.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 863918 22.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 217275 5.77% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2690091 71.47% 77.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 856746 22.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403371869 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403353378 62.48% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued @@ -398,279 +398,283 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165559477 25.64% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76663269 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165552451 25.64% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76659500 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645601186 # Type of FU issued -system.cpu.iq.rate 1.961498 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624523749 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645571900 # Type of FU issued +system.cpu.iq.rate 1.961712 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3764112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005831 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624410084 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757319559 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637543970 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649373276 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649335992 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30369655 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30371258 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23250160 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123060 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10236870 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23233651 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 124604 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12357 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10230316 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12923 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32784 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12884 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 32539 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10725676 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 690728 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32845 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16029 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1358556 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460812 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2819368 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641523461 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163490704 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4077725 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10716313 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 798788 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 92055 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 679928215 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 686727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172186244 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80451329 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1514 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 33028 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15856 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12357 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1355593 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460304 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2815897 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641504035 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163487420 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4067865 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3107 # number of nop insts executed -system.cpu.iew.exec_refs 239380202 # number of memory reference insts executed -system.cpu.iew.exec_branches 74672586 # Number of branches executed -system.cpu.iew.exec_stores 75889498 # Number of stores executed -system.cpu.iew.exec_rate 1.949109 # Inst execution rate -system.cpu.iew.wb_sent 638973087 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637563068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418509904 # num instructions producing a value -system.cpu.iew.wb_consumers 649810327 # num instructions consuming a value +system.cpu.iew.exec_nop 3045 # number of nop insts executed +system.cpu.iew.exec_refs 239375677 # number of memory reference insts executed +system.cpu.iew.exec_branches 74669000 # Number of branches executed +system.cpu.iew.exec_stores 75888257 # Number of stores executed +system.cpu.iew.exec_rate 1.949351 # Inst execution rate +system.cpu.iew.wb_sent 638951120 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637543986 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418515101 # num instructions producing a value +system.cpu.iew.wb_consumers 649819096 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937076 # insts written-back per cycle +system.cpu.iew.wb_rate 1.937317 # insts written-back per cycle system.cpu.iew.wb_fanout 0.644049 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77641136 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2340694 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317453199 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897480 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237382 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 77576557 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2337624 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317414467 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897708 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237617 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93244159 29.37% 29.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104350587 32.87% 62.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42987524 13.54% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8793922 2.77% 78.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25958876 8.18% 86.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12900336 4.06% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7627072 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1171824 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20418899 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93227454 29.37% 29.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104339541 32.87% 62.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42982023 13.54% 75.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8785495 2.77% 78.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25936003 8.17% 86.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12920810 4.07% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7630828 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1171764 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20420549 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317453199 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052771 # Number of instructions committed -system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 317414467 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570051636 # Number of instructions committed +system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174060 # Number of memory references committed -system.cpu.commit.loads 148952820 # Number of loads committed +system.cpu.commit.refs 219173606 # Number of memory references committed +system.cpu.commit.loads 148952593 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70892751 # Number of branches committed +system.cpu.commit.branches 70892524 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20418899 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20420549 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 977035801 # The number of ROB reads -system.cpu.rob.rob_writes 1370761733 # The number of ROB writes -system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 957905 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052720 # Number of Instructions Simulated -system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated -system.cpu.cpi 0.577380 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577380 # CPI: Total CPI of All Threads -system.cpu.ipc 1.731963 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.731963 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204362065 # number of integer regfile reads -system.cpu.int_regfile_writes 663044095 # number of integer regfile writes +system.cpu.rob.rob_reads 976929705 # The number of ROB reads +system.cpu.rob.rob_writes 1370620821 # The number of ROB writes +system.cpu.timesIdled 41180 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 955237 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570051585 # Number of Instructions Simulated +system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated +system.cpu.cpi 0.577292 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577292 # CPI: Total CPI of All Threads +system.cpu.ipc 1.732227 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.732227 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204271897 # number of integer regfile reads +system.cpu.int_regfile_writes 663022837 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234776328 # number of misc regfile reads -system.cpu.misc_regfile_writes 3110 # number of misc regfile writes -system.cpu.icache.replacements 60 # number of replacements -system.cpu.icache.tagsinuse 685.359263 # Cycle average of tags in use -system.cpu.icache.total_refs 67083066 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 81808.617073 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 234769906 # number of misc regfile reads +system.cpu.misc_regfile_writes 2656 # number of misc regfile writes +system.cpu.icache.replacements 58 # number of replacements +system.cpu.icache.tagsinuse 683.079303 # Cycle average of tags in use +system.cpu.icache.total_refs 67067899 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 817 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 82090.451652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 685.359263 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.334648 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.334648 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67083066 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67083066 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67083066 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits -system.cpu.icache.overall_hits::total 67083066 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1155 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1155 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1155 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1155 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1155 # number of overall misses -system.cpu.icache.overall_misses::total 1155 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51421999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51421999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51421999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51421999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51421999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51421999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67084221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67084221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67084221 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67084221 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67084221 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67084221 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 683.079303 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.333535 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.333535 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67067899 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67067899 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67067899 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67067899 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67067899 # number of overall hits +system.cpu.icache.overall_hits::total 67067899 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses +system.cpu.icache.overall_misses::total 1141 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51270999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51270999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51270999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51270999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51270999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51270999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67069040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67069040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67069040 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67069040 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67069040 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67069040 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44521.211255 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44521.211255 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44521.211255 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44521.211255 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44935.143734 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44935.143734 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44935.143734 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44935.143734 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.428571 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.555556 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 335 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 335 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 335 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 335 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 335 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38656999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38656999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38656999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38656999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38656999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38656999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 322 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 322 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 322 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 322 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 322 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39128499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39128499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39128499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39128499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39128499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39128499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47142.681707 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47142.681707 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47775.945055 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47775.945055 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47775.945055 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47775.945055 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47775.945055 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47775.945055 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2559 # number of replacements -system.cpu.l2cache.tagsinuse 22365.188888 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24170 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.399710 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2562 # number of replacements +system.cpu.l2cache.tagsinuse 22345.080888 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517383 # 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number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 192886 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 421636 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 421636 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225369 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225369 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 81 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 418174 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 418255 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 81 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 418174 # number of overall hits -system.cpu.l2cache.overall_hits::total 418255 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 739 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4814 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088160 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061308 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061308 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38041.822647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139474.739612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126010.355668 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58459.975493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58459.975493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440681 # number of replacements -system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use -system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits -system.cpu.dcache.overall_hits::total 197562725 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses -system.cpu.dcache.overall_misses::total 3714801 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159649500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5159649500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250552202 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40250552202 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45410201702 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45410201702 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998901 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131514845 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131514845 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66043576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66043576 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1323 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1323 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 197558421 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197558421 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197558421 # number of overall hits +system.cpu.dcache.overall_hits::total 197558421 # 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number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40277017700 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 312000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 312000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45431972700 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45431972700 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45431972700 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45431972700 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131856643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131856643 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.944558 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.944558 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.925268 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.925268 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12224.127673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12224.127673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201274174 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201274174 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201274174 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201274174 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048604 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048604 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.014892 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.014892 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018461 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018461 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018461 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018461 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15081.875845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15081.875845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11937.627414 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 11937.627414 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15600 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15600 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12226.854880 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12226.854880 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 132982 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4828 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.543911 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks -system.cpu.dcache.writebacks::total 421636 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060484256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060484256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.143266 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.143266 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.631998 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.631998 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 421606 # number of writebacks +system.cpu.dcache.writebacks::total 421606 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144292 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144292 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3126791 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3126791 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 20 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 20 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3271083 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3271083 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3271083 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3271083 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247164 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247164 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444670 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444670 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444670 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444670 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2876994000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2876994000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4061058256 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4061058256 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6938052256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6938052256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6938052256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6938052256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14566.615698 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14566.615698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16430.622000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16430.622000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |