diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
| commit | 3c666083c6f5fecc38699a6f0c5f4f25b23e18c9 (patch) | |
| tree | e554e37e76714f9ae9c9faa07ef645db0f9a6d93 /tests/long/se/00.gzip | |
| parent | 8e2a8fbb7e4751260c88fccd19ebe8d1138d0695 (diff) | |
| download | gem5-3c666083c6f5fecc38699a6f0c5f4f25b23e18c9.tar.xz | |
ARM: Update stats for IT and conditional branch changes
Diffstat (limited to 'tests/long/se/00.gzip')
9 files changed, 533 insertions, 517 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 5d521d8ff..043132ebd 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -514,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 2783a8301..35fcd0232 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:26 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:38:16 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164277874000 because target called exit() +Exiting @ tick 164248292500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 46c526502..8bc0cbb1b 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164278 # Number of seconds simulated -sim_ticks 164277874000 # Number of ticks simulated -final_tick 164277874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164248 # Number of seconds simulated +sim_ticks 164248292500 # Number of ticks simulated +final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 203470 # Simulator instruction rate (inst/s) -host_op_rate 215002 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58636208 # Simulator tick rate (ticks/s) -host_mem_usage 227276 # Number of bytes of host memory used -host_seconds 2801.65 # Real time elapsed on the host -sim_insts 570051643 # Number of instructions simulated -sim_ops 602359850 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5845952 # Number of bytes read from this memory -system.physmem.bytes_inst_read 50048 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3721408 # Number of bytes written to this memory -system.physmem.num_reads 91343 # Number of read requests responded to by this memory -system.physmem.num_writes 58147 # Number of write requests responded to by this memory +host_inst_rate 250614 # Simulator instruction rate (inst/s) +host_op_rate 264817 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72208895 # Simulator tick rate (ticks/s) +host_mem_usage 224524 # Number of bytes of host memory used +host_seconds 2274.63 # Real time elapsed on the host +sim_insts 570052728 # Number of instructions simulated +sim_ops 602360935 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 5850432 # Number of bytes read from this memory +system.physmem.bytes_inst_read 51136 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3722112 # Number of bytes written to this memory +system.physmem.num_reads 91413 # Number of read requests responded to by this memory +system.physmem.num_writes 58158 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 35585754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 304655 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 22653130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 58238884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 35619439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 311334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 22661496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 58280935 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,141 +64,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 328555749 # number of cpu cycles simulated +system.cpu.numCycles 328496586 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85495228 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80299392 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2363839 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47188450 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46808758 # Number of BTB hits +system.cpu.BPredUnit.lookups 85500889 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80301573 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2363462 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47194810 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46809578 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1441266 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2064 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68932526 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669692235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85495228 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48250024 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130038876 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13469589 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 117716369 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67498352 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 807371 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 327717199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.177607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.200173 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1441693 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2047 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68928725 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669724193 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85500889 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48251271 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130040939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13471504 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117632066 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 466 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67495318 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807242 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 327633093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.178244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.200456 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 197678537 60.32% 60.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20955398 6.39% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4944268 1.51% 68.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14317146 4.37% 72.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8982056 2.74% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9405272 2.87% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4386310 1.34% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5814100 1.77% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61234112 18.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 197592366 60.31% 60.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20955363 6.40% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4944852 1.51% 68.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14316797 4.37% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8978717 2.74% 75.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9406752 2.87% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4386482 1.34% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5812411 1.77% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61239353 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 327717199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260215 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.038291 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93143264 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94872868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108628769 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20045238 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11027060 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4784060 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1759 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 705973468 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5432 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11027060 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107429081 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13945008 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 118563 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114317154 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80880333 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697178999 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 231 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59283430 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19375407 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 624 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723780453 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241174730 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241174602 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 327633093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260279 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.038755 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93122772 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94805335 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108615724 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20060132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11029130 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4785077 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1812 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 705993706 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5866 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11029130 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107405098 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13994903 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53643 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114322395 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80827924 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697209083 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59229209 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19383033 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 653 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723812839 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241314962 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241314834 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417466 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96362987 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11553 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11552 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169904976 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172902366 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80616631 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21434396 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 27805052 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681951411 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9116 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646829241 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1424329 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79415012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197703011 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 327717199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.973742 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.738606 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419202 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96393637 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6694 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6687 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169956085 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172904405 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80621547 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21577919 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28225780 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681971655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4856 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646826004 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1423990 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79433587 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197870891 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 327633093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.974239 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.736392 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68508405 20.90% 20.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84956160 25.92% 46.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75144846 22.93% 69.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40581693 12.38% 82.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28626833 8.74% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15169754 4.63% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5928523 1.81% 97.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6496810 1.98% 99.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2304175 0.70% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68428283 20.89% 20.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84743637 25.87% 46.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75345420 23.00% 69.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40565003 12.38% 82.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28664322 8.75% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15213545 4.64% 95.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5876273 1.79% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6659013 2.03% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2137597 0.65% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 327717199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 327633093 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 204843 5.11% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2907010 72.53% 77.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 896423 22.36% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205009 5.12% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2904405 72.49% 77.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 897167 22.39% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403920439 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403920644 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -226,153 +226,153 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166108811 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76793420 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166111461 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76787311 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646829241 # Type of FU issued -system.cpu.iq.rate 1.968705 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4008276 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006197 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1626808250 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761386923 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638549644 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646826004 # Type of FU issued +system.cpu.iq.rate 1.969049 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4006581 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006194 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1626715636 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761421594 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638533475 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650837497 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650832565 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30424903 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30420680 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23949762 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 129784 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11648 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10395608 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23951584 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 127945 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11724 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10400307 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12818 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12531 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12832 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12549 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11027060 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 853408 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 62572 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682026706 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 660555 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172902366 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80616631 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6245 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11648 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1315368 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1582506 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2897874 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642687405 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163985784 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4141836 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11029130 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 827373 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 62655 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682042744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 662438 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172904405 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80621547 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3504 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13090 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6258 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11724 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1313555 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1583724 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2897279 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642671991 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163979527 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4154013 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66179 # number of nop insts executed -system.cpu.iew.exec_refs 239997187 # number of memory reference insts executed -system.cpu.iew.exec_branches 74667058 # Number of branches executed -system.cpu.iew.exec_stores 76011403 # Number of stores executed -system.cpu.iew.exec_rate 1.956098 # Inst execution rate -system.cpu.iew.wb_sent 640040588 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638549660 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420197588 # num instructions producing a value -system.cpu.iew.wb_consumers 654962025 # num instructions consuming a value +system.cpu.iew.exec_nop 66233 # number of nop insts executed +system.cpu.iew.exec_refs 239982954 # number of memory reference insts executed +system.cpu.iew.exec_branches 74668739 # Number of branches executed +system.cpu.iew.exec_stores 76003427 # Number of stores executed +system.cpu.iew.exec_rate 1.956404 # Inst execution rate +system.cpu.iew.wb_sent 640027985 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638533491 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420151811 # num instructions producing a value +system.cpu.iew.wb_consumers 654946950 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.943505 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.641560 # average fanout of values written-back +system.cpu.iew.wb_rate 1.943806 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641505 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570051694 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602359901 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 79676133 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6355 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2424230 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 316690140 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.902048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.239406 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570052779 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602360986 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79691237 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2423863 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 316603964 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.902569 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.239613 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 92731092 29.28% 29.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104002875 32.84% 62.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43058477 13.60% 75.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8922442 2.82% 78.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25674548 8.11% 86.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13103987 4.14% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7582493 2.39% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1154147 0.36% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20460079 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92664555 29.27% 29.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103983968 32.84% 62.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43054287 13.60% 75.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8920631 2.82% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25673085 8.11% 86.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13110941 4.14% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7578873 2.39% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1154724 0.36% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20462900 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 316690140 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570051694 # Number of instructions committed -system.cpu.commit.committedOps 602359901 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 316603964 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052779 # Number of instructions committed +system.cpu.commit.committedOps 602360986 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173627 # Number of memory references committed -system.cpu.commit.loads 148952604 # Number of loads committed +system.cpu.commit.refs 219174061 # Number of memory references committed +system.cpu.commit.loads 148952821 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828611 # Number of branches committed +system.cpu.commit.branches 70828828 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522679 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523547 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20460079 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20462900 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 978265483 # The number of ROB reads -system.cpu.rob.rob_writes 1375131668 # The number of ROB writes -system.cpu.timesIdled 36876 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 838550 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570051643 # Number of Instructions Simulated -system.cpu.committedOps 602359850 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570051643 # Number of Instructions Simulated -system.cpu.cpi 0.576361 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.576361 # CPI: Total CPI of All Threads -system.cpu.ipc 1.735023 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.735023 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210434144 # number of integer regfile reads -system.cpu.int_regfile_writes 664206400 # number of integer regfile writes +system.cpu.rob.rob_reads 978192675 # The number of ROB reads +system.cpu.rob.rob_writes 1375166180 # The number of ROB writes +system.cpu.timesIdled 37006 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 863493 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052728 # Number of Instructions Simulated +system.cpu.committedOps 602360935 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052728 # Number of Instructions Simulated +system.cpu.cpi 0.576256 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.576256 # CPI: Total CPI of All Threads +system.cpu.ipc 1.735338 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.735338 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210352058 # number of integer regfile reads +system.cpu.int_regfile_writes 664199500 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905030713 # number of misc regfile reads -system.cpu.misc_regfile_writes 2676 # number of misc regfile writes -system.cpu.icache.replacements 62 # number of replacements -system.cpu.icache.tagsinuse 695.805278 # Cycle average of tags in use -system.cpu.icache.total_refs 67497251 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 819 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 82414.225885 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905055598 # number of misc regfile reads +system.cpu.misc_regfile_writes 3110 # number of misc regfile writes +system.cpu.icache.replacements 66 # number of replacements +system.cpu.icache.tagsinuse 704.852693 # Cycle average of tags in use +system.cpu.icache.total_refs 67494169 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 836 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 80734.651914 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 695.805278 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.339749 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.339749 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67497251 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67497251 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67497251 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67497251 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67497251 # number of overall hits -system.cpu.icache.overall_hits::total 67497251 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1101 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1101 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1101 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1101 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1101 # number of overall misses -system.cpu.icache.overall_misses::total 1101 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37785500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37785500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37785500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37785500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37785500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37785500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67498352 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67498352 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67498352 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67498352 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67498352 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67498352 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34319.255223 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 704.852693 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.344166 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.344166 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67494169 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67494169 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67494169 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67494169 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67494169 # number of overall hits +system.cpu.icache.overall_hits::total 67494169 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1149 # 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Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 88231000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.647718 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999670 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 132066425 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 132066425 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 67860846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 67860846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1466 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1466 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1337 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1337 # 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Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87177000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.673413 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999676 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999676 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 132064751 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 132064751 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 67849620 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 67849620 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1690 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1690 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1554 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2847382500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24334000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2823048500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2847382500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235918 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203691 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203691 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31117.647059 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31081.566549 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31223.434364 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 799 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32297 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33096 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58317 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58317 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 799 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90614 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91413 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 799 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90614 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91413 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24875000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1003961000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028836000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1821234000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1821234000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24875000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2825195000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2850070000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24875000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2825195000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2850070000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163537 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235994 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31132.665832 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31085.271078 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31229.898657 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index f06b9ec67..867a31b3a 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index d3f3c8cc8..fda635c2d 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:43:07 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:54:39 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index f3821c915..1d050592c 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu sim_ticks 301191370000 # Number of ticks simulated final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3323130 # Simulator instruction rate (inst/s) -host_op_rate 3511472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1755802369 # Simulator tick rate (ticks/s) -host_mem_usage 216428 # Number of bytes of host memory used -host_seconds 171.54 # Real time elapsed on the host +host_inst_rate 2848986 # Simulator instruction rate (inst/s) +host_op_rate 3010454 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1505284316 # Simulator tick rate (ticks/s) +host_mem_usage 213580 # Number of bytes of host memory used +host_seconds 200.09 # Real time elapsed on the host sim_insts 570051644 # Number of instructions simulated sim_ops 602359851 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2680160157 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 602359851 # Nu system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 14843a60a..877a85204 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -183,7 +183,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index eee2e0cb2..25af6cb73 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:45:54 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:58:09 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 52945d306..f70524856 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.796763 # Nu sim_ticks 796762926000 # Number of ticks simulated final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1880906 # Simulator instruction rate (inst/s) -host_op_rate 1986306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2635941289 # Simulator tick rate (ticks/s) -host_mem_usage 225340 # Number of bytes of host memory used -host_seconds 302.27 # Real time elapsed on the host +host_inst_rate 2008356 # Simulator instruction rate (inst/s) +host_op_rate 2120897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2814551305 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 283.09 # Real time elapsed on the host sim_insts 568539343 # Number of instructions simulated sim_ops 600398281 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5759488 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 600398281 # Nu system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read |