diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/long/se/00.gzip | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/long/se/00.gzip')
5 files changed, 1413 insertions, 1488 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 7484e6ff9..c659f4312 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.269672 # Nu sim_ticks 269671683500 # Number of ticks simulated final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125294 # Simulator instruction rate (inst/s) -host_op_rate 125294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56139844 # Simulator tick rate (ticks/s) -host_mem_usage 224468 # Number of bytes of host memory used -host_seconds 4803.57 # Real time elapsed on the host +host_inst_rate 149368 # Simulator instruction rate (inst/s) +host_op_rate 149368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66926769 # Simulator tick rate (ticks/s) +host_mem_usage 224496 # Number of bytes of host memory used +host_seconds 4029.35 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 26294 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1014 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1014 # Categorize write packet sizes system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 384531397 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests +system.physmem.totQLat 383646750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1095736750 # Sum of mem lat for all requests system.physmem.totBusLat 131400000 # Total cycles spent in databus access -system.physmem.totBankLat 580703750 # Total cycles spent in bank access -system.physmem.avgQLat 14632.09 # Average queueing delay per request -system.physmem.avgBankLat 22096.79 # Average bank access latency per request +system.physmem.totBankLat 580690000 # Total cycles spent in bank access +system.physmem.avgQLat 14598.43 # Average queueing delay per request +system.physmem.avgBankLat 22096.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41728.89 # Average memory access latency +system.physmem.avgMemAccLat 41694.70 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -379,14 +364,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.116549 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22879.116891 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.482794 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.953898 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.679858 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21684.482898 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.953897 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.680097 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy @@ -418,14 +403,14 @@ system.cpu.l2cache.overall_misses::total 26294 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199043000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1198171500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1198171500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1669703000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1714784000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1668831500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1713912500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1669703000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1714784000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1668831500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1713912500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -453,14 +438,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.057631 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56219.195424 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56178.333646 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56178.333646 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65182.646231 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65182.646231 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34645117 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418280186 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452925303 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 933604040 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 933604040 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34645117 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1351884226 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1386529343 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34645117 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1351884226 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1386529343 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34644438 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418276481 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452920919 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932715801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932715801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34644438 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350992282 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1385636720 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34644438 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350992282 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1385636720 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -504,25 +489,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41195.145065 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101401.257212 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91205.256343 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43773.632783 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43773.632783 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41194.337693 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.359030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91204.373540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43731.986168 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43731.986168 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.423527 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4093.423689 # Cycle average of tags in use system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 332210000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.423527 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.423689 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits @@ -543,12 +528,12 @@ system.cpu.dcache.overall_misses::cpu.data 2179204 # system.cpu.dcache.overall_misses::total 2179204 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23175803000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23175803000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29160484000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29160484000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29160484000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29160484000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23170641500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23170641500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29155322500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29155322500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29155322500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29155322500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -567,12 +552,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12976.569635 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12976.569635 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13381.254807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.679613 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.679613 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13378.886281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13378.886281 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked @@ -601,12 +586,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 455395 system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -617,12 +602,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index fd6611525..80e818735 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133806 # Number of seconds simulated -sim_ticks 133806308500 # Number of ticks simulated -final_tick 133806308500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133774 # Number of seconds simulated +sim_ticks 133773851500 # Number of ticks simulated +final_tick 133773851500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271409 # Simulator instruction rate (inst/s) -host_op_rate 271409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64213833 # Simulator tick rate (ticks/s) -host_mem_usage 226532 # Number of bytes of host memory used -host_seconds 2083.76 # Real time elapsed on the host +host_inst_rate 262576 # Simulator instruction rate (inst/s) +host_op_rate 262576 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62108832 # Simulator tick rate (ticks/s) +host_mem_usage 226536 # Number of bytes of host memory used +host_seconds 2153.86 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636352 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67200 # Number of bytes written to this memory -system.physmem.bytes_written::total 67200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25568 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26529 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 459649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12229259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12688908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 459649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 459649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 502218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 502218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 502218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 459649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12229259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13191127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26529 # Total number of read requests seen -system.physmem.writeReqs 1050 # Total number of write requests seen -system.physmem.cpureqs 27579 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697856 # Total number of bytes read from memory -system.physmem.bytesWritten 67200 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697856 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67200 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26524 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 455934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12233661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12689595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 455934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 501383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 501383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 501383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 455934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12233661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13190979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26524 # Total number of read requests seen +system.physmem.writeReqs 1048 # Total number of write requests seen +system.physmem.cpureqs 27572 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697536 # Total number of bytes read from memory +system.physmem.bytesWritten 67072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1631 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1647 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1682 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis @@ -72,44 +72,31 @@ system.physmem.perBankWrReqs::9 75 # Tr system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133806263000 # Total gap between requests +system.physmem.totGap 133773818000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26529 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1050 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.readPktSize::6 26524 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1048 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 8806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -137,8 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see @@ -151,8 +137,8 @@ system.physmem.wrQLenPdf::9 46 # Wh system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see @@ -161,7 +147,7 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 648232398 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1339932398 # Sum of mem lat for all requests -system.physmem.totBusLat 132570000 # Total cycles spent in databus access -system.physmem.totBankLat 559130000 # Total cycles spent in bank access -system.physmem.avgQLat 24448.68 # Average queueing delay per request -system.physmem.avgBankLat 21088.10 # Average bank access latency per request +system.physmem.totQLat 654284750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1345973500 # Sum of mem lat for all requests +system.physmem.totBusLat 132545000 # Total cycles spent in databus access +system.physmem.totBankLat 559143750 # Total cycles spent in bank access +system.physmem.avgQLat 24681.61 # Average queueing delay per request +system.physmem.avgBankLat 21092.60 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50536.79 # Average memory access latency +system.physmem.avgMemAccLat 50774.21 # Average memory access latency system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s @@ -186,41 +171,41 @@ system.physmem.avgConsumedWrBW 0.50 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.03 # Average write queue length over time -system.physmem.readRowHits 16972 # Number of row buffer hits during reads -system.physmem.writeRowHits 273 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 26.00 # Row buffer hit rate for writes -system.physmem.avgGap 4851744.55 # Average gap between requests -system.cpu.branchPred.lookups 76500721 # Number of BP lookups -system.cpu.branchPred.condPredicted 70919742 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2718676 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43116993 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41952631 # Number of BTB hits +system.physmem.avgWrQLen 9.24 # Average write queue length over time +system.physmem.readRowHits 16966 # Number of row buffer hits during reads +system.physmem.writeRowHits 271 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes +system.physmem.avgGap 4851799.58 # Average gap between requests +system.cpu.branchPred.lookups 76502410 # Number of BP lookups +system.cpu.branchPred.condPredicted 70922676 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2717282 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43095322 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41949760 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.299529 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1606312 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.341795 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1606512 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 241 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122623794 # DTB read hits -system.cpu.dtb.read_misses 28860 # DTB read misses +system.cpu.dtb.read_hits 122629608 # DTB read hits +system.cpu.dtb.read_misses 28810 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122652654 # DTB read accesses -system.cpu.dtb.write_hits 40761180 # DTB write hits -system.cpu.dtb.write_misses 25673 # DTB write misses +system.cpu.dtb.read_accesses 122658418 # DTB read accesses +system.cpu.dtb.write_hits 40760367 # DTB write hits +system.cpu.dtb.write_misses 25602 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40786853 # DTB write accesses -system.cpu.dtb.data_hits 163384974 # DTB hits -system.cpu.dtb.data_misses 54533 # DTB misses +system.cpu.dtb.write_accesses 40785969 # DTB write accesses +system.cpu.dtb.data_hits 163389975 # DTB hits +system.cpu.dtb.data_misses 54412 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163439507 # DTB accesses -system.cpu.itb.fetch_hits 65534932 # ITB hits +system.cpu.dtb.data_accesses 163444387 # DTB accesses +system.cpu.itb.fetch_hits 65529846 # ITB hits system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65534973 # ITB accesses +system.cpu.itb.fetch_accesses 65529887 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,133 +219,133 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267612618 # number of cpu cycles simulated +system.cpu.numCycles 267547704 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67186400 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699453099 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76500721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43558943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117852914 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11666249 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73358963 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 67181660 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699454641 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76502410 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43556272 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117851527 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11664601 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73301689 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65534932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 934826 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267314333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.616594 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.444810 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65529846 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 933458 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267250540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.617224 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444995 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149461419 55.91% 55.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10349982 3.87% 59.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11850266 4.43% 64.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10577716 3.96% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7012506 2.62% 70.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2870690 1.07% 71.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3579816 1.34% 73.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3108437 1.16% 74.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68503501 25.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149399013 55.90% 55.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10348526 3.87% 59.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11849388 4.43% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10578020 3.96% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7012807 2.62% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2871984 1.07% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3578789 1.34% 73.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3106707 1.16% 74.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68505306 25.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267314333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285864 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.613678 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84322022 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57655855 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102751859 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13670665 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8913932 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3876852 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 942 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691462372 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3197 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8913932 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92304341 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12773232 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1346 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103106270 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50215212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 681285072 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 434 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38522944 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5472741 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520920645 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 897379043 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 897376453 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2590 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267250540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285939 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.614317 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84320129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57595253 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102753479 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13668133 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8913546 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3876280 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 932 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691464517 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3449 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8913546 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92299678 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12776720 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1189 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103108433 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50150974 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681302234 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 431 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38477727 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5455282 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520934901 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 897390123 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 897387366 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2757 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 57065756 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 66 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112077327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 127005785 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42387861 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14833107 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10089887 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621266103 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 59 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604722021 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299730 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 55073821 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30009810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267314333 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.262213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.825151 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 57080012 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 63 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112027328 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127008438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42384710 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14844783 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10088023 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621271293 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604725807 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299798 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 55080788 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30005964 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267250540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.262767 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823653 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52513972 19.65% 19.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55954300 20.93% 40.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53424383 19.99% 60.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36299246 13.58% 74.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31212895 11.68% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23807225 8.91% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10138155 3.79% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3408674 1.28% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 555483 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52429829 19.62% 19.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55852855 20.90% 40.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53444845 20.00% 60.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36460113 13.64% 74.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31255141 11.70% 85.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23773948 8.90% 94.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10075913 3.77% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3406027 1.27% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 551869 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267314333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267250540 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2798552 71.38% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 727516 18.56% 89.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 394572 10.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2756472 71.14% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 40 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 728591 18.80% 89.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 389871 10.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439175234 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7035 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439176954 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7066 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued @@ -388,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124352577 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41187127 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124356224 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41185515 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604722021 # Type of FU issued -system.cpu.iq.rate 2.259692 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3920679 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480975025 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 676343136 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596595322 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3759 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2270 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1723 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608640802 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1898 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12279325 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604725807 # Type of FU issued +system.cpu.iq.rate 2.260254 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3874974 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006408 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480873086 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 676355161 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596602519 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3840 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2402 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1730 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608598846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1935 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12280408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12491743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36092 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5478 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2936540 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12494396 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35705 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5495 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2933389 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6432 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 54776 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6442 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 54892 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8913932 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1438086 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 192048 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 664143136 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1694587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 127005785 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42387861 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 59 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 143884 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7497 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5478 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342912 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1811100 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3154012 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599591446 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122652830 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5130575 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8913546 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1440408 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 191911 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 664145675 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1694595 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127008438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42384710 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 55 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 143753 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7490 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5495 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342563 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1811283 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3153846 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599598114 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122658565 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5127693 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42876974 # number of nop insts executed -system.cpu.iew.exec_refs 163458157 # number of memory reference insts executed -system.cpu.iew.exec_branches 66641389 # Number of branches executed -system.cpu.iew.exec_stores 40805327 # Number of stores executed -system.cpu.iew.exec_rate 2.240520 # Inst execution rate -system.cpu.iew.wb_sent 597536756 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596597045 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415962909 # num instructions producing a value -system.cpu.iew.wb_consumers 530370743 # num instructions consuming a value +system.cpu.iew.exec_nop 42874327 # number of nop insts executed +system.cpu.iew.exec_refs 163462793 # number of memory reference insts executed +system.cpu.iew.exec_branches 66641793 # Number of branches executed +system.cpu.iew.exec_stores 40804228 # Number of stores executed +system.cpu.iew.exec_rate 2.241089 # Inst execution rate +system.cpu.iew.wb_sent 597543507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596604249 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415969736 # num instructions producing a value +system.cpu.iew.wb_consumers 530347418 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229331 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784287 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229899 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62162261 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 62164646 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2717793 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258400401 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.329164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.692856 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2716416 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258336994 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329736 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.693311 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79574518 30.80% 30.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72566023 28.08% 58.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25599330 9.91% 68.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9197400 3.56% 72.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10258446 3.97% 76.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20921268 8.10% 84.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6836400 2.65% 87.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3734572 1.45% 88.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29712444 11.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79521079 30.78% 30.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72557315 28.09% 58.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25650829 9.93% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9136101 3.54% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10241480 3.96% 76.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20967757 8.12% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6801640 2.63% 87.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3711202 1.44% 88.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29749591 11.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258400401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258336994 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +461,192 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29712444 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29749591 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892642792 # The number of ROB reads -system.cpu.rob.rob_writes 1336966756 # The number of ROB writes -system.cpu.timesIdled 34291 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 298285 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892544623 # The number of ROB reads +system.cpu.rob.rob_writes 1336970755 # The number of ROB writes +system.cpu.timesIdled 34274 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 297164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.473188 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.473188 # CPI: Total CPI of All Threads -system.cpu.ipc 2.113325 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.113325 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 845166386 # number of integer regfile reads -system.cpu.int_regfile_writes 490617161 # number of integer regfile writes -system.cpu.fp_regfile_reads 389 # number of floating regfile reads +system.cpu.cpi 0.473073 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473073 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113838 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113838 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 845171662 # number of integer regfile reads +system.cpu.int_regfile_writes 490625638 # number of integer regfile writes +system.cpu.fp_regfile_reads 396 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 825.582407 # Cycle average of tags in use -system.cpu.icache.total_refs 65533545 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 66939.269663 # Average number of references to valid blocks. +system.cpu.icache.replacements 39 # number of replacements +system.cpu.icache.tagsinuse 824.684718 # Cycle average of tags in use +system.cpu.icache.total_refs 65528462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 971 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67485.542739 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 825.582407 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403116 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403116 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65533545 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65533545 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65533545 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65533545 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65533545 # number of overall hits -system.cpu.icache.overall_hits::total 65533545 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1386 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1386 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1386 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1386 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1386 # number of overall misses -system.cpu.icache.overall_misses::total 1386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74542000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 74542000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 74542000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 74542000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 74542000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 74542000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65534931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65534931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65534931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65534931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65534931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65534931 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 824.684718 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.402678 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.402678 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65528462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65528462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65528462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65528462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65528462 # number of overall hits +system.cpu.icache.overall_hits::total 65528462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses +system.cpu.icache.overall_misses::total 1383 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 72600500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 72600500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 72600500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 72600500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 72600500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 72600500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65529845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65529845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65529845 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65529845 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65529845 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65529845 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53782.106782 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53782.106782 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53782.106782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53782.106782 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52494.938539 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52494.938539 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52494.938539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52494.938539 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.400000 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 979 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54570500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54570500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54570500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54570500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54570500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54570500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 412 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58186.138825 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58186.138825 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks +system.cpu.l2cache.writebacks::total 1049 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 953 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5258 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21266 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21266 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25571 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26524 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25571 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26524 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41181755 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 363891160 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 405072915 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1243149416 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1243149416 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41181755 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1607040576 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1648222331 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41181755 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1607040576 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1648222331 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020464 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024879 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056932 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43212.754460 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84527.563298 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77039.352415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.134205 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.134205 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460939 # number of replacements -system.cpu.dcache.tagsinuse 4090.899850 # Cycle average of tags in use -system.cpu.dcache.total_refs 146914514 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465035 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.921412 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 301771000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.899850 # Average occupied blocks per requestor +system.cpu.dcache.replacements 460826 # number of replacements +system.cpu.dcache.tagsinuse 4090.898597 # Cycle average of tags in use +system.cpu.dcache.total_refs 146919615 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464922 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 316.009169 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 301835000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.898597 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998755 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998755 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109265934 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109265934 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37648563 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37648563 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146914497 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146914497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146914497 # number of overall hits -system.cpu.dcache.overall_hits::total 146914497 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1025246 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1025246 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802758 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802758 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2828004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2828004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2828004 # number of overall misses -system.cpu.dcache.overall_misses::total 2828004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15342477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15342477500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26169777829 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26169777829 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 37000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 37000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41512255329 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41512255329 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41512255329 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41512255329 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110291180 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110291180 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 109271003 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109271003 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648598 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648598 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146919601 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146919601 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146919601 # number of overall hits +system.cpu.dcache.overall_hits::total 146919601 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1024794 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1024794 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802723 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802723 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2827517 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2827517 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2827517 # number of overall misses +system.cpu.dcache.overall_misses::total 2827517 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15336763000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15336763000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26197701326 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26197701326 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 20000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 20000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41534464326 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41534464326 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41534464326 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41534464326 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110295797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110295797 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149742501 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149742501 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149742501 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149742501 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009296 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009296 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045696 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045696 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.190476 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.190476 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018886 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018886 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018886 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018886 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14964.679209 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14964.679209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14516.522922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14516.522922 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14678.994559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14678.994559 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301355 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2673 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17784 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 149747118 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149747118 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149747118 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149747118 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009291 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009291 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045695 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045695 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.125000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018882 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018882 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018882 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018882 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14965.703351 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14965.703351 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14532.294382 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14532.294382 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14689.377403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14689.377403 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 303569 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2051 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17829 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.945288 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 243 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.026698 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 186.454545 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445006 # number of writebacks -system.cpu.dcache.writebacks::total 445006 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814778 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 814778 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548191 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1548191 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2362969 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2362969 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2362969 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2362969 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 465035 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 465035 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 465035 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 465035 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697344500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697344500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097543997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097543997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6794888497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6794888497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6794888497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6794888497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12815.936389 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12815.936389 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16096.131851 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16096.131851 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 444903 # number of writebacks +system.cpu.dcache.writebacks::total 444903 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814423 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 814423 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548172 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548172 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2362595 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2362595 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2362595 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2362595 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210371 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210371 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254551 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254551 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464922 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464922 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464922 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2696208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2696208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4103693497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4103693497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6799901497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6799901497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6799901497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6799901497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12816.443331 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12816.443331 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16121.301810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16121.301810 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index e289c0e8e..aa7b7ad18 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.164572 # Nu sim_ticks 164572262000 # Number of ticks simulated final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164809 # Simulator instruction rate (inst/s) -host_op_rate 174150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47579904 # Simulator tick rate (ticks/s) -host_mem_usage 241928 # Number of bytes of host memory used -host_seconds 3458.86 # Real time elapsed on the host +host_inst_rate 185108 # Simulator instruction rate (inst/s) +host_op_rate 195599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53440170 # Simulator tick rate (ticks/s) +host_mem_usage 241944 # Number of bytes of host memory used +host_seconds 3079.56 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 27336 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2538 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 2538 # Categorize write packet sizes system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 921366434 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1672075184 # Sum of mem lat for all requests +system.physmem.totQLat 921339250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1672034250 # Sum of mem lat for all requests system.physmem.totBusLat 136675000 # Total cycles spent in databus access -system.physmem.totBankLat 614033750 # Total cycles spent in bank access -system.physmem.avgQLat 33705.24 # Average queueing delay per request -system.physmem.avgBankLat 22462.46 # Average bank access latency per request +system.physmem.totBankLat 614020000 # Total cycles spent in bank access +system.physmem.avgQLat 33704.25 # Average queueing delay per request +system.physmem.avgBankLat 22461.95 # Average bank access latency per request system.physmem.avgBusLat 4999.82 # Average bus latency per request -system.physmem.avgMemAccLat 61167.51 # Average memory access latency +system.physmem.avgMemAccLat 61166.02 # Average memory access latency system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s @@ -323,11 +308,11 @@ system.cpu.iq.issued_per_cycle::mean 1.967168 # Nu system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85141417 25.94% 46.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76162034 23.21% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40819071 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85141419 25.94% 46.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76162032 23.21% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40819070 12.44% 82.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14914630 4.54% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14914631 4.54% 95.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle @@ -629,16 +614,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 743 # system.cpu.l2cache.overall_misses::cpu.data 26602 # number of overall misses system.cpu.l2cache.overall_misses::total 27345 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40442500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687360500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 727803000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687347500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 727790000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1581776500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1581776500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 40442500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2269137000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2309579500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2269124000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2309566500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 40442500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2269137000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2309579500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2269124000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2309566500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 831 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197598 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198429 # number of ReadReq accesses(hits+misses) @@ -666,16 +651,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.894103 system.cpu.l2cache.overall_miss_rate::cpu.data 0.059811 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.061367 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54431.359354 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142872.687591 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 131041.231545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142869.985450 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 131038.890889 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72588.522785 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72588.522785 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.488760 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84460.760651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84460.285244 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85299.488760 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84460.760651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84460.285244 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -706,17 +691,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27336 system.cpu.l2cache.overall_mshr_misses::cpu.inst 741 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26595 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27336 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149679 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627911476 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659061155 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310031171 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310031171 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149679 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937942647 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1969092326 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149679 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937942647 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1969092326 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149092 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627893373 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659042465 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310013362 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310013362 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149092 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937906735 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969055827 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149092 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937906735 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969055827 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027945 # mshr miss rate for ReadReq accesses @@ -728,17 +713,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.061347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.061347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42037.353576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130705.969192 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118856.835888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.992336 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.992336 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42036.561404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130702.200874 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118853.465284 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.175072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.175072 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 440669 # number of replacements system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use @@ -771,16 +756,16 @@ system.cpu.dcache.demand_misses::cpu.data 3718210 # n system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses system.cpu.dcache.overall_misses::total 3718210 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073572500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5073572500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073533500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5073533500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45778801266 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45778801266 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45778801266 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45778801266 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45778762266 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45778762266 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45778762266 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45778762266 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) @@ -803,16 +788,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.018473 system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.521697 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.521697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.407635 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.407635 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12312.053721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12312.053721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12312.043232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12312.043232 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked @@ -841,14 +826,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 444768 system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836417500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836417500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836404500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836404500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932840321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6932840321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932840321 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6932840321 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932827321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6932827321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932827321 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6932827321 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses @@ -857,14 +842,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.412219 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.412219 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.346429 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.346429 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index dd62eb55a..4f3b9b27a 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387316 # Number of seconds simulated -sim_ticks 387315507500 # Number of ticks simulated -final_tick 387315507500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387321 # Number of seconds simulated +sim_ticks 387320726500 # Number of ticks simulated +final_tick 387320726500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183094 # Simulator instruction rate (inst/s) -host_op_rate 183671 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50610731 # Simulator tick rate (ticks/s) -host_mem_usage 233664 # Number of bytes of host memory used -host_seconds 7652.83 # Real time elapsed on the host +host_inst_rate 176162 # Simulator instruction rate (inst/s) +host_op_rate 176717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48695201 # Simulator tick rate (ticks/s) +host_mem_usage 235496 # Number of bytes of host memory used +host_seconds 7953.98 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678528 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76544 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678784 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76480 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1196 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26227 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26231 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27426 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4333749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4333749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4949928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27424 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4334351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4334351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4950357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27427 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755072 # Total number of bytes read from memory +system.physmem.cpureqs 29960 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755264 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755264 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1768 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1660 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis @@ -77,37 +77,24 @@ system.physmem.perBankWrReqs::14 154 # Tr system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387315479500 # Total gap between requests +system.physmem.totGap 387320698500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27424 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2533 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 7981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5076 # What read queue length does an incoming req see +system.physmem.readPktSize::6 27427 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 2533 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 7983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5082 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 713274952 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1439334952 # Sum of mem lat for all requests -system.physmem.totBusLat 137120000 # Total cycles spent in databus access -system.physmem.totBankLat 588940000 # Total cycles spent in bank access -system.physmem.avgQLat 26009.15 # Average queueing delay per request -system.physmem.avgBankLat 21475.35 # Average bank access latency per request +system.physmem.totQLat 712904000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1439226500 # Sum of mem lat for all requests +system.physmem.totBusLat 137135000 # Total cycles spent in databus access +system.physmem.totBankLat 589187500 # Total cycles spent in bank access +system.physmem.avgQLat 25992.78 # Average queueing delay per request +system.physmem.avgBankLat 21482.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52484.50 # Average memory access latency +system.physmem.avgMemAccLat 52474.81 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s @@ -186,252 +171,252 @@ system.physmem.avgConsumedWrBW 0.42 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 16.51 # Average write queue length over time -system.physmem.readRowHits 17585 # Number of row buffer hits during reads +system.physmem.avgWrQLen 16.63 # Average write queue length over time +system.physmem.readRowHits 17586 # Number of row buffer hits during reads system.physmem.writeRowHits 1048 # Number of row buffer hits during writes system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes -system.physmem.avgGap 12929047.62 # Average gap between requests -system.cpu.branchPred.lookups 97759655 # Number of BP lookups -system.cpu.branchPred.condPredicted 88050231 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3614520 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65786552 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65492883 # Number of BTB hits +system.physmem.avgGap 12927927.19 # Average gap between requests +system.cpu.branchPred.lookups 97754812 # Number of BP lookups +system.cpu.branchPred.condPredicted 88045070 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3614513 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65790839 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65487235 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.553603 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1341 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.538531 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774631016 # number of cpu cycles simulated +system.cpu.numCycles 774641454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164855721 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642251558 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97759655 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65494224 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329204399 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20834739 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263342259 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2502 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 164855086 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642226882 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97754812 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65488562 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329193327 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20835132 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263364086 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2508 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161937023 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 736247 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774398184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126696 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161933823 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 733897 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774407665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126639 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146663 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445193785 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74062525 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37899229 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077552 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28106227 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18772117 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11485912 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3791430 0.49% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146009407 18.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445214338 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74055584 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37896707 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077649 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28106182 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772378 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11485240 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3791473 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146008114 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774398184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126202 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120044 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215922553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214452390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284209898 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42820116 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16993227 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636550752 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16993227 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239771948 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36701097 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52424917 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302039391 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126467604 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625687860 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927407 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73464560 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3152152 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356365192 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746429093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712307786 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34121307 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774407665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126194 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.119983 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215996576 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214396476 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284196048 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42825985 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16992580 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636523781 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16992580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239852916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36748965 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52423247 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302028125 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126361832 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625670094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30926636 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73309992 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3198488 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356344294 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746400105 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712277962 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34122143 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111594753 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2643851 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2663506 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271777312 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436941235 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179754378 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254555015 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82904621 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512542697 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2609193 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459339312 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53583 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109245499 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130204517 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 365522 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774398184 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431065 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111573855 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2642593 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663144 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271720784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436941817 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179749373 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254480906 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83188791 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512511277 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2608080 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459319933 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 52996 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109213691 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130186216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 364409 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774407665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431122 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145558409 18.80% 18.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184658706 23.85% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209828049 27.10% 69.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131187469 16.94% 86.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70686123 9.13% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20416273 2.64% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7987184 1.03% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3894628 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181343 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145648239 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184522685 23.83% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209864984 27.10% 69.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131209019 16.94% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70693972 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20392101 2.63% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8014841 1.03% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3879808 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182016 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774398184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774407665 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 118946 7.04% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95273 5.64% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1158517 68.57% 81.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 316903 18.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140362 8.20% 8.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95230 5.57% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1159729 67.79% 81.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315506 18.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866474644 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866449380 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644797 0.18% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419098125 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171121746 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644870 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419102646 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171123037 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459339312 # Type of FU issued -system.cpu.iq.rate 1.883915 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1689639 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676979008 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615425319 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443226704 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17841022 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9210458 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8545776 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451900530 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9128421 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215265115 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459319933 # Type of FU issued +system.cpu.iq.rate 1.883865 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1710827 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001172 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676966203 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615362108 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443197913 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17845151 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9210352 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8546882 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451899562 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9131198 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215327027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34428392 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58884 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245184 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12906236 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34428974 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58580 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245871 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12901231 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3305 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 101102 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3337 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 100836 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16993227 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3018866 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 247688 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608835504 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4126277 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436941235 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179754378 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2526244 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 149012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1899 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245184 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2269311 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473063 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3742374 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454021381 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416550474 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5317931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16992580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3019126 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247748 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608802731 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436941817 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179749373 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2524925 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 149083 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1915 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245871 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2268919 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473448 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3742367 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454001167 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416555573 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5318766 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93683614 # number of nop insts executed -system.cpu.iew.exec_refs 586997386 # number of memory reference insts executed -system.cpu.iew.exec_branches 89036634 # Number of branches executed -system.cpu.iew.exec_stores 170446912 # Number of stores executed -system.cpu.iew.exec_rate 1.877050 # Inst execution rate -system.cpu.iew.wb_sent 1452648479 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451772480 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153427719 # num instructions producing a value -system.cpu.iew.wb_consumers 1204682131 # num instructions consuming a value +system.cpu.iew.exec_nop 93683374 # number of nop insts executed +system.cpu.iew.exec_refs 587003910 # number of memory reference insts executed +system.cpu.iew.exec_branches 89035290 # Number of branches executed +system.cpu.iew.exec_stores 170448337 # Number of stores executed +system.cpu.iew.exec_rate 1.876999 # Inst execution rate +system.cpu.iew.wb_sent 1452626666 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451744795 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153395564 # num instructions producing a value +system.cpu.iew.wb_consumers 1204642088 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874147 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957454 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874086 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957459 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119216890 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119183948 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3614520 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757404957 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966614 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509691 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3614513 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757415085 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966588 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 239974569 31.68% 31.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275852046 36.42% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42571811 5.62% 73.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54691782 7.22% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19624283 2.59% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13282059 1.75% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30580381 4.04% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10561653 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70266373 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240000251 31.69% 31.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275796766 36.41% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42566622 5.62% 73.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54725654 7.23% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19677570 2.60% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13283245 1.75% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30556171 4.03% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10517669 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70291137 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757404957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757415085 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,70 +427,70 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70266373 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70291137 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295813886 # The number of ROB reads -system.cpu.rob.rob_writes 3234496299 # The number of ROB writes -system.cpu.timesIdled 25967 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 232832 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295766308 # The number of ROB reads +system.cpu.rob.rob_writes 3234429823 # The number of ROB writes +system.cpu.timesIdled 26016 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 233789 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552838 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552838 # CPI: Total CPI of All Threads -system.cpu.ipc 1.808847 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.808847 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979103244 # number of integer regfile reads -system.cpu.int_regfile_writes 1275174788 # number of integer regfile writes -system.cpu.fp_regfile_reads 16962430 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491706 # number of floating regfile writes -system.cpu.misc_regfile_reads 592650972 # number of misc regfile reads +system.cpu.cpi 0.552846 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552846 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808823 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808823 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979081340 # number of integer regfile reads +system.cpu.int_regfile_writes 1275150411 # number of integer regfile writes +system.cpu.fp_regfile_reads 16965180 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491866 # number of floating regfile writes +system.cpu.misc_regfile_reads 592655969 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 197 # number of replacements -system.cpu.icache.tagsinuse 1035.237714 # Cycle average of tags in use -system.cpu.icache.total_refs 161935084 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121208.895210 # Average number of references to valid blocks. +system.cpu.icache.replacements 200 # number of replacements +system.cpu.icache.tagsinuse 1035.615179 # Cycle average of tags in use +system.cpu.icache.total_refs 161931886 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121025.325859 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.237714 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505487 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505487 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161935084 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161935084 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161935084 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161935084 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161935084 # number of overall hits -system.cpu.icache.overall_hits::total 161935084 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1939 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1939 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1939 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1939 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1939 # number of overall misses -system.cpu.icache.overall_misses::total 1939 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 84566500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 84566500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 84566500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 84566500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 84566500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 84566500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161937023 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161937023 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161937023 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161937023 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161937023 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161937023 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.615179 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505671 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505671 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161931886 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161931886 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161931886 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161931886 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161931886 # number of overall hits +system.cpu.icache.overall_hits::total 161931886 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1937 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1937 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1937 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1937 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1937 # number of overall misses +system.cpu.icache.overall_misses::total 1937 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 85579500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 85579500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 85579500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 85579500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 85579500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 85579500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161933823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161933823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161933823 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161933823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161933823 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161933823 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43613.460547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43613.460547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43613.460547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43613.460547 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44181.466185 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44181.466185 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44181.466185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44181.466185 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -514,120 +499,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 602 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 602 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 602 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 602 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 602 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 602 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1337 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1337 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1337 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1337 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1337 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62189000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62189000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62434000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62434000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62434000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62434000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62434000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62434000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46513.836948 # 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number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.893204 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022133 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.027901 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083009 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083009 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.893204 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056616 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059026 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.893204 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056616 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059026 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49872.909699 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100222.109762 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 89549.007444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72890.176727 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.176727 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49872.909699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77522.778392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76317.059832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49872.909699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77522.778392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76317.059832 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,160 +623,160 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1197 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4444 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5641 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21783 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21783 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1197 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26227 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37239.759398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65155.178518 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63936.729106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37239.759398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65155.178518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63936.729106 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1196 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4446 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5642 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21785 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21785 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44803245 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1708560252 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1753363497 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44803245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1708560252 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1753363497 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022133 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027901 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083009 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083009 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059026 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059026 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37460.907191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87749.861898 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77089.530486 # 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number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367955330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367955330 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367955330 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004590 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004590 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011335 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011335 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.007648 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.007648 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.007648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.283038 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.283038 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16869.993336 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16869.993336 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.685000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.685000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16875.796073 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16875.796073 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16574.256521 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16574.256521 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 590116 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35661 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16578.269888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16578.269888 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 588860 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35662 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.547938 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.512254 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443933 # number of writebacks -system.cpu.dcache.writebacks::total 443933 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722205 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 722205 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628938 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628938 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2351143 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2351143 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2351143 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2351143 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200850 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262429 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262429 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443982 # number of writebacks +system.cpu.dcache.writebacks::total 443982 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722195 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722195 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628797 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628797 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2350992 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2350992 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2350992 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2350992 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200877 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200877 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262434 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262434 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463279 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463279 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463279 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463279 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2612152000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2612152000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357934500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357934500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 463311 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463311 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463311 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463311 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2613052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2613052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357141500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6970086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970086500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6970086500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970194000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6970194000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970194000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6970194000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -800,16 +785,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.486682 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.486682 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16606.146805 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16606.146805 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13008.221449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13008.221449 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16602.808706 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16602.808706 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index dc034cfd1..6ca2fc4f2 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.607292 # Nu sim_ticks 607292111000 # Number of ticks simulated final_tick 607292111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91190 # Simulator instruction rate (inst/s) -host_op_rate 168022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62928697 # Simulator tick rate (ticks/s) -host_mem_usage 248736 # Number of bytes of host memory used -host_seconds 9650.48 # Real time elapsed on the host +host_inst_rate 88731 # Simulator instruction rate (inst/s) +host_op_rate 163492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61232046 # Simulator tick rate (ticks/s) +host_mem_usage 248756 # Number of bytes of host memory used +host_seconds 9917.88 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 27359 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2534 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 2534 # Categorize write packet sizes system.physmem.rdQLenPdf::0 26892 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 100 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 90448613 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 895548613 # Sum of mem lat for all requests +system.physmem.totQLat 90421500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 895535250 # Sum of mem lat for all requests system.physmem.totBusLat 136795000 # Total cycles spent in databus access -system.physmem.totBankLat 668305000 # Total cycles spent in bank access -system.physmem.avgQLat 3305.99 # Average queueing delay per request -system.physmem.avgBankLat 24427.25 # Average bank access latency per request +system.physmem.totBankLat 668318750 # Total cycles spent in bank access +system.physmem.avgQLat 3305.00 # Average queueing delay per request +system.physmem.avgBankLat 24427.75 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32733.24 # Average memory access latency +system.physmem.avgMemAccLat 32732.75 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s @@ -235,22 +220,22 @@ system.cpu.fetch.rateDist::max_value 8 # Nu system.cpu.fetch.rateDist::total 1214221440 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.130483 # Number of branch fetches per cycle system.cpu.fetch.rate 1.200203 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 288175293 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497913619 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 274106217 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92482436 # Number of cycles decode is unblocking +system.cpu.decode.IdleCycles 288175297 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497913615 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274106209 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92482444 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 61543875 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2343534245 # Number of instructions handled by decode system.cpu.rename.SquashCycles 61543875 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 336850045 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 336850046 # Number of cycles rename is idle system.cpu.rename.BlockCycles 124204658 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2567 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303948664 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387671631 # Number of cycles rename is unblocking +system.cpu.rename.RunCycles 303948666 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387671628 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 2247678746 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 360 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242705543 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120202916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.IQFullEvents 242705531 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120202926 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 2618040036 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 5722358621 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 5722353197 # Number of integer rename lookups @@ -259,11 +244,11 @@ system.cpu.rename.CommittedMaps 1886895258 # Nu system.cpu.rename.UndoneMaps 731144778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 87 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731406447 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 731406444 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 531670409 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 219217246 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 342048419 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144614488 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 144614487 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 1993488562 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1783952231 # Number of instructions issued @@ -275,12 +260,12 @@ system.cpu.iq.issued_per_cycle::samples 1214221440 # Nu system.cpu.iq.issued_per_cycle::mean 1.469215 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.421905 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360233763 29.67% 29.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 364161192 29.99% 59.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234288879 19.30% 78.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141409866 11.65% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60623194 4.99% 95.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39782569 3.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360233765 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364161190 29.99% 59.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234288875 19.30% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141409873 11.65% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60623190 4.99% 95.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39782570 3.28% 98.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 11078669 0.91% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 2040416 0.17% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 602892 0.05% 100.00% # Number of insts issued each cycle @@ -368,7 +353,7 @@ system.cpu.iq.fp_inst_queue_writes 1776 # Nu system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 1740037802 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 245 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210029942 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 210029946 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 112628288 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 39424 # Number of memory responses ignored because the instruction is squashed @@ -404,8 +389,8 @@ system.cpu.iew.exec_stores 191706202 # Nu system.cpu.iew.exec_rate 1.454114 # Inst execution rate system.cpu.iew.wb_sent 1725748007 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1724635217 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267063012 # num instructions producing a value -system.cpu.iew.wb_consumers 1828799696 # num instructions consuming a value +system.cpu.iew.wb_producers 1267063011 # num instructions producing a value +system.cpu.iew.wb_consumers 1828799692 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.419939 # insts written-back per cycle system.cpu.iew.wb_fanout 0.692839 # average fanout of values written-back @@ -583,14 +568,14 @@ system.cpu.l2cache.overall_misses::total 27359 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46268500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 330234500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 376503000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1134971000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1134971000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1134984000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1134984000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 46268500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1465205500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1511474000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1465218500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1511487000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 46268500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1465205500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1511474000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1465218500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1511487000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 918 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 203811 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 204729 # number of ReadReq accesses(hits+misses) @@ -620,14 +605,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.060649 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51352.386238 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72403.968428 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68931.343830 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.260127 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.260127 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.853816 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.853816 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 55245.951972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55379.034697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 55246.427135 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 55245.951972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55379.034697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 55246.427135 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,17 +634,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27359 system.cpu.l2cache.overall_mshr_misses::cpu.inst 901 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26458 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27359 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35083215 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273211469 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 308294684 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862598556 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862598556 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35083215 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1135810025 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1170893240 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35083215 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1135810025 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1170893240 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35082483 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273207016 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 308289499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862590617 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862590617 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35082483 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1135797633 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1170880116 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35082483 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1135797633 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1170880116 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022379 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026679 # mshr miss rate for ReadReq accesses @@ -671,35 +656,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.060649 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058772 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.060649 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38938.085461 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59901.659504 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56443.552545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39393.458282 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39393.458282 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38938.085461 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42797.369787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38938.085461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42797.369787 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38937.273030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59900.683184 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56442.603259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39393.095721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39393.095721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38937.273030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42928.325384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38937.273030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.325384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 446086 # number of replacements system.cpu.dcache.tagsinuse 4092.713768 # Cycle average of tags in use -system.cpu.dcache.total_refs 452307982 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 452307978 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 450182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1004.722494 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1004.722486 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4092.713768 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264368372 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264368372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 264368368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264368368 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187939603 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 187939603 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452307975 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452307975 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452307975 # number of overall hits -system.cpu.dcache.overall_hits::total 452307975 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 452307971 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452307971 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452307971 # number of overall hits +system.cpu.dcache.overall_hits::total 452307971 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 211281 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 211281 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 246455 # number of WriteReq misses @@ -710,20 +695,20 @@ system.cpu.dcache.overall_misses::cpu.data 457736 # system.cpu.dcache.overall_misses::total 457736 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022618500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 3022618500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119755500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4119755500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7142374000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7142374000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7142374000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7142374000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264579653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264579653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119768500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4119768500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7142387000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7142387000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7142387000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7142387000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264579649 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264579649 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452765711 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452765711 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452765711 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452765711 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 452765707 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452765707 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452765707 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452765707 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000799 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000799 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses @@ -734,12 +719,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.153890 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.153890 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.055669 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.055669 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15603.697328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15603.697328 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.108417 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.108417 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15603.725728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15603.725728 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked @@ -768,12 +753,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 450191 system.cpu.dcache.overall_mshr_misses::total 450191 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528414500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528414500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626209000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626209000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154623500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6154623500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154623500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6154623500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626222000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626222000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6154636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154636500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6154636500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -784,12 +769,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.317025 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.317025 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.310374 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.310374 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.363139 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.363139 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |