diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
| commit | 26ca8b87470912d5e593a21fc968dd2ddf0e20b2 (patch) | |
| tree | bf97df45e65f08107321f58d83688b08bbd3f675 /tests/long/se/00.gzip | |
| parent | 6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6 (diff) | |
| download | gem5-26ca8b87470912d5e593a21fc968dd2ddf0e20b2.tar.xz | |
Regressions: Update stats due to O3 CPU changes
Diffstat (limited to 'tests/long/se/00.gzip')
6 files changed, 811 insertions, 744 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 9f24d0367..2c3feadf1 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.fuPool] type=FUPool @@ -445,9 +465,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -478,7 +510,7 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -489,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -497,12 +529,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index d3786fda6..316fa1ee5 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:31:06 -gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing +gem5 compiled Feb 10 2012 00:18:03 +gem5 started Feb 10 2012 00:18:23 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 177098873000 because target called exit() +Exiting @ tick 177116942500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 5022d17a1..e05b6f985 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,24 +1,24 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.177099 # Number of seconds simulated -sim_ticks 177098873000 # Number of ticks simulated -final_tick 177098873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.177117 # Number of seconds simulated +sim_ticks 177116942500 # Number of ticks simulated +final_tick 177116942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154897 # Simulator instruction rate (inst/s) -host_tick_rate 45541130 # Simulator tick rate (ticks/s) -host_mem_usage 220436 # Number of bytes of host memory used -host_seconds 3888.77 # Real time elapsed on the host -sim_insts 602359805 # Number of instructions simulated -system.physmem.bytes_read 5833856 # Number of bytes read from this memory +host_inst_rate 89657 # Simulator instruction rate (inst/s) +host_tick_rate 26362655 # Simulator tick rate (ticks/s) +host_mem_usage 256136 # Number of bytes of host memory used +host_seconds 6718.48 # Real time elapsed on the host +sim_insts 602359810 # Number of instructions simulated +system.physmem.bytes_read 5833792 # Number of bytes read from this memory system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3720192 # Number of bytes written to this memory -system.physmem.num_reads 91154 # Number of read requests responded to by this memory -system.physmem.num_writes 58128 # Number of write requests responded to by this memory +system.physmem.bytes_written 3720320 # Number of bytes written to this memory +system.physmem.num_reads 91153 # Number of read requests responded to by this memory +system.physmem.num_writes 58130 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 32941237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 265253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 21006300 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 53947537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 32937515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 265226 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 21004879 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 53942395 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -62,141 +62,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 354197747 # number of cpu cycles simulated +system.cpu.numCycles 354233886 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91137531 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 84224367 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4001637 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 86284566 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 80014553 # Number of BTB hits +system.cpu.BPredUnit.lookups 91144697 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 84232652 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4003225 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 86347481 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 80064419 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1704311 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1605 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 76786839 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 703787736 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91137531 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81718864 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 159146597 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 18455506 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 103039518 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 620 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 74412736 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1337820 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 353350911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.128080 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.980798 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1704141 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1603 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 76798037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 703840817 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91144697 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81768560 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 159197395 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 18458844 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 103018501 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 74422546 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1338162 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 353393528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.127927 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.980484 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 194204457 54.96% 54.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25620928 7.25% 62.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 19248235 5.45% 67.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24404617 6.91% 74.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11778472 3.33% 77.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13409998 3.80% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4602257 1.30% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7805373 2.21% 85.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52276574 14.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 194196282 54.95% 54.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25625707 7.25% 62.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 19294200 5.46% 67.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24432014 6.91% 74.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11774546 3.33% 77.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13391437 3.79% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4604134 1.30% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7796226 2.21% 85.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52278982 14.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 353350911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257307 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.986991 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 98877750 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83515155 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 137076269 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19506954 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14374783 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6301291 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2551 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 740114896 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7230 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14374783 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 111843103 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9537973 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 119731 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 143514381 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73960940 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 727174418 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 286 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59845789 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10289393 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 334 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 752889395 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3380302991 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3380302863 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 353393528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257301 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.986938 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 98941962 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83442113 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 137180071 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19452898 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14376484 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6300700 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 2518 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 740147617 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 7037 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14376484 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 111904204 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9631562 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 118839 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 143566748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73795691 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 727217623 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 278 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59684680 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10267337 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 752950298 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3380504235 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3380504107 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 125472001 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 13297 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 13294 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 132095966 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 179744866 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 82855502 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 19180586 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24795671 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 702443112 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9504 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 663038146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 743101 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 99536301 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 237037166 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3158 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 353350911 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.876430 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.733239 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 125532896 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 13135 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 13128 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 131736703 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 179759563 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 82851365 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 19142240 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24648771 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 702464419 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 9443 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 663065354 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 737309 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 99563138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 237077273 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3096 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 353393528 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.876280 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.733355 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 85428360 24.18% 24.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90441308 25.60% 49.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76153703 21.55% 71.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 42544702 12.04% 83.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 25577763 7.24% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 18033700 5.10% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7283699 2.06% 97.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6627828 1.88% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1259848 0.36% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 85420653 24.17% 24.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 90592891 25.64% 49.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76061550 21.52% 71.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 42517322 12.03% 83.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 25489615 7.21% 90.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 18140901 5.13% 95.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7279964 2.06% 97.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6670408 1.89% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1220224 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 353350911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 353393528 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 202982 4.88% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2990868 71.85% 76.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 968637 23.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202199 4.87% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2984693 71.84% 76.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 967527 23.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412586864 62.23% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6565 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412589272 62.22% 62.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued @@ -224,137 +224,137 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 172485012 26.01% 88.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 77959702 11.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 172499638 26.02% 88.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 77969869 11.76% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 663038146 # Type of FU issued -system.cpu.iq.rate 1.871943 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4162487 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006278 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1684332755 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 802000478 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 650204091 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 663065354 # Type of FU issued +system.cpu.iq.rate 1.871829 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4154419 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006265 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1684415928 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 802048612 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 650214601 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 667200613 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 667219753 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 29662170 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 29667951 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30792271 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 224606 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11800 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12634488 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30806967 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 225012 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11842 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12630350 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 13695 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12640 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 13680 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12577 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14374783 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 826341 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 58736 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 702522112 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1853549 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 179744866 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 82855502 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 8175 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13020 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5275 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11800 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4156328 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 497844 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4654172 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 656067860 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169121282 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6970286 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 14376484 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 831826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 58719 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 702543187 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1852399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 179759563 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 82851365 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 8113 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13094 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5271 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11842 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4161334 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 494337 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4655671 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 656082264 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169130146 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6983090 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69496 # number of nop insts executed -system.cpu.iew.exec_refs 245806937 # number of memory reference insts executed -system.cpu.iew.exec_branches 76463124 # Number of branches executed -system.cpu.iew.exec_stores 76685655 # Number of stores executed -system.cpu.iew.exec_rate 1.852264 # Inst execution rate -system.cpu.iew.wb_sent 652210228 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 650204107 # cumulative count of insts written-back -system.cpu.iew.wb_producers 423315850 # num instructions producing a value -system.cpu.iew.wb_consumers 657380921 # num instructions consuming a value +system.cpu.iew.exec_nop 69325 # number of nop insts executed +system.cpu.iew.exec_refs 245820033 # number of memory reference insts executed +system.cpu.iew.exec_branches 76462484 # Number of branches executed +system.cpu.iew.exec_stores 76689887 # Number of stores executed +system.cpu.iew.exec_rate 1.852116 # Inst execution rate +system.cpu.iew.wb_sent 652222843 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 650214617 # cumulative count of insts written-back +system.cpu.iew.wb_producers 423345319 # num instructions producing a value +system.cpu.iew.wb_consumers 657402766 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.835709 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.643943 # average fanout of values written-back +system.cpu.iew.wb_rate 1.835552 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.643966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 100172226 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6346 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4060978 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 338976129 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.776998 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.152747 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 100193357 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6347 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4062580 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 339017045 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.776783 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.152670 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 108154848 31.91% 31.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 106518775 31.42% 63.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49308103 14.55% 77.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9862304 2.91% 80.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23329668 6.88% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14306268 4.22% 91.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7919036 2.34% 94.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1343281 0.40% 94.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18233846 5.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 108187576 31.91% 31.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 106522126 31.42% 63.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49316522 14.55% 77.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9859363 2.91% 80.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23336266 6.88% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14305882 4.22% 91.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7916477 2.34% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1329398 0.39% 94.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18243435 5.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 338976129 # Number of insts commited each cycle -system.cpu.commit.count 602359856 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 339017045 # Number of insts commited each cycle +system.cpu.commit.count 602359861 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173609 # Number of memory references committed -system.cpu.commit.loads 148952595 # Number of loads committed +system.cpu.commit.refs 219173611 # Number of memory references committed +system.cpu.commit.loads 148952596 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828602 # Number of branches committed +system.cpu.commit.branches 70828603 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522643 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522647 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 18233846 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 18243435 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1023273753 # The number of ROB reads -system.cpu.rob.rob_writes 1419480895 # The number of ROB writes -system.cpu.timesIdled 37084 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 846836 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359805 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated -system.cpu.cpi 0.588017 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.588017 # CPI: Total CPI of All Threads -system.cpu.ipc 1.700631 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.700631 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3275893571 # number of integer regfile reads -system.cpu.int_regfile_writes 675997918 # number of integer regfile writes +system.cpu.rob.rob_reads 1023326216 # The number of ROB reads +system.cpu.rob.rob_writes 1419524916 # The number of ROB writes +system.cpu.timesIdled 37353 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 840358 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359810 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated +system.cpu.cpi 0.588077 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.588077 # CPI: Total CPI of All Threads +system.cpu.ipc 1.700458 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.700458 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3275977261 # number of integer regfile reads +system.cpu.int_regfile_writes 676006750 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 943643021 # number of misc regfile reads -system.cpu.misc_regfile_writes 2658 # number of misc regfile writes +system.cpu.misc_regfile_reads 943708295 # number of misc regfile reads +system.cpu.misc_regfile_writes 2660 # number of misc regfile writes system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 657.503073 # Cycle average of tags in use -system.cpu.icache.total_refs 74411745 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 766 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 97143.270235 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 657.275674 # Cycle average of tags in use +system.cpu.icache.total_refs 74421550 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 765 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 97283.071895 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 657.503073 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.321046 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 74411745 # number of ReadReq hits -system.cpu.icache.demand_hits 74411745 # number of demand (read+write) hits -system.cpu.icache.overall_hits 74411745 # number of overall hits -system.cpu.icache.ReadReq_misses 991 # number of ReadReq misses -system.cpu.icache.demand_misses 991 # number of demand (read+write) misses -system.cpu.icache.overall_misses 991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34848500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34848500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34848500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 74412736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 74412736 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 74412736 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 657.275674 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.320935 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 74421550 # number of ReadReq hits +system.cpu.icache.demand_hits 74421550 # number of demand (read+write) hits +system.cpu.icache.overall_hits 74421550 # number of overall hits +system.cpu.icache.ReadReq_misses 996 # number of ReadReq misses +system.cpu.icache.demand_misses 996 # number of demand (read+write) misses +system.cpu.icache.overall_misses 996 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 34937500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 34937500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 34937500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 74422546 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 74422546 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 74422546 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35164.984864 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35164.984864 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35164.984864 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35077.811245 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35077.811245 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35077.811245 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,67 +364,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 766 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 766 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 766 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 231 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 231 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 231 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 765 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 765 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 765 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 26233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 26233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 26233500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 26235000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26235000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26235000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34247.389034 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34294.117647 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 441233 # number of replacements -system.cpu.dcache.tagsinuse 4094.750739 # Cycle average of tags in use -system.cpu.dcache.total_refs 205781738 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445329 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 462.089237 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 87973000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.750739 # Average occupied blocks per context +system.cpu.dcache.replacements 441200 # number of replacements +system.cpu.dcache.tagsinuse 4094.750887 # Cycle average of tags in use +system.cpu.dcache.total_refs 205785268 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 445296 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 462.131409 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87972000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.750887 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 137926945 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 67852137 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1328 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 205779082 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 205779082 # number of overall hits -system.cpu.dcache.ReadReq_misses 249074 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1565394 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 11 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1814468 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1814468 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3282849000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 27038418025 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 203000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 30321267025 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30321267025 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 138176019 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 137930344 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67852261 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 205782605 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 205782605 # number of overall hits +system.cpu.dcache.ReadReq_misses 248964 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1565270 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1814234 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1814234 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3282822000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 27026336525 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 201000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 30309158525 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 30309158525 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 138179308 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1339 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 207593550 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 207593550 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001803 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.022550 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.008215 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.008740 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008740 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13180.215518 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17272.595925 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 18454.545455 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 16710.830406 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 16710.830406 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 207596839 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 207596839 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001802 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.022549 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.006701 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008739 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008739 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13185.930496 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17266.245775 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 22333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 16706.311603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 16706.311603 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked @@ -433,70 +433,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 395275 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51126 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1318013 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 11 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1369139 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1369139 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197948 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247381 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 445329 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 445329 # number of overall MSHR misses +system.cpu.dcache.writebacks 395250 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51046 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1317892 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1368938 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1368938 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197918 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247378 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 445296 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 445296 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1625134500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2544872027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4170006527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4170006527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1625205500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2544318027 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4169523527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4169523527 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001433 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8209.906137 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10287.257417 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8211.509312 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.142684 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72960 # number of replacements -system.cpu.l2cache.tagsinuse 17805.724339 # Cycle average of tags in use -system.cpu.l2cache.total_refs 422235 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88493 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.771394 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72965 # number of replacements +system.cpu.l2cache.tagsinuse 17807.300199 # Cycle average of tags in use +system.cpu.l2cache.total_refs 421253 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.760351 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1879.670498 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15926.053841 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057363 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486025 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165899 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 395275 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 189031 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 354930 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 354930 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32812 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58353 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91165 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91165 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1126662000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2003366500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3130028500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3130028500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198711 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 395275 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247384 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 446095 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 446095 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165124 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235880 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204362 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204362 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34336.888943 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34331.850976 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34333.664235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34333.664235 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1881.136315 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15926.163884 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057408 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486028 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165871 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 395250 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 189027 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 354898 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 354898 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32808 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58355 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91163 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91163 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1126263500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2003081500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3129345000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3129345000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198679 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 395250 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247382 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 446061 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 446061 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165131 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235890 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204373 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204373 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34328.928920 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.790421 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34326.919913 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34326.919913 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -505,28 +505,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58128 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32801 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58353 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91154 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91154 # number of overall MSHR misses +system.cpu.l2cache.writebacks 58130 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32798 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58355 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91153 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1019608000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822407000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2842015000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2842015000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1019340000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822214500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2841554500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2841554500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165069 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235880 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204338 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204338 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31084.662053 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31230.733638 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165080 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235890 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204351 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.334106 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31226.364493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 6e971ebcf..3b035cefe 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -89,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -149,7 +159,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.fuPool] type=FUPool @@ -446,9 +463,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -479,7 +512,7 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -490,7 +523,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -498,7 +531,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr @@ -522,7 +555,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index bff73f5f1..774f2864e 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ -Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout -Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr +Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 28 2012 12:11:40 -gem5 started Jan 28 2012 12:12:43 +gem5 compiled Feb 9 2012 12:45:55 +gem5 started Feb 9 2012 12:46:40 gem5 executing on ribera.cs.wisc.edu -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -42,4 +42,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 588785308000 because target called exit() +Exiting @ tick 586834596000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index f7c59f027..1e4919244 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.588785 # Number of seconds simulated -sim_ticks 588785308000 # Number of ticks simulated -final_tick 588785308000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.586835 # Number of seconds simulated +sim_ticks 586834596000 # Number of ticks simulated +final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112730 # Simulator instruction rate (inst/s) -host_tick_rate 40933847 # Simulator tick rate (ticks/s) -host_mem_usage 244824 # Number of bytes of host memory used -host_seconds 14383.83 # Real time elapsed on the host +host_inst_rate 99458 # Simulator instruction rate (inst/s) +host_tick_rate 35994653 # Simulator tick rate (ticks/s) +host_mem_usage 253740 # Number of bytes of host memory used +host_seconds 16303.38 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated -system.physmem.bytes_read 5878272 # Number of bytes read from this memory -system.physmem.bytes_inst_read 57216 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3742528 # Number of bytes written to this memory -system.physmem.num_reads 91848 # Number of read requests responded to by this memory -system.physmem.num_writes 58477 # Number of write requests responded to by this memory +system.physmem.bytes_read 5879616 # Number of bytes read from this memory +system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3743488 # Number of bytes written to this memory +system.physmem.num_reads 91869 # Number of read requests responded to by this memory +system.physmem.num_writes 58492 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9983727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 97176 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 6356354 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 16340082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 10019205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 97172 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 6379119 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 16398324 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1177570617 # number of cpu cycles simulated +system.cpu.numCycles 1173669193 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 141882222 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 141882222 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7459322 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 135523268 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 134664780 # Number of BTB hits +system.cpu.BPredUnit.lookups 140536614 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 140536614 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7896314 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 133769291 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 132901689 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 141519405 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1135188232 # Number of instructions fetch has processed -system.cpu.fetch.Branches 141882222 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 134664780 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 328423216 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 56273795 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 658902879 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 135738609 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 998788 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1177479353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.766783 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.096310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 138231227 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1143529036 # Number of instructions fetch has processed +system.cpu.fetch.Branches 140536614 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 132901689 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330118681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 56348337 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 656952944 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 136534174 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2392311 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1173574785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.778199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.100517 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 852058955 72.36% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 15948065 1.35% 73.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 17931063 1.52% 75.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17495755 1.49% 76.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23352779 1.98% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16626553 1.41% 80.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 22402886 1.90% 82.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28214099 2.40% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183449198 15.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 846464435 72.13% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 17271965 1.47% 73.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15892053 1.35% 74.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 19142892 1.63% 76.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23218397 1.98% 78.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16689415 1.42% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 22145456 1.89% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30830267 2.63% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 181919905 15.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1177479353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.120487 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.964009 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 241266448 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 565597424 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225300633 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 96681345 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 48633503 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2058834896 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 48633503 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 289994325 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 136667782 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3607 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 255841310 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 446338826 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2031094400 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 199 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 278357951 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 133112570 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2019296537 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4928551600 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4928548640 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2960 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1173574785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119741 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.974320 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 240018155 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 564065687 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 224667967 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 96551481 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 48271495 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2053347825 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 48271495 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 288250921 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 136396250 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3594 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 255481832 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 445170693 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2022383034 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 772 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 278054588 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 132157059 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2011799289 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4917261318 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4917257566 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 401301887 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 93 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 797995614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 517349896 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 226176362 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 355062669 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 148977960 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1979799927 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 215 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1779311117 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 175082 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 358154503 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 654941515 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 165 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1177479353 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.511119 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.319645 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 393804639 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 92 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 795963127 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 515675644 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 225280197 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 353360778 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 147850226 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1972232230 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 190 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1776284004 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 173989 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 350598274 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 640215855 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1173574785 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.513567 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.313751 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 271443176 23.05% 23.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 420511572 35.71% 58.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 239784716 20.36% 79.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 159545639 13.55% 92.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 48751983 4.14% 96.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 21481111 1.82% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 13897994 1.18% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1713551 0.15% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 349611 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 268099715 22.84% 22.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 420406461 35.82% 58.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 239398162 20.40% 79.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 159391711 13.58% 92.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 48358537 4.12% 96.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24330955 2.07% 98.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11625243 0.99% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1646303 0.14% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 317698 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1177479353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1173574785 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 183781 6.86% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2344413 87.49% 94.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 151333 5.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 185497 7.34% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2190114 86.61% 93.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153108 6.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 26390474 1.48% 1.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1101178190 61.89% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 457060255 25.69% 89.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194682198 10.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 26819156 1.51% 1.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1098315644 61.83% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 456429787 25.70% 89.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194719417 10.96% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1779311117 # Type of FU issued -system.cpu.iq.rate 1.511002 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2679527 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001506 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4738956161 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2338163322 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1758678242 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 1776284004 # Type of FU issued +system.cpu.iq.rate 1.513445 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2528719 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4728845466 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2323038766 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1755173186 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 458 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1755600151 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1751993548 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 207757708 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 207962564 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 98307771 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 75876 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 215687 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 37990305 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 96633519 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 76725 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 215178 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 37094140 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1126 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 1306 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 48633503 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1923683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 157688 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1979800142 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 665872 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 517349896 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 226176362 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 48271495 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1965747 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 154206 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1972232420 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7113535 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 515675644 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 225280197 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 85 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 70768 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 44 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 215687 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4604749 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3040457 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7645206 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766024784 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 451208749 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 13286333 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 69568 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 118 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 215178 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4620478 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3457907 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8078385 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1762068190 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 450602678 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 14215814 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 645051015 # number of memory reference insts executed -system.cpu.iew.exec_branches 112022135 # Number of branches executed -system.cpu.iew.exec_stores 193842266 # Number of stores executed -system.cpu.iew.exec_rate 1.499719 # Inst execution rate -system.cpu.iew.wb_sent 1764443624 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1758678254 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1332033031 # num instructions producing a value -system.cpu.iew.wb_consumers 1982428848 # num instructions consuming a value +system.cpu.iew.exec_refs 644481818 # number of memory reference insts executed +system.cpu.iew.exec_branches 111935144 # Number of branches executed +system.cpu.iew.exec_stores 193879140 # Number of stores executed +system.cpu.iew.exec_rate 1.501333 # Inst execution rate +system.cpu.iew.wb_sent 1756702193 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1755173198 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1327558450 # num instructions producing a value +system.cpu.iew.wb_consumers 1975144997 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.493480 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.671920 # average fanout of values written-back +system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 358308768 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7459361 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1128845850 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.436418 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.651874 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1125303290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.440940 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.651939 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 347283519 30.76% 30.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 441725058 39.13% 69.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 99623372 8.83% 78.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 136537223 12.10% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 31770740 2.81% 93.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26056867 2.31% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22501724 1.99% 97.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8245904 0.73% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15101443 1.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 343524257 30.53% 30.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 441933791 39.27% 69.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 99674686 8.86% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 136523006 12.13% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 31731928 2.82% 93.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26136643 2.32% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22505633 2.00% 97.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8189692 0.73% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15083654 1.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1128845850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1125303290 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -266,48 +266,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15101443 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15083654 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3093547157 # The number of ROB reads -system.cpu.rob.rob_writes 4008258633 # The number of ROB writes -system.cpu.timesIdled 21053 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 91264 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3082456564 # The number of ROB reads +system.cpu.rob.rob_writes 3992764754 # The number of ROB writes +system.cpu.timesIdled 21723 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 94408 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.726226 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.726226 # CPI: Total CPI of All Threads -system.cpu.ipc 1.376982 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.376982 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3270153545 # number of integer regfile reads -system.cpu.int_regfile_writes 1754693299 # number of integer regfile writes +system.cpu.cpi 0.723820 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.723820 # CPI: Total CPI of All Threads +system.cpu.ipc 1.381560 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.381560 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3268959976 # number of integer regfile reads +system.cpu.int_regfile_writes 1746565098 # number of integer regfile writes system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 907833056 # number of misc regfile reads +system.cpu.misc_regfile_reads 905288155 # number of misc regfile reads system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 808.459907 # Cycle average of tags in use -system.cpu.icache.total_refs 135737385 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 897 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 151323.729097 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 807.278486 # Cycle average of tags in use +system.cpu.icache.total_refs 136532946 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 152721.416107 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 808.459907 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.394756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 135737385 # number of ReadReq hits -system.cpu.icache.demand_hits 135737385 # number of demand (read+write) hits -system.cpu.icache.overall_hits 135737385 # number of overall hits -system.cpu.icache.ReadReq_misses 1224 # number of ReadReq misses -system.cpu.icache.demand_misses 1224 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1224 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 43199000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 43199000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 43199000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 135738609 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 135738609 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 135738609 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 807.278486 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.394179 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 136532946 # number of ReadReq hits +system.cpu.icache.demand_hits 136532946 # number of demand (read+write) hits +system.cpu.icache.overall_hits 136532946 # number of overall hits +system.cpu.icache.ReadReq_misses 1228 # number of ReadReq misses +system.cpu.icache.demand_misses 1228 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1228 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 43195500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 43195500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 43195500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 136534174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 136534174 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 136534174 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35293.300654 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35293.300654 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35293.300654 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35175.488599 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35175.488599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35175.488599 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -317,59 +317,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 327 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 327 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 327 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 897 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 334 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 334 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 334 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 894 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 894 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 894 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 31683500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 31683500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 31683500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 31569000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 31569000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 31569000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35321.627648 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35321.627648 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35321.627648 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.080537 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459032 # number of replacements -system.cpu.dcache.tagsinuse 4094.268658 # Cycle average of tags in use -system.cpu.dcache.total_refs 431168175 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463128 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 930.991378 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 416529000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.268658 # Average occupied blocks per context +system.cpu.dcache.replacements 459037 # number of replacements +system.cpu.dcache.tagsinuse 4094.269422 # Cycle average of tags in use +system.cpu.dcache.total_refs 430357004 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463133 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 929.229841 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 414463000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.269422 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999577 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 243231636 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 187936539 # number of WriteReq hits -system.cpu.dcache.demand_hits 431168175 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 431168175 # number of overall hits -system.cpu.dcache.ReadReq_misses 217117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 249518 # number of WriteReq misses -system.cpu.dcache.demand_misses 466635 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 466635 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2193700500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 3216393000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 5410093500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 5410093500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 243448753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 242420503 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 187936501 # number of WriteReq hits +system.cpu.dcache.demand_hits 430357004 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 430357004 # number of overall hits +system.cpu.dcache.ReadReq_misses 217102 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 249556 # number of WriteReq misses +system.cpu.dcache.demand_misses 466658 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 466658 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2192767500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3219007000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 5411774500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 5411774500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 242637605 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 431634810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 431634810 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000892 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 430823662 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 430823662 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000895 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.001326 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.001081 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.001081 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10103.771239 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 12890.424739 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 11593.844225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 11593.844225 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.001083 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.001083 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10100.171809 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12898.936511 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 11596.875013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 11596.875013 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,69 +378,69 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 409997 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3467 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 38 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3505 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3505 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213650 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249480 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 463130 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 463130 # number of overall MSHR misses +system.cpu.dcache.writebacks 409999 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3488 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 35 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 3523 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3523 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213614 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249521 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1524751500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2467190000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3991941500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3991941500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1523998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2469759000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3993757500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3993757500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000878 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000880 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001073 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001073 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7136.679148 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9889.329806 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8619.483730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8619.483730 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001075 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001075 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7134.356831 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9898.000569 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73588 # number of replacements -system.cpu.l2cache.tagsinuse 17962.176251 # Cycle average of tags in use -system.cpu.l2cache.total_refs 452941 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89203 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.077643 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73601 # number of replacements +system.cpu.l2cache.tagsinuse 17971.586292 # Cycle average of tags in use +system.cpu.l2cache.total_refs 452847 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89223 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.075451 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1977.761332 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15984.414919 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.060356 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487806 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181391 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 409997 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 190788 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 372179 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 372179 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33152 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58696 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91848 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91848 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1130561500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2008268500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3138830000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3138830000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214543 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 409997 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249484 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464027 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464027 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154524 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235270 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197937 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197937 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34102.361848 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34214.742061 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34174.179078 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34174.179078 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1981.498209 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15990.088083 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.060471 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487979 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181345 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 409999 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 190815 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 372160 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 372160 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33162 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58707 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91869 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91869 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1129684500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2008512000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3138196500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3138196500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214507 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 409999 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249522 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464029 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464029 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154596 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235278 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.197981 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.197981 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34065.632350 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34212.478921 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34159.471639 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34159.471639 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,27 +449,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58477 # number of writebacks +system.cpu.l2cache.writebacks 58492 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33152 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58696 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91848 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91848 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33162 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58707 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91869 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91869 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1027873500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819617000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2847490500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2847490500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1028173500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819949000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2848122500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2848122500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154524 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235270 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197937 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197937 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871501 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.698514 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.204730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.204730 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235278 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.197981 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.197981 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.568482 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.545080 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |