diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/long/se/00.gzip | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/long/se/00.gzip')
| -rw-r--r-- | tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt | 658 | ||||
| -rw-r--r-- | tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 1162 | ||||
| -rw-r--r-- | tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt | 1172 | ||||
| -rw-r--r-- | tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 1202 | ||||
| -rw-r--r-- | tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt | 1160 |
5 files changed, 3072 insertions, 2282 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 182ad7ea2..eaa40425f 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.271545 # Number of seconds simulated -sim_ticks 271544682500 # Number of ticks simulated -final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.271565 # Number of seconds simulated +sim_ticks 271565222500 # Number of ticks simulated +final_tick 271565222500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142205 # Simulator instruction rate (inst/s) -host_op_rate 142205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64159611 # Simulator tick rate (ticks/s) -host_mem_usage 212920 # Number of bytes of host memory used -host_seconds 4232.33 # Real time elapsed on the host +host_inst_rate 118122 # Simulator instruction rate (inst/s) +host_op_rate 118122 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53298093 # Simulator tick rate (ticks/s) +host_mem_usage 217868 # Number of bytes of host memory used +host_seconds 5095.21 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,175 @@ system.physmem.num_reads::cpu.data 25316 # Nu system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 198214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5966694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6164908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 209999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 209999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 209999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 198214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5966694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6374907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5966243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6164442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 209983 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 209983 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 209983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5966243 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6374424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26157 # Total number of read requests seen +system.physmem.writeReqs 891 # Total number of write requests seen +system.physmem.cpureqs 27048 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1674048 # Total number of bytes read from memory +system.physmem.bytesWritten 57024 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1674048 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 57024 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1560 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1574 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1662 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1553 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1614 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1596 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1666 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 65 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 65 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 71 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 48 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 41 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 49 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 271565170500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 26157 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 891 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 22499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 129156577 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 809724577 # Sum of mem lat for all requests +system.physmem.totBusLat 104608000 # Total cycles spent in databus access +system.physmem.totBankLat 575960000 # Total cycles spent in bank access +system.physmem.avgQLat 4938.69 # Average queueing delay per request +system.physmem.avgBankLat 22023.55 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30962.24 # Average memory access latency +system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.21 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.21 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 7.68 # Average write queue length over time +system.physmem.readRowHits 17269 # Number of row buffer hits during reads +system.physmem.writeRowHits 120 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 13.47 # Row buffer hit rate for writes +system.physmem.avgGap 10040120.18 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -42,18 +200,18 @@ system.cpu.dtb.read_hits 114517787 # DT system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 114520418 # DTB read accesses -system.cpu.dtb.write_hits 39661840 # DTB write hits +system.cpu.dtb.write_hits 39661841 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664142 # DTB write accesses -system.cpu.dtb.data_hits 154179627 # DTB hits +system.cpu.dtb.write_accesses 39664143 # DTB write accesses +system.cpu.dtb.data_hits 154179628 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154184560 # DTB accesses -system.cpu.itb.fetch_hits 25070818 # ITB hits +system.cpu.dtb.data_accesses 154184561 # DTB accesses +system.cpu.itb.fetch_hits 25070821 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25070840 # ITB accesses +system.cpu.itb.fetch_accesses 25070843 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 543089366 # number of cpu cycles simulated +system.cpu.numCycles 543130446 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86310005 # Number of BP lookups +system.cpu.branch_predictor.lookups 86310002 # Number of BP lookups system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36354317 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52694904 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34317639 # Number of BTB hits +system.cpu.branch_predictor.condIncorrect 36354316 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52694902 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34317638 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 65.125157 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36895090 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49414915 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541552617 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 65.125158 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36895088 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49414914 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541552418 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005407463 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1005407264 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255071199 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 255071398 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 155051796 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2591546 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36349330 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26198577 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.114383 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.predictedNotTakenIncorrect 2591545 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36349329 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26198578 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.114381 # Percentage of Incorrect Branches Predicts system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538349706 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538350006 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 387700 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53984537 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489104829 # Number of cycles cpu stages are processed. -system.cpu.activity 90.059732 # Percentage of cycles cpu is active +system.cpu.timesIdled 387710 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54025519 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489104927 # Number of cycles cpu stages are processed. +system.cpu.activity 90.052939 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -114,144 +272,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.902356 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.902424 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.902356 # CPI: Total CPI of All Threads -system.cpu.ipc 1.108210 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.902424 # CPI: Total CPI of All Threads +system.cpu.ipc 1.108126 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.108210 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 204234221 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338855145 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.393994 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 232262845 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310826521 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.233034 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 201309957 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341779409 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.932444 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 431519146 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111570220 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.543621 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 196111910 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346977456 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.889569 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.108126 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 204275308 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338855138 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.389273 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 232303926 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310826520 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.228705 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 201351117 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341779329 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.927669 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 431560271 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111570175 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.542059 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 196153041 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346977405 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.884727 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.073717 # Cycle average of tags in use -system.cpu.icache.total_refs 25069794 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.013382 # Cycle average of tags in use +system.cpu.icache.total_refs 25069798 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29321.396491 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29321.401170 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.073717 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355993 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355993 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25069794 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25069794 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25069794 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25069794 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25069794 # number of overall hits -system.cpu.icache.overall_hits::total 25069794 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses -system.cpu.icache.overall_misses::total 1022 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56347500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56347500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56347500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56347500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56347500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56347500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25070816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25070816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25070816 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25070816 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25070816 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25070816 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.013382 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355964 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355964 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25069798 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25069798 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25069798 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25069798 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25069798 # number of overall hits +system.cpu.icache.overall_hits::total 25069798 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses +system.cpu.icache.overall_misses::total 1021 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 53787000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 53787000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 53787000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 53787000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 53787000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 53787000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25070819 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25070819 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25070819 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25070819 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25070819 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25070819 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55134.540117 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55134.540117 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55134.540117 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52680.705191 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52680.705191 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52680.705191 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52680.705191 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 175 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 109 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 58.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 36.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46510500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46510500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46510500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43651000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43651000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43651000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43651000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43651000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43651000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54398.245614 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54398.245614 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51053.801170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51053.801170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.014631 # Cycle average of tags in use -system.cpu.dcache.total_refs 152406162 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.593977 # Cycle average of tags in use +system.cpu.dcache.total_refs 152406549 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.668062 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 268976000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.014631 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999515 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999515 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38285655 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38285655 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152406162 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152406162 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152406162 # number of overall hits -system.cpu.dcache.overall_hits::total 152406162 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1165666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1165666 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1559201 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1559201 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1559201 # number of overall misses -system.cpu.dcache.overall_misses::total 1559201 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5490501500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5490501500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16777875500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16777875500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22268377000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22268377000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22268377000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22268377000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.668912 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 342752000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.593977 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999413 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999413 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120505 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120505 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38286044 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38286044 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152406549 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152406549 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152406549 # number of overall hits +system.cpu.dcache.overall_hits::total 152406549 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393537 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393537 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1165277 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1165277 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1558814 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1558814 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1558814 # number of overall misses +system.cpu.dcache.overall_misses::total 1558814 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5631779500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5631779500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16513706000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16513706000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22145485500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22145485500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22145485500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22145485500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -262,38 +420,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363 system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13951.748891 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13951.748891 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14393.381552 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14393.381552 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 42145 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4093205 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.320164 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19.357151 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029537 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029537 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010124 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010124 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14310.673456 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14310.673456 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14171.485406 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14171.485406 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14206.624716 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14206.624716 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14206.624716 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14206.624716 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 44530 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3993200 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3165 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 211455 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.069510 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18.884396 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks system.cpu.dcache.writebacks::total 436902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911503 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911503 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1103806 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1103806 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1103806 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1103806 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192305 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192305 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911114 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911114 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1103419 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1103419 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1103419 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1103419 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -302,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395605000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395605000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3804662000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3804662000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6200267000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6200267000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6200267000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6200267000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2467175500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2467175500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3742658000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3742658000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6209833500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6209833500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6209833500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6209833500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,28 +476,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11904.692097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11904.692097 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14969.377919 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14969.377919 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12260.353721 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12260.353721 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14725.424236 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14725.424236 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13636.147740 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13636.147740 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13636.147740 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13636.147740 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 917 # number of replacements -system.cpu.l2cache.tagsinuse 22852.343306 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22846.870251 # Cycle average of tags in use system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21651.877416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 719.990292 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 480.475597 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660763 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021972 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014663 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697398 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21647.185426 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 719.934202 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 479.750624 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660620 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021971 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014641 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697231 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits @@ -364,17 +522,17 @@ system.cpu.l2cache.demand_misses::total 26157 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 215882000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 261384000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1220308500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1220308500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45502000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1436190500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1481692500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45502000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1436190500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1481692500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42642500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 287448500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 330091000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1158328500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1158328500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42642500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1445777000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1488419500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42642500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1445777000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1488419500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -399,22 +557,22 @@ system.cpu.l2cache.demand_miss_rate::total 0.057330 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54104.637337 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52398.543689 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52687.764564 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57572.584450 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57572.584450 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 217 # number of cycles access was blocked +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50704.518430 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69769.053398 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66537.190083 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54648.447820 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54648.447820 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50704.518430 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57109.219466 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56903.295485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50704.518430 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57109.219466 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56903.295485 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 2538 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 230.727273 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -431,17 +589,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26157 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35251500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165390500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200642000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 961154000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 961154000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1126544500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1161796000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1126544500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1161796000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32026854 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 234985616 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 267012470 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891005143 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891005143 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32026854 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1125990759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1158017613 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32026854 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1125990759 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1158017613 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses @@ -453,17 +611,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41916.171225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.325243 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40443.862125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45346.008681 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45346.008681 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38081.871581 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57035.343689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53822.308002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42036.475892 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42036.475892 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 66988a872..28d2d6014 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,217 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133202 # Number of seconds simulated -sim_ticks 133202081500 # Number of ticks simulated -final_tick 133202081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133501 # Number of seconds simulated +sim_ticks 133501490500 # Number of ticks simulated +final_tick 133501490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 258977 # Simulator instruction rate (inst/s) -host_op_rate 258977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60995759 # Simulator tick rate (ticks/s) -host_mem_usage 213944 # Number of bytes of host memory used -host_seconds 2183.79 # Real time elapsed on the host +host_inst_rate 263578 # Simulator instruction rate (inst/s) +host_op_rate 263578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62218941 # Simulator tick rate (ticks/s) +host_mem_usage 217856 # Number of bytes of host memory used +host_seconds 2145.67 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627520 # Number of bytes read from this memory -system.physmem.bytes_read::total 1688832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627136 # Number of bytes read from this memory +system.physmem.bytes_read::total 1688448 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 58752 # Number of bytes written to this memory system.physmem.bytes_written::total 58752 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25430 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26388 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25424 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26382 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 918 # Number of write requests responded to by this memory system.physmem.num_writes::total 918 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 460293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12218428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12678721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 460293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 460293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 441074 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 441074 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 441074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 460293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12218428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13119795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 459261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12188149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12647409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 459261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 459261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 440085 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 440085 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 440085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 459261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12188149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13087494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26382 # Total number of read requests seen +system.physmem.writeReqs 918 # Total number of write requests seen +system.physmem.cpureqs 27300 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1688448 # Total number of bytes read from memory +system.physmem.bytesWritten 58752 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1688448 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 58752 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1728 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1633 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1563 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1614 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1549 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1659 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1668 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 67 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 55 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 72 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 49 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 42 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 53 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 133501465500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 26382 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 918 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 5916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 842096821 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1422758821 # Sum of mem lat for all requests +system.physmem.totBusLat 105516000 # Total cycles spent in databus access +system.physmem.totBankLat 475146000 # Total cycles spent in bank access +system.physmem.avgQLat 31923.00 # Average queueing delay per request +system.physmem.avgBankLat 18012.28 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 53935.28 # Average memory access latency +system.physmem.avgRdBW 12.65 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.44 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.65 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.44 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgWrQLen 10.07 # Average write queue length over time +system.physmem.readRowHits 17947 # Number of row buffer hits during reads +system.physmem.writeRowHits 124 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 13.51 # Row buffer hit rate for writes +system.physmem.avgGap 4890163.57 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123824653 # DTB read hits -system.cpu.dtb.read_misses 18111 # DTB read misses +system.cpu.dtb.read_hits 123834550 # DTB read hits +system.cpu.dtb.read_misses 17810 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123842764 # DTB read accesses -system.cpu.dtb.write_hits 40832181 # DTB write hits -system.cpu.dtb.write_misses 27219 # DTB write misses +system.cpu.dtb.read_accesses 123852360 # DTB read accesses +system.cpu.dtb.write_hits 40838763 # DTB write hits +system.cpu.dtb.write_misses 27151 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40859400 # DTB write accesses -system.cpu.dtb.data_hits 164656834 # DTB hits -system.cpu.dtb.data_misses 45330 # DTB misses +system.cpu.dtb.write_accesses 40865914 # DTB write accesses +system.cpu.dtb.data_hits 164673313 # DTB hits +system.cpu.dtb.data_misses 44961 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164702164 # DTB accesses -system.cpu.itb.fetch_hits 66456282 # ITB hits -system.cpu.itb.fetch_misses 39 # ITB misses +system.cpu.dtb.data_accesses 164718274 # DTB accesses +system.cpu.itb.fetch_hits 66485884 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66456321 # ITB accesses +system.cpu.itb.fetch_accesses 66485922 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,140 +225,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 266404164 # number of cpu cycles simulated +system.cpu.numCycles 267002982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78470433 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72835844 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3045377 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42694984 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41620121 # Number of BTB hits +system.cpu.BPredUnit.lookups 78490289 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72847815 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3050228 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42945683 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41640479 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1626012 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68396808 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 710651464 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78470433 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43246133 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119157795 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12900055 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 68967877 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1025 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66456282 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 943162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 266369518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.667916 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.466169 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1629196 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68428860 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710798920 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78490289 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43269675 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119192583 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12919622 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 69466328 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1179 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66485884 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 944600 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 266949725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.662670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.464655 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 147211723 55.27% 55.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10361930 3.89% 59.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11839981 4.44% 63.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10604273 3.98% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6985851 2.62% 70.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2662888 1.00% 71.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3489906 1.31% 72.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3104255 1.17% 73.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70108711 26.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 147757142 55.35% 55.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10366639 3.88% 59.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11845375 4.44% 63.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10612007 3.98% 67.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6988496 2.62% 70.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2666505 1.00% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3491309 1.31% 72.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3106869 1.16% 73.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70115383 26.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 266369518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.294554 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.667569 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85436450 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 53444664 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104479529 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13163939 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9844936 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3905187 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1152 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 701891597 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4998 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9844936 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93666462 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10915780 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 985 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104171147 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 47770208 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690014062 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37142293 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4412591 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527194579 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 906673497 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 906670681 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2816 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 266949725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293968 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.662139 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85457793 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 53956348 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104522021 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13153880 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9859683 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3909548 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1132 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 702023291 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5115 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9859683 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93690944 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11427696 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1077 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104202524 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 47767801 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690131281 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37133482 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4417196 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527277904 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906836279 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906833414 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2865 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63339690 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 89 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 106261883 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128976533 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42417035 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14777590 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9627827 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626339991 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608311695 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 332491 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60098493 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33347060 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 266369518 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.283714 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.821089 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63423015 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 100 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 106239657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128990605 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42428237 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14728779 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9525532 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626440684 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608386027 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 332535 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60195764 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33399973 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 74 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 266949725 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.279028 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823675 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 51762898 19.43% 19.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 53589578 20.12% 39.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53994858 20.27% 59.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 37661936 14.14% 73.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31638901 11.88% 85.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23703533 8.90% 94.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10074612 3.78% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3319964 1.25% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 623238 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52346454 19.61% 19.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 53679990 20.11% 39.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53956371 20.21% 59.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 37644200 14.10% 74.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31434632 11.78% 85.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23774675 8.91% 94.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10171294 3.81% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3315844 1.24% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 626265 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 266369518 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 266949725 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2702741 76.36% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 515259 14.56% 90.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 321532 9.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2688356 76.19% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 516717 14.64% 90.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323442 9.17% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 440952184 72.49% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7450 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441007420 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7412 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued @@ -228,84 +386,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126098325 20.73% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41253693 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126109044 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41262108 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608311695 # Type of FU issued -system.cpu.iq.rate 2.283417 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3539537 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005819 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1486861080 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 686441117 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598748300 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3856 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2343 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1699 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 611849296 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1936 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12174453 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608386027 # Type of FU issued +system.cpu.iq.rate 2.278574 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3528520 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005800 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1487578943 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686639010 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598810761 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3891 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2383 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1718 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 611912593 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1954 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12176241 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14462491 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33569 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4944 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2965714 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14476563 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33526 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4894 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2976916 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6773 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 155 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6758 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 144 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9844936 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 227072 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16439 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670244681 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1692417 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128976533 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42417035 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6445 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4188 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4944 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342659 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2208068 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3550727 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602499469 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123842867 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5812226 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9859683 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 765668 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16511 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670353065 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1690084 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128990605 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42428237 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6929 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3539 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4894 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1348243 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2207087 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3555330 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602565477 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123852464 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5820550 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43904609 # number of nop insts executed -system.cpu.iew.exec_refs 164718956 # number of memory reference insts executed -system.cpu.iew.exec_branches 66994757 # Number of branches executed -system.cpu.iew.exec_stores 40876089 # Number of stores executed -system.cpu.iew.exec_rate 2.261599 # Inst execution rate -system.cpu.iew.wb_sent 599990050 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598749999 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417673921 # num instructions producing a value -system.cpu.iew.wb_consumers 531386701 # num instructions consuming a value +system.cpu.iew.exec_nop 43912290 # number of nop insts executed +system.cpu.iew.exec_refs 164735376 # number of memory reference insts executed +system.cpu.iew.exec_branches 67003758 # Number of branches executed +system.cpu.iew.exec_stores 40882912 # Number of stores executed +system.cpu.iew.exec_rate 2.256774 # Inst execution rate +system.cpu.iew.wb_sent 600054937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598812479 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417702193 # num instructions producing a value +system.cpu.iew.wb_consumers 531441219 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.247525 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786007 # average fanout of values written-back +system.cpu.iew.wb_rate 2.242718 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.785980 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 68221188 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68328005 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3044329 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 256524582 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.346196 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.706570 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3049164 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 257090042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.341036 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.706336 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77999684 30.41% 30.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72616675 28.31% 58.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26248532 10.23% 68.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7743107 3.02% 71.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10914414 4.25% 76.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20847110 8.13% 84.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6257952 2.44% 86.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3103879 1.21% 88.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30793229 12.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 78450782 30.51% 30.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72765387 28.30% 58.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26309862 10.23% 69.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7783958 3.03% 72.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10791645 4.20% 76.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20794996 8.09% 84.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6257040 2.43% 86.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3054798 1.19% 87.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30881574 12.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 256524582 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 257090042 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +474,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30793229 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30881574 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 895745115 # The number of ROB reads -system.cpu.rob.rob_writes 1350023504 # The number of ROB writes -system.cpu.timesIdled 796 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34646 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 896329047 # The number of ROB reads +system.cpu.rob.rob_writes 1350251983 # The number of ROB writes +system.cpu.timesIdled 964 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53257 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.471051 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.471051 # CPI: Total CPI of All Threads -system.cpu.ipc 2.122911 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.122911 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848545483 # number of integer regfile reads -system.cpu.int_regfile_writes 492673182 # number of integer regfile writes -system.cpu.fp_regfile_reads 367 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cpi 0.472110 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.472110 # CPI: Total CPI of All Threads +system.cpu.ipc 2.118150 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.118150 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848643813 # number of integer regfile reads +system.cpu.int_regfile_writes 492723889 # number of integer regfile writes +system.cpu.fp_regfile_reads 378 # number of floating regfile reads +system.cpu.fp_regfile_writes 49 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 44 # number of replacements -system.cpu.icache.tagsinuse 827.655289 # Cycle average of tags in use -system.cpu.icache.total_refs 66454892 # Total number of references to valid blocks. +system.cpu.icache.replacements 45 # number of replacements +system.cpu.icache.tagsinuse 826.583116 # Cycle average of tags in use +system.cpu.icache.total_refs 66484511 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67880.379980 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 67910.634321 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 827.655289 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.404129 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.404129 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66454892 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66454892 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66454892 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66454892 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66454892 # number of overall hits -system.cpu.icache.overall_hits::total 66454892 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1390 # number of overall misses -system.cpu.icache.overall_misses::total 1390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48196500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48196500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48196500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48196500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48196500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48196500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66456282 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66456282 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66456282 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66456282 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66456282 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66456282 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 826.583116 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.403605 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.403605 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66484511 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66484511 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66484511 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66484511 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66484511 # number of overall hits +system.cpu.icache.overall_hits::total 66484511 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1373 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1373 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1373 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1373 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1373 # number of overall misses +system.cpu.icache.overall_misses::total 1373 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50434500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50434500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50434500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50434500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50434500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50434500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66485884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66485884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66485884 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66485884 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66485884 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66485884 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34673.741007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34673.741007 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34673.741007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34673.741007 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36733.066278 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36733.066278 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36733.066278 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36733.066278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36733.066278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36733.066278 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,286 +546,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 411 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 411 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 411 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 411 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 411 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 411 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 394 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 394 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 394 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 394 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 394 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 394 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 979 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 979 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 979 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35467500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35467500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35467500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35467500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35467500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35467500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36994000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36994000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36994000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36994000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36994000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36994000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36228.294178 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36228.294178 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36228.294178 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36228.294178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36228.294178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36228.294178 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37787.538304 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37787.538304 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37787.538304 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37787.538304 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37787.538304 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37787.538304 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460690 # number of replacements -system.cpu.dcache.tagsinuse 4093.413189 # Cycle average of tags in use -system.cpu.dcache.total_refs 149609253 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464786 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 321.888467 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 135777000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.413189 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999368 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999368 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 111075212 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 111075212 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38533998 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38533998 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 43 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 43 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 149609210 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 149609210 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 149609210 # number of overall hits -system.cpu.dcache.overall_hits::total 149609210 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 568128 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 568128 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 917323 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 917323 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1485451 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1485451 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1485451 # number of overall misses -system.cpu.dcache.overall_misses::total 1485451 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3277756500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3277756500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7625818400 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7625818400 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10903574900 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10903574900 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10903574900 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10903574900 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 111643340 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 111643340 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 460592 # number of replacements +system.cpu.dcache.tagsinuse 4091.681579 # Cycle average of tags in use +system.cpu.dcache.total_refs 149616636 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464688 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 321.972239 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 272105000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4091.681579 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998946 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998946 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 111082260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111082260 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38534319 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38534319 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149616579 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 149616579 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 149616579 # number of overall hits +system.cpu.dcache.overall_hits::total 149616579 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 569184 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 569184 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 917002 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 917002 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1486186 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1486186 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1486186 # number of overall misses +system.cpu.dcache.overall_misses::total 1486186 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5325915500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5325915500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10007471913 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10007471913 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15333387413 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15333387413 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15333387413 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15333387413 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111651444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111651444 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151094661 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151094661 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151094661 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151094661 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005089 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005089 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.023252 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.023252 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009831 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009831 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009831 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009831 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5769.397917 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 5769.397917 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8313.122423 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8313.122423 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7340.245420 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7340.245420 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 963 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 413 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 102 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.441176 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 37.545455 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151102765 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151102765 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151102765 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151102765 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005098 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005098 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.023244 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.023244 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009836 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009836 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009836 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009836 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9357.106841 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9357.106841 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10913.249822 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10913.249822 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10317.273486 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10317.273486 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10317.273486 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10317.273486 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1070 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 182 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.758242 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444931 # number of writebacks -system.cpu.dcache.writebacks::total 444931 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 357852 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 357852 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 662813 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 662813 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1020665 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1020665 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1020665 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1020665 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210276 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210276 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254510 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464786 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464786 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464786 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464786 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578667000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 578667000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1370952996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1370952996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1949619996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1949619996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1949619996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1949619996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2751.940307 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2751.940307 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5386.637052 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5386.637052 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4194.661621 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4194.661621 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4194.661621 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4194.661621 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 444845 # number of writebacks +system.cpu.dcache.writebacks::total 444845 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359021 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 359021 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 662477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 662477 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1021498 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1021498 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1021498 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1021498 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210163 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210163 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254525 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254525 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464688 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464688 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464688 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464688 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 841779000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 841779000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751356497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751356497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2593135497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2593135497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2593135497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2593135497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003075 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003075 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4005.362504 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4005.362504 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 6880.882023 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 6880.882023 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5580.379732 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 5580.379732 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5580.379732 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 5580.379732 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 947 # number of replacements -system.cpu.l2cache.tagsinuse 22961.963492 # Cycle average of tags in use -system.cpu.l2cache.total_refs 555516 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23381 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.759292 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22923.825111 # Cycle average of tags in use +system.cpu.l2cache.total_refs 555284 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23374 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.756482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21525.973194 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 820.941483 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 615.048815 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.656921 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025053 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018770 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.700744 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21489.572206 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 820.765317 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 613.487588 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.655810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.025048 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.018722 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.699580 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 205984 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 206005 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 444931 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 444931 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233372 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 233372 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 205882 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 205903 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 444845 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 444845 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 233382 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 233382 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 439356 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 439377 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 439264 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 439285 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 439356 # number of overall hits -system.cpu.l2cache.overall_hits::total 439377 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 439264 # number of overall hits +system.cpu.l2cache.overall_hits::total 439285 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4292 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5250 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21138 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21138 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5239 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21143 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21143 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 958 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25430 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26388 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 25424 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 26382 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 958 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25430 # number of overall misses -system.cpu.l2cache.overall_misses::total 26388 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34437000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 148748500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 183185500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 844655000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 844655000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34437000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 993403500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1027840500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34437000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 993403500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1027840500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 25424 # number of overall misses +system.cpu.l2cache.overall_misses::total 26382 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35966000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 406243000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 442209000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1225336000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1225336000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35966000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1631579000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1667545000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35966000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1631579000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1667545000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210276 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211255 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 444931 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 444931 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254510 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254510 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 210163 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 211142 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 444845 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 444845 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254525 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254525 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 464786 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 465765 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 464688 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 465667 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 464786 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 465765 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 464688 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 465667 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978550 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020411 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024851 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083054 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083054 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020370 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024813 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083068 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083068 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.978550 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054713 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056655 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.054712 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.056654 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.978550 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054713 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056655 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35946.764092 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34657.152842 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34892.476190 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.078437 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.078437 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.235155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 38951.057299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.235155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 38951.057299 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 198 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.054712 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.056654 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 37542.797495 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 94894.417192 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 84407.138767 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57954.689495 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57954.689495 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 37542.797495 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64174.756136 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 63207.679478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 37542.797495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64174.756136 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 63207.679478 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 77 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2.444444 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4.909091 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 918 # number of writebacks system.cpu.l2cache.writebacks::total 918 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4292 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5250 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21138 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21138 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4281 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5239 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21143 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21143 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25430 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26382 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25430 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26388 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31379500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135795500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167175000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778050000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778050000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31379500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913845500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 945225000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31379500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913845500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 945225000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 25424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26382 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32555439 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389619183 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 422174622 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1153721420 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1153721420 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32555439 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1543340603 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1575896042 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32555439 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1543340603 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1575896042 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020411 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024851 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083054 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083054 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020370 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083068 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083068 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054713 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056655 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054712 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056654 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054713 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056655 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32755.219207 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31639.212488 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31842.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.118081 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.118081 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.725521 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.259209 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.725521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.259209 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054712 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056654 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33982.712944 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 91011.255081 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80583.054400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54567.536300 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54567.536300 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33982.712944 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60704.082874 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59733.759457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33982.712944 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60704.082874 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59733.759457 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index c6b30ffc7..6dfebbc39 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,197 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.163008 # Number of seconds simulated -sim_ticks 163008222000 # Number of ticks simulated -final_tick 163008222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.163308 # Number of seconds simulated +sim_ticks 163308075000 # Number of ticks simulated +final_tick 163308075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178133 # Simulator instruction rate (inst/s) -host_op_rate 188229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50937760 # Simulator tick rate (ticks/s) -host_mem_usage 228580 # Number of bytes of host memory used -host_seconds 3200.15 # Real time elapsed on the host +host_inst_rate 134720 # Simulator instruction rate (inst/s) +host_op_rate 142356 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38594530 # Simulator tick rate (ticks/s) +host_mem_usage 233164 # Number of bytes of host memory used +host_seconds 4231.38 # Real time elapsed on the host sim_insts 570052710 # Number of instructions simulated sim_ops 602360916 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1771648 # Number of bytes read from this memory -system.physmem.bytes_read::total 1819712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 204352 # Number of bytes written to this memory -system.physmem.bytes_written::total 204352 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27682 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28433 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3193 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3193 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 294856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10868458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11163314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 294856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 294856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1253630 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1253630 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1253630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 294856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10868458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12416944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1771456 # Number of bytes read from this memory +system.physmem.bytes_read::total 1819968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 204864 # Number of bytes written to this memory +system.physmem.bytes_written::total 204864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27679 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28437 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3201 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3201 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 297058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10847326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11144385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 297058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 297058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1254463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1254463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1254463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 297058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10847326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12398848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 28438 # Total number of read requests seen +system.physmem.writeReqs 3201 # Total number of write requests seen +system.physmem.cpureqs 31639 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1819968 # Total number of bytes read from memory +system.physmem.bytesWritten 204864 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1819968 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 204864 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1839 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1814 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1796 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1898 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1846 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1677 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 220 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 240 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 185 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 204 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 177 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 173 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 163308062000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 28438 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 3201 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 10296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1146806136 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1807266136 # Sum of mem lat for all requests +system.physmem.totBusLat 113312000 # Total cycles spent in databus access +system.physmem.totBankLat 547148000 # Total cycles spent in bank access +system.physmem.avgQLat 40483.13 # Average queueing delay per request +system.physmem.avgBankLat 19314.74 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 63797.87 # Average memory access latency +system.physmem.avgRdBW 11.14 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 11.14 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.25 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgWrQLen 8.45 # Average write queue length over time +system.physmem.readRowHits 18527 # Number of row buffer hits during reads +system.physmem.writeRowHits 1851 # Number of row buffer hits during writes +system.physmem.readRowHitRate 65.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes +system.physmem.avgGap 5161606.31 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,106 +235,106 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 326016445 # number of cpu cycles simulated +system.cpu.numCycles 326616151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85521826 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80321411 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2409005 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47176245 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46862526 # Number of BTB hits +system.cpu.BPredUnit.lookups 85529383 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80327419 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2411594 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47239817 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46868068 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438689 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 908 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68838729 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669384047 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85521826 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48301215 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130014225 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13401210 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 116068554 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67395150 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 787497 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 325897750 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.188570 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.203934 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1438897 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 976 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68850265 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669456795 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85529383 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48306965 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130031029 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13412588 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 115987741 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67404301 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 787271 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 325854018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.189155 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.204154 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 195883756 60.11% 60.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20926266 6.42% 66.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4973061 1.53% 68.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14397687 4.42% 72.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8914249 2.74% 75.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9438407 2.90% 78.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4391608 1.35% 79.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5795696 1.78% 81.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61177020 18.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 195823205 60.10% 60.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20926796 6.42% 66.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4974411 1.53% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14401150 4.42% 72.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8914958 2.74% 75.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9439818 2.90% 78.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4393851 1.35% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5794662 1.78% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61185167 18.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 325897750 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.262324 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053222 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92928440 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93325217 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108744555 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19925503 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10974035 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4721193 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1619 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 705690133 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6091 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10974035 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107218931 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12903831 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39750 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114312743 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80448460 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 696999769 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59211261 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 18958262 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 603 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723690859 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3240622549 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3240622421 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 325854018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261865 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.049674 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92909986 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93274931 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108737205 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19949035 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10982861 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4721514 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1634 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 705778363 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5683 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10982861 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107200735 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12803432 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 41316 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114329497 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80496177 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697076108 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 75 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59278982 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 18940548 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 607 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723768936 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3240980671 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3240980543 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627419173 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96271686 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2053 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2007 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169155311 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172874803 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80609628 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21505343 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28086060 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681842513 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3260 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646713779 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1407547 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79314162 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197591004 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 331 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 325897750 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.984407 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.742434 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 96349763 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2017 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1967 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169248841 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172890049 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80617622 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21466789 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 27949042 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681898631 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3279 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646738917 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1408601 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79369513 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197745870 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 350 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 325854018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.984750 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.743125 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 67307339 20.65% 20.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84522408 25.94% 46.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 74985673 23.01% 69.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40267786 12.36% 81.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28844208 8.85% 90.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15117912 4.64% 95.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5722755 1.76% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6923607 2.12% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2206062 0.68% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67303060 20.65% 20.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84497277 25.93% 46.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74959252 23.00% 69.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40290304 12.36% 81.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28820123 8.84% 90.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15118844 4.64% 95.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5732215 1.76% 97.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6879322 2.11% 99.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2253621 0.69% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 325897750 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 325854018 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205384 5.40% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205105 5.40% 5.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available @@ -205,13 +363,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2833511 74.46% 79.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 766298 20.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2822579 74.31% 79.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 770924 20.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403852803 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6571 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403867506 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,84 +397,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166065084 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76789318 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166069409 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76795433 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646713779 # Type of FU issued -system.cpu.iq.rate 1.983685 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3805193 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005884 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624538012 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761171255 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638446114 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646738917 # Type of FU issued +system.cpu.iq.rate 1.980119 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3798608 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005873 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624539025 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761282766 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638466372 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650518952 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650537505 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30376789 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30381283 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23921985 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123764 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11533 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10388390 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23937231 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 124667 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11589 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10396384 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12747 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17143 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12749 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 16530 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10974035 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 319837 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 41126 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 681848951 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 703596 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172874803 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80609628 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1912 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10996 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4141 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11533 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1387510 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1519308 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2906818 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642524921 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163926120 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4188858 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10982861 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 283658 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42314 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 681905072 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 702708 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172890049 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80617622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1929 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 10939 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4841 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11589 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1389637 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1521620 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2911257 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642548978 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163933240 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4189939 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3178 # number of nop insts executed -system.cpu.iew.exec_refs 239918745 # number of memory reference insts executed -system.cpu.iew.exec_branches 74716876 # Number of branches executed -system.cpu.iew.exec_stores 75992625 # Number of stores executed -system.cpu.iew.exec_rate 1.970836 # Inst execution rate -system.cpu.iew.wb_sent 639915699 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638446130 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420790055 # num instructions producing a value -system.cpu.iew.wb_consumers 656091526 # num instructions consuming a value +system.cpu.iew.exec_nop 3162 # number of nop insts executed +system.cpu.iew.exec_refs 239931847 # number of memory reference insts executed +system.cpu.iew.exec_branches 74717690 # Number of branches executed +system.cpu.iew.exec_stores 75998607 # Number of stores executed +system.cpu.iew.exec_rate 1.967291 # Inst execution rate +system.cpu.iew.wb_sent 639936452 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638466388 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420738662 # num instructions producing a value +system.cpu.iew.wb_consumers 656063471 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.958325 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.641359 # average fanout of values written-back +system.cpu.iew.wb_rate 1.954791 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641308 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79497382 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 79553511 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2929 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2407463 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 314923716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.912720 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.240103 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2410069 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 314871158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.913040 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.240132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91160511 28.95% 28.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103755163 32.95% 61.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42928794 13.63% 75.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8971951 2.85% 78.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25547635 8.11% 86.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13484569 4.28% 90.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7640580 2.43% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1100606 0.35% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20333907 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91119458 28.94% 28.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103740730 32.95% 61.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42921464 13.63% 75.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8973909 2.85% 78.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25553482 8.12% 86.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13492783 4.29% 90.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7636973 2.43% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1102971 0.35% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20329388 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 314923716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 314871158 # Number of insts commited each cycle system.cpu.commit.committedInsts 570052761 # Number of instructions committed system.cpu.commit.committedOps 602360967 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -327,69 +485,69 @@ system.cpu.commit.branches 70892749 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533523531 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20333907 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20329388 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 976447546 # The number of ROB reads -system.cpu.rob.rob_writes 1374722217 # The number of ROB writes -system.cpu.timesIdled 15150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 118695 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 976455636 # The number of ROB reads +system.cpu.rob.rob_writes 1374843243 # The number of ROB writes +system.cpu.timesIdled 13781 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 762133 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570052710 # Number of Instructions Simulated system.cpu.committedOps 602360916 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570052710 # Number of Instructions Simulated -system.cpu.cpi 0.571906 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.571906 # CPI: Total CPI of All Threads -system.cpu.ipc 1.748540 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.748540 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3209706655 # number of integer regfile reads -system.cpu.int_regfile_writes 664060053 # number of integer regfile writes +system.cpu.cpi 0.572958 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.572958 # CPI: Total CPI of All Threads +system.cpu.ipc 1.745329 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.745329 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3209817028 # number of integer regfile reads +system.cpu.int_regfile_writes 664078534 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 904689637 # number of misc regfile reads +system.cpu.misc_regfile_reads 904771120 # number of misc regfile reads system.cpu.misc_regfile_writes 3106 # number of misc regfile writes -system.cpu.icache.replacements 58 # number of replacements -system.cpu.icache.tagsinuse 694.540428 # Cycle average of tags in use -system.cpu.icache.total_refs 67394031 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 818 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 82388.790954 # Average number of references to valid blocks. +system.cpu.icache.replacements 68 # number of replacements +system.cpu.icache.tagsinuse 692.511005 # Cycle average of tags in use +system.cpu.icache.total_refs 67403190 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 831 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 81110.938628 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 694.540428 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.339131 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.339131 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67394031 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67394031 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67394031 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67394031 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67394031 # number of overall hits -system.cpu.icache.overall_hits::total 67394031 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1119 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1119 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1119 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1119 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1119 # number of overall misses -system.cpu.icache.overall_misses::total 1119 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37389000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37389000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37389000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37389000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37389000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37389000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67395150 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67395150 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67395150 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67395150 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67395150 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67395150 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33412.868633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33412.868633 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33412.868633 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33412.868633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33412.868633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33412.868633 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 692.511005 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.338140 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.338140 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67403190 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67403190 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67403190 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67403190 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67403190 # number of overall hits +system.cpu.icache.overall_hits::total 67403190 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1111 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1111 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1111 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1111 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1111 # number of overall misses +system.cpu.icache.overall_misses::total 1111 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39508000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39508000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39508000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39508000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39508000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39508000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67404301 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67404301 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67404301 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67404301 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67404301 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67404301 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35560.756076 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35560.756076 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35560.756076 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35560.756076 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35560.756076 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35560.756076 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,309 +556,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 301 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 301 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 301 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 301 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 818 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 818 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 818 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 818 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 818 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 818 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28166000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28166000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28166000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28166000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28166000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28166000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 831 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 831 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 831 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 831 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 831 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 831 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29618500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29618500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29618500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29618500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29618500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29618500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34432.762836 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34432.762836 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34432.762836 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34432.762836 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34432.762836 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34432.762836 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35641.997593 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35641.997593 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35641.997593 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35641.997593 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35641.997593 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35641.997593 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440381 # number of replacements -system.cpu.dcache.tagsinuse 4094.318957 # Cycle average of tags in use -system.cpu.dcache.total_refs 200223099 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444477 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 450.468976 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 101578000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.318957 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999590 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999590 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 132093235 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 132093235 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 68126614 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 68126614 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1698 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1698 # number of LoadLockedReq hits +system.cpu.dcache.replacements 440563 # number of replacements +system.cpu.dcache.tagsinuse 4092.333527 # Cycle average of tags in use +system.cpu.dcache.total_refs 200225147 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444659 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 450.289204 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 278327000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.333527 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999105 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999105 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 132095464 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 132095464 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 68126436 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 68126436 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1695 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1695 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1552 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1552 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 200219849 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 200219849 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 200219849 # number of overall hits -system.cpu.dcache.overall_hits::total 200219849 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 216476 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 216476 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1290917 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1290917 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 200221900 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 200221900 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 200221900 # number of overall hits +system.cpu.dcache.overall_hits::total 200221900 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 216514 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 216514 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1291095 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1291095 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1507393 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1507393 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1507393 # number of overall misses -system.cpu.dcache.overall_misses::total 1507393 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1206496500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1206496500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11662167592 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11662167592 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 117000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 117000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12868664092 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12868664092 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12868664092 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12868664092 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 132309711 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 132309711 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1507609 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1507609 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1507609 # number of overall misses +system.cpu.dcache.overall_misses::total 1507609 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2275129000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2275129000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13136790063 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13136790063 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 217000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15411919063 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15411919063 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15411919063 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15411919063 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 132311978 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 132311978 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1720 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1720 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1717 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1717 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1552 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1552 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201727242 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201727242 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201727242 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201727242 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 201729509 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201729509 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201729509 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201729509 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001636 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001636 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018596 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018596 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012791 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012791 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007472 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007472 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007472 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007472 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5573.349933 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 5573.349933 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9034.018137 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9034.018137 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 5318.181818 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 5318.181818 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8537.033204 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8537.033204 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 54626 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3014 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.124088 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018599 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018599 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012813 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012813 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007473 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007473 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007473 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007473 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10507.999483 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10507.999483 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10174.921337 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10174.921337 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9863.636364 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9863.636364 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10222.756075 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10222.756075 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10222.756075 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10222.756075 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 57181 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3033 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.852951 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421091 # number of writebacks -system.cpu.dcache.writebacks::total 421091 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 19124 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 19124 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1043792 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1043792 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 421155 # number of writebacks +system.cpu.dcache.writebacks::total 421155 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18984 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 18984 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1043965 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1043965 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1062916 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1062916 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1062916 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1062916 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197352 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197352 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247125 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247125 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444477 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444477 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444477 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444477 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 592577000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 592577000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1461825592 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1461825592 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2054402592 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 2054402592 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2054402592 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2054402592 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1062949 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1062949 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1062949 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1062949 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197530 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197530 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247130 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247130 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444660 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444660 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444660 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444660 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1126335500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1126335500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1838542063 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1838542063 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2964877563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2964877563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2964877563 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2964877563 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001493 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002203 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002203 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002203 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002203 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3002.639953 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3002.639953 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5915.328647 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5915.328647 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4622.067266 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4622.067266 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4622.067266 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4622.067266 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002204 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002204 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 5702.098415 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5702.098415 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7439.574568 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7439.574568 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6667.740663 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 6667.740663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6667.740663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 6667.740663 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 4254 # number of replacements -system.cpu.l2cache.tagsinuse 21918.529183 # Cycle average of tags in use -system.cpu.l2cache.total_refs 505241 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 25292 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 19.976317 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 4260 # number of replacements +system.cpu.l2cache.tagsinuse 21882.249420 # Cycle average of tags in use +system.cpu.l2cache.total_refs 505380 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 25296 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 19.978653 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20774.501874 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 178.847286 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 965.180022 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633987 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.005458 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.029455 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.668900 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 63 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 191849 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 191912 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 421091 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 421091 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224937 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224937 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 63 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 416786 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 416849 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 63 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 416786 # number of overall hits -system.cpu.l2cache.overall_hits::total 416849 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 755 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 5503 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 6258 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 22188 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 22188 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 755 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 27691 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 28446 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 755 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 27691 # number of overall misses -system.cpu.l2cache.overall_misses::total 28446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27249500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 189324500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 216574000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 974356500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 974356500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27249500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1163681000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1190930500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27249500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1163681000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1190930500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 818 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 197352 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 198170 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 421091 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 421091 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247125 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247125 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 818 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 444477 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 445295 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 818 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 444477 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 445295 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922983 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027884 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.031579 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089785 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089785 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922983 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.062300 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063881 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922983 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.062300 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063881 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36092.052980 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.870616 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34607.542346 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43913.669551 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43913.669551 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36092.052980 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42023.798346 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 41866.360824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36092.052980 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42023.798346 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 41866.360824 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 27147 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 20736.940727 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 179.307999 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 966.000694 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.632841 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.005472 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.029480 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.667793 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 69 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 192020 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 192089 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 421155 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 421155 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224950 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 224950 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 69 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 416970 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 417039 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 69 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 416970 # number of overall hits +system.cpu.l2cache.overall_hits::total 417039 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 762 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 5510 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 6272 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 22180 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 22180 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 762 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 27690 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 28452 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 762 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 27690 # number of overall misses +system.cpu.l2cache.overall_misses::total 28452 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 28687000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 722594500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 751281500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1350770000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1350770000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 28687000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2073364500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2102051500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 28687000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2073364500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2102051500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 831 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 197530 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 198361 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 421155 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 421155 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247130 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247130 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 831 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 444660 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 445491 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 831 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 444660 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 445491 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.916968 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027894 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.031619 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089750 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089750 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916968 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.062272 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063867 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916968 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.062272 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063867 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 37646.981627 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 131142.377495 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 119783.402423 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60900.360685 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60900.360685 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 37646.981627 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74877.735645 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73880.623506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 37646.981627 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74877.735645 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73880.623506 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 28123 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2920 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 2973 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9.296918 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9.459469 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 3193 # number of writebacks -system.cpu.l2cache.writebacks::total 3193 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 3201 # number of writebacks +system.cpu.l2cache.writebacks::total 3201 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5494 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 6245 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22188 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 22188 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 27682 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 28433 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 27682 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 28433 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24797500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172259500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197057000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899948500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899948500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24797500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072208000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1097005500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24797500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072208000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1097005500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031513 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089785 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089785 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062280 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063852 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062280 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063852 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33019.307590 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.113578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31554.363491 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40560.145123 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40560.145123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5500 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6258 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22180 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 22180 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 27680 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 28438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 27680 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 28438 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25719146 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 701873552 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 727592698 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1275833198 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1275833198 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25719146 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1977706750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2003425896 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25719146 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1977706750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2003425896 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027844 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063835 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063835 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33930.271768 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 127613.373091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 116266.011186 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57521.785302 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57521.785302 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 293c634b6..532c2f1d1 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,173 +1,331 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.386987 # Number of seconds simulated -sim_ticks 386986985000 # Number of ticks simulated -final_tick 386986985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387215 # Number of seconds simulated +sim_ticks 387214915500 # Number of ticks simulated +final_tick 387214915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190632 # Simulator instruction rate (inst/s) -host_op_rate 191233 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52649747 # Simulator tick rate (ticks/s) -host_mem_usage 217240 # Number of bytes of host memory used -host_seconds 7350.22 # Real time elapsed on the host +host_inst_rate 118034 # Simulator instruction rate (inst/s) +host_op_rate 118406 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32618299 # Simulator tick rate (ticks/s) +host_mem_usage 226848 # Number of bytes of host memory used +host_seconds 11871.09 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1679104 # Number of bytes read from this memory -system.physmem.bytes_read::total 1757888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 78784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 78784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163264 # Number of bytes written to this memory -system.physmem.bytes_written::total 163264 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26236 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27467 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2551 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2551 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 203583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4338916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4542499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 203583 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 203583 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 421885 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 421885 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 421885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 203583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4338916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4964384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 78656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678976 # Number of bytes read from this memory +system.physmem.bytes_read::total 1757632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 78656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 78656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163392 # Number of bytes written to this memory +system.physmem.bytes_written::total 163392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26234 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27463 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2553 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2553 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 203133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4336031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4539164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 421967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 421967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 421967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4336031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4961131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27464 # Total number of read requests seen +system.physmem.writeReqs 2553 # Total number of write requests seen +system.physmem.cpureqs 30017 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1757632 # Total number of bytes read from memory +system.physmem.bytesWritten 163392 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1757632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 163392 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1703 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1758 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1623 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 172 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 387214887500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 27464 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 2553 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 6398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 916617704 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1530569704 # Sum of mem lat for all requests +system.physmem.totBusLat 109840000 # Total cycles spent in databus access +system.physmem.totBankLat 504112000 # Total cycles spent in bank access +system.physmem.avgQLat 33380.11 # Average queueing delay per request +system.physmem.avgBankLat 18358.05 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 55738.15 # Average memory access latency +system.physmem.avgRdBW 4.54 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 12.78 # Average write queue length over time +system.physmem.readRowHits 18350 # Number of row buffer hits during reads +system.physmem.writeRowHits 1423 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 55.74 # Row buffer hit rate for writes +system.physmem.avgGap 12899853.00 # Average gap between requests system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 773973971 # number of cpu cycles simulated +system.cpu.numCycles 774429832 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98196903 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88415122 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3785922 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66048945 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65663541 # Number of BTB hits +system.cpu.BPredUnit.lookups 98185573 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88408048 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3782090 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66047653 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65662573 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1365 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165893347 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648920679 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98196903 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65664906 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330423745 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21687705 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 259909474 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2700 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162828772 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 752135 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 773928223 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.136454 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.151019 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1362 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165872466 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648691883 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98185573 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65663935 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330391084 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21655373 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 260441698 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2775 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162813824 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 754521 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774378524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.134915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150373 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 443504478 57.31% 57.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74374556 9.61% 66.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37974673 4.91% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9085275 1.17% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28162152 3.64% 76.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18827829 2.43% 79.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11514662 1.49% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3870211 0.50% 81.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146614387 18.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 443987440 57.33% 57.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74371964 9.60% 66.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37979457 4.90% 71.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9083058 1.17% 73.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28156651 3.64% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18823006 2.43% 79.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11516280 1.49% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3872547 0.50% 81.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146588121 18.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 773928223 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126874 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.130460 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 216918337 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 211126972 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285339114 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42844971 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17698829 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642655288 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17698829 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 240878845 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33665029 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51866735 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303087743 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126731042 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631322359 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 30917915 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73728979 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3098650 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360964482 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755920727 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2722080159 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33840568 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774378524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126784 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.128911 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 216878479 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 211680769 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285325834 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42823062 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17670380 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642440106 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17670380 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 240852826 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34201656 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 51873963 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303043152 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126736547 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631096404 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 30920192 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73688032 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3125584 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360785655 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755532793 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2721694232 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33838561 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116194043 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2680701 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2696386 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 272557720 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438727279 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180254007 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255223658 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82981799 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517066880 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2635302 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460886365 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45400 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113758577 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136602100 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 391631 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 773928223 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.887625 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.429425 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116015216 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2681563 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2696177 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 272664149 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438656145 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180228164 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255185830 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83164069 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1516867754 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2636658 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460784709 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45870 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113563441 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136393501 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 392987 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774378524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.886396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.429689 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 144009666 18.61% 18.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 185251464 23.94% 42.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210317974 27.18% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131221648 16.96% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70752732 9.14% 95.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20294392 2.62% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7875333 1.02% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4040989 0.52% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 164025 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 144522601 18.66% 18.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 185174960 23.91% 42.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210422651 27.17% 69.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131027562 16.92% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70858421 9.15% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20344015 2.63% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7836220 1.01% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4026070 0.52% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 166024 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 773928223 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774378524 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90190 5.49% 5.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 99214 6.04% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1093274 66.56% 78.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 359776 21.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112088 6.69% 6.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 98938 5.90% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1079860 64.44% 77.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 384872 22.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867180921 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867100758 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2647347 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2647457 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -193,84 +351,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419785067 28.73% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171273030 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419766221 28.74% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171270273 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460886365 # Type of FU issued -system.cpu.iq.rate 1.887514 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1642454 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001124 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3679668823 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624597420 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444476565 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17719984 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9099813 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8555773 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453469070 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9059749 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215381487 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460784709 # Type of FU issued +system.cpu.iq.rate 1.886271 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1675758 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001147 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3679920663 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624205262 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444366362 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17748907 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9099237 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8557399 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453373806 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9086661 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215387676 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36214436 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54352 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 244694 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13405865 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36143302 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55137 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245231 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13380022 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3598 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3602 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17698829 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 443700 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14828 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613898358 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4123447 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438727279 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180254007 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2549639 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8198 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1497 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 244694 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2356359 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1563564 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3919923 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455334067 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417065579 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5552298 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17670380 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1032740 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 13152 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613687741 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4121479 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438656145 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180228164 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2550792 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8203 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245231 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2357183 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1559022 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3916205 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455236393 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417044165 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5548316 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94196176 # number of nop insts executed -system.cpu.iew.exec_refs 587643036 # number of memory reference insts executed -system.cpu.iew.exec_branches 89109340 # Number of branches executed -system.cpu.iew.exec_stores 170577457 # Number of stores executed -system.cpu.iew.exec_rate 1.880340 # Inst execution rate -system.cpu.iew.wb_sent 1453944636 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1453032338 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154452527 # num instructions producing a value -system.cpu.iew.wb_consumers 1205669839 # num instructions consuming a value +system.cpu.iew.exec_nop 94183329 # number of nop insts executed +system.cpu.iew.exec_refs 587622922 # number of memory reference insts executed +system.cpu.iew.exec_branches 89108958 # Number of branches executed +system.cpu.iew.exec_stores 170578757 # Number of stores executed +system.cpu.iew.exec_rate 1.879107 # Inst execution rate +system.cpu.iew.wb_sent 1453841644 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452923761 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154329978 # num instructions producing a value +system.cpu.iew.wb_consumers 1205560357 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.877366 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957520 # average fanout of values written-back +system.cpu.iew.wb_rate 1.876121 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957505 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 124266701 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124055997 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3785922 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 756230005 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.969670 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.506799 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3782090 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756708755 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.968423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.506505 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 237695032 31.43% 31.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276589849 36.57% 68.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43049426 5.69% 73.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54802104 7.25% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19618852 2.59% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13377170 1.77% 85.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30585382 4.04% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10542801 1.39% 90.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69969389 9.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 238213555 31.48% 31.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276540536 36.55% 68.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43021375 5.69% 73.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54822808 7.24% 80.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19645378 2.60% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13385764 1.77% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30553973 4.04% 89.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10565526 1.40% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69959840 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 756230005 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756708755 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -281,70 +439,70 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69969389 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69959840 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2299985729 # The number of ROB reads -system.cpu.rob.rob_writes 3245302839 # The number of ROB writes -system.cpu.timesIdled 3314 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 45748 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2300263324 # The number of ROB reads +system.cpu.rob.rob_writes 3244852707 # The number of ROB writes +system.cpu.timesIdled 1017 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51308 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552369 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552369 # CPI: Total CPI of All Threads -system.cpu.ipc 1.810383 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.810383 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980648344 # number of integer regfile reads -system.cpu.int_regfile_writes 1276312589 # number of integer regfile writes -system.cpu.fp_regfile_reads 16966196 # number of floating regfile reads -system.cpu.fp_regfile_writes 10497856 # number of floating regfile writes -system.cpu.misc_regfile_reads 593314657 # number of misc regfile reads +system.cpu.cpi 0.552695 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552695 # CPI: Total CPI of All Threads +system.cpu.ipc 1.809317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.809317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980527314 # number of integer regfile reads +system.cpu.int_regfile_writes 1276211568 # number of integer regfile writes +system.cpu.fp_regfile_reads 16969770 # number of floating regfile reads +system.cpu.fp_regfile_writes 10498210 # number of floating regfile writes +system.cpu.misc_regfile_reads 593297660 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 209 # number of replacements -system.cpu.icache.tagsinuse 1046.532429 # Cycle average of tags in use -system.cpu.icache.total_refs 162826872 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1358 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119901.967599 # Average number of references to valid blocks. +system.cpu.icache.replacements 217 # number of replacements +system.cpu.icache.tagsinuse 1045.896866 # Cycle average of tags in use +system.cpu.icache.total_refs 162811965 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1366 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119188.846999 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1046.532429 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.511002 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.511002 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162826872 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162826872 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162826872 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162826872 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162826872 # number of overall hits -system.cpu.icache.overall_hits::total 162826872 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1900 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1900 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1900 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1900 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1900 # number of overall misses -system.cpu.icache.overall_misses::total 1900 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60525500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60525500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60525500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60525500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60525500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60525500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162828772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162828772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162828772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162828772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162828772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162828772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31855.526316 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31855.526316 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31855.526316 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31855.526316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31855.526316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31855.526316 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1045.896866 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.510692 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.510692 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162811965 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162811965 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162811965 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162811965 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162811965 # number of overall hits +system.cpu.icache.overall_hits::total 162811965 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1859 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1859 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1859 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1859 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1859 # number of overall misses +system.cpu.icache.overall_misses::total 1859 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 53339000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 53339000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 53339000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 53339000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 53339000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 53339000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162813824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162813824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162813824 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162813824 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162813824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162813824 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000011 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000011 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28692.307692 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28692.307692 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28692.307692 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28692.307692 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28692.307692 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28692.307692 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,144 +511,144 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 541 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 541 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 541 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 541 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 541 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 541 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1359 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1359 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1359 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1359 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1359 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1359 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44484500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 44484500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44484500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 44484500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44484500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 44484500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 492 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 492 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 492 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 492 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 492 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 492 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1367 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1367 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1367 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1367 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1367 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1367 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 40091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 40091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 40091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 40091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 40091000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 40091000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32733.259750 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32733.259750 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32733.259750 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 32733.259750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32733.259750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 32733.259750 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29327.724945 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29327.724945 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29327.724945 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29327.724945 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29327.724945 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29327.724945 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 458293 # number of replacements -system.cpu.dcache.tagsinuse 4094.978889 # Cycle average of tags in use -system.cpu.dcache.total_refs 365901633 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 462389 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 791.328585 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 146096000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.978889 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999751 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999751 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200748020 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200748020 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 165152294 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 165152294 # number of WriteReq hits +system.cpu.dcache.replacements 458245 # number of replacements +system.cpu.dcache.tagsinuse 4094.164833 # Cycle average of tags in use +system.cpu.dcache.total_refs 365848378 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 462341 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.295555 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 304049000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.164833 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999552 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999552 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200718396 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200718396 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 165128663 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 165128663 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365900314 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365900314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365900314 # number of overall hits -system.cpu.dcache.overall_hits::total 365900314 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 892277 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 892277 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1694522 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1694522 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365847059 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365847059 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365847059 # number of overall hits +system.cpu.dcache.overall_hits::total 365847059 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 893632 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 893632 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1718153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1718153 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2586799 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2586799 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2586799 # number of overall misses -system.cpu.dcache.overall_misses::total 2586799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4566320500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4566320500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12448030999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12448030999 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 61000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 61000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17014351499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17014351499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17014351499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17014351499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201640297 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201640297 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2611785 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2611785 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2611785 # number of overall misses +system.cpu.dcache.overall_misses::total 2611785 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6936484000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6936484000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15815722499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15815722499 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 50000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 50000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22752206499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22752206499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22752206499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22752206499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201612028 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201612028 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368487113 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368487113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368487113 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368487113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004425 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004425 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010156 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010156 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368458844 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368458844 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368458844 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368458844 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004432 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004432 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010298 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010298 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007020 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007020 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007020 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007020 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5117.604174 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 5117.604174 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7346.042718 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7346.042718 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 8714.285714 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 8714.285714 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 6577.376711 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 6577.376711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 6577.376711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 6577.376711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007088 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007088 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007088 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007088 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7762.125797 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7762.125797 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9205.072249 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9205.072249 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 7142.857143 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 7142.857143 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8711.362727 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8711.362727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8711.362727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8711.362727 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443179 # number of writebacks -system.cpu.dcache.writebacks::total 443179 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 691990 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 691990 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432427 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1432427 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2124417 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2124417 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2124417 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2124417 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200287 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200287 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262095 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262095 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443162 # number of writebacks +system.cpu.dcache.writebacks::total 443162 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 693399 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 693399 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1456052 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1456052 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2149451 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2149451 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2149451 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2149451 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200233 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200233 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262101 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262101 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 462382 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 462382 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 462382 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 462382 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 552794000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 552794000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1426313000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1426313000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 47000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 47000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1979107000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1979107000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1979107000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1979107000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 462334 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 462334 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 462334 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 462334 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 847043500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 847043500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1875854500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1875854500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 36000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 36000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2722898000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2722898000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2722898000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2722898000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000993 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses @@ -501,154 +659,154 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001255 system.cpu.dcache.demand_mshr_miss_rate::total 0.001255 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001255 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001255 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2760.009387 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2760.009387 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5441.969515 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5441.969515 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 6714.285714 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 6714.285714 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4280.242310 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4280.242310 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4280.242310 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4280.242310 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4230.289213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4230.289213 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7156.991007 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7156.991007 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 5142.857143 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 5142.857143 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5889.460866 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 5889.460866 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5889.460866 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 5889.460866 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2680 # number of replacements -system.cpu.l2cache.tagsinuse 22390.965144 # Cycle average of tags in use -system.cpu.l2cache.total_refs 542233 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24313 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.302184 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2679 # number of replacements +system.cpu.l2cache.tagsinuse 22378.512464 # Cycle average of tags in use +system.cpu.l2cache.total_refs 542084 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24310 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.298807 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20751.792913 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 997.606125 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 641.566106 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633294 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.030445 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019579 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.683318 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 128 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 195840 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 195968 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443179 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 443179 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240313 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240313 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 128 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 436153 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 436281 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 128 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 436153 # number of overall hits -system.cpu.l2cache.overall_hits::total 436281 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1231 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4442 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5673 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21794 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21794 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1231 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26236 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27467 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1231 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26236 # number of overall misses -system.cpu.l2cache.overall_misses::total 27467 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42973500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 154131000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 197104500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 847072500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 847072500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42973500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1001203500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1044177000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42973500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1001203500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1044177000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1359 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 200282 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 201641 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 443179 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 443179 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 262107 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 262107 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1359 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 462389 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 463748 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1359 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 462389 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 463748 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.905813 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022179 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.028134 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083149 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083149 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.905813 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.056740 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059228 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.905813 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.056740 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059228 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34909.423233 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34698.559208 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34744.315177 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38867.234101 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38867.234101 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34909.423233 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38161.438481 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 38015.691557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34909.423233 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38161.438481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 38015.691557 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 20735.512523 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 999.090351 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 643.909590 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.632798 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.030490 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019651 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.682938 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 137 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 195795 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 195932 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 443162 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 443162 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 240312 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 240312 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 137 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 436107 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 436244 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 137 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 436107 # number of overall hits +system.cpu.l2cache.overall_hits::total 436244 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1230 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4433 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5663 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21801 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21801 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1230 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26234 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27464 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1230 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26234 # number of overall misses +system.cpu.l2cache.overall_misses::total 27464 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38568000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 446023500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 484591500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1290023500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1290023500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 38568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1736047000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1774615000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 38568000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1736047000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1774615000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1367 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 200228 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 201595 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 443162 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 443162 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 262113 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 262113 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1367 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 462341 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 463708 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1367 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 462341 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 463708 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.899781 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022140 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.028091 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083174 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083174 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.899781 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059227 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.899781 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056742 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059227 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31356.097561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100614.369501 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 85571.516864 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59172.675565 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59172.675565 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31356.097561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66175.459328 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 64616.042820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31356.097561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66175.459328 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 64616.042820 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 28 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2551 # number of writebacks -system.cpu.l2cache.writebacks::total 2551 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1231 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4442 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5673 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21794 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21794 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1231 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26236 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27467 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1231 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26236 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27467 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39025000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 138834500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 177859500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 777128500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 777128500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39025000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 915963000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 954988000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39025000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 915963000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 954988000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022179 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028134 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083149 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083149 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056740 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059228 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056740 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059228 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31701.868400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31254.952724 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31351.930196 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35657.910434 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35657.910434 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31701.868400 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34912.448544 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34768.558634 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31701.868400 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34912.448544 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34768.558634 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2553 # number of writebacks +system.cpu.l2cache.writebacks::total 2553 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1230 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4433 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5663 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21801 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21801 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1230 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26234 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27464 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1230 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26234 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27464 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34143480 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430451654 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 464595134 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1217504185 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1217504185 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34143480 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1647955839 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1682099319 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34143480 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1647955839 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1682099319 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028091 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083174 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083174 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059227 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 27758.926829 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 97101.658922 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 82040.461593 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55846.254071 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55846.254071 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 27758.926829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62817.558855 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61247.426413 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 27758.926829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62817.558855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61247.426413 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index bad8d0f8e..24127a6e1 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,276 +1,434 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.609798 # Number of seconds simulated -sim_ticks 609797568500 # Number of ticks simulated -final_tick 609797568500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.609434 # Number of seconds simulated +sim_ticks 609433847500 # Number of ticks simulated +final_tick 609433847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67150 # Simulator instruction rate (inst/s) -host_op_rate 123728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46530668 # Simulator tick rate (ticks/s) -host_mem_usage 230840 # Number of bytes of host memory used -host_seconds 13105.28 # Real time elapsed on the host +host_inst_rate 61609 # Simulator instruction rate (inst/s) +host_op_rate 113518 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42665232 # Simulator tick rate (ticks/s) +host_mem_usage 229588 # Number of bytes of host memory used +host_seconds 14284.09 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1694784 # Number of bytes read from this memory -system.physmem.bytes_read::total 1752896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58112 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 58176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1694272 # Number of bytes read from this memory +system.physmem.bytes_read::total 1752448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58176 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162816 # Number of bytes written to this memory system.physmem.bytes_written::total 162816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26481 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26473 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27382 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2544 # Number of write requests responded to by this memory system.physmem.num_writes::total 2544 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2779257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2874554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95297 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95297 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 267000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 267000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 267000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2779257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3141554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 95459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2780075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2875534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 95459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 95459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 267159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 267159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 267159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 95459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2780075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3142694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27384 # Total number of read requests seen +system.physmem.writeReqs 2544 # Total number of write requests seen +system.physmem.cpureqs 29928 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1752448 # Total number of bytes read from memory +system.physmem.bytesWritten 162816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1752448 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 13 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1781 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1776 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1670 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 155 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 609433834000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 27384 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 2544 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 26904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 56299249 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 811057249 # Sum of mem lat for all requests +system.physmem.totBusLat 109484000 # Total cycles spent in databus access +system.physmem.totBankLat 645274000 # Total cycles spent in bank access +system.physmem.avgQLat 2056.89 # Average queueing delay per request +system.physmem.avgBankLat 23575.10 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29631.99 # Average memory access latency +system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 8.89 # Average write queue length over time +system.physmem.readRowHits 17700 # Number of row buffer hits during reads +system.physmem.writeRowHits 1376 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 54.09 # Row buffer hit rate for writes +system.physmem.avgGap 20363333.13 # Average gap between requests system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1219595138 # number of cpu cycles simulated +system.cpu.numCycles 1218867696 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 153419281 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 153419281 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26709105 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 75190754 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 74807048 # Number of BTB hits +system.cpu.BPredUnit.lookups 154233173 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 154233173 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26682976 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 75825299 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 75424108 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180231048 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1488409356 # Number of instructions fetch has processed -system.cpu.fetch.Branches 153419281 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 74807048 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 400557825 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92407802 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 573234633 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 185924931 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9228337 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1219569114 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.084484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.278873 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180166559 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1483545531 # Number of instructions fetch has processed +system.cpu.fetch.Branches 154233173 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 75424108 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 400496189 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 91879143 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 573121383 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 424 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 185204471 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8524885 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1218826768 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.080610 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.274340 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 826230375 67.75% 67.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23815932 1.95% 69.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15671088 1.28% 70.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17469051 1.43% 72.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26718016 2.19% 74.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18180169 1.49% 76.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 27807273 2.28% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39426907 3.23% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 224250303 18.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 825549489 67.73% 67.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24308401 1.99% 69.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15365270 1.26% 70.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17994568 1.48% 72.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26708645 2.19% 74.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18181975 1.49% 76.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28608277 2.35% 78.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39394925 3.23% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 222715218 18.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1219569114 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125795 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.220413 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 289356881 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 496684656 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 275171365 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92810894 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 65545318 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2357736314 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 65545318 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 337721602 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 122595128 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1576 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 305744833 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387960657 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2261287899 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242284686 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120945759 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2627574208 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5773835618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5773831438 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4180 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1218826768 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126538 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.217151 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 289191573 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 496681660 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 275162301 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92749072 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 65042162 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2356227760 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 65042162 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 337598744 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 122716382 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1927 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 305616336 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387851217 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2259951612 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 313 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242131587 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 121014894 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2627036833 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5767802630 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5767798158 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4472 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 740678951 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 84 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 730447231 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 543232760 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220439884 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 349480208 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144920713 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2014741693 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 481 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784164311 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 260366 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 392823529 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 821144040 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1219569114 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.462946 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.418593 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 740141576 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 82 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 730432949 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 541717387 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220348120 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 348120905 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144711749 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2012299347 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1784417764 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 261262 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 390397150 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 813518141 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 472 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1218826768 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.464045 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.419425 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 363999611 29.85% 29.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 365670586 29.98% 59.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234855592 19.26% 79.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 140866108 11.55% 90.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60913141 4.99% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 40023537 3.28% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10789680 0.88% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1930984 0.16% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 519875 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 363571086 29.83% 29.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 365294377 29.97% 59.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234631055 19.25% 79.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141184624 11.58% 90.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60758407 4.98% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 40069639 3.29% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10832423 0.89% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1950212 0.16% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 534945 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1219569114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1218826768 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 467350 16.09% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2184649 75.23% 91.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 251796 8.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 467444 16.32% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2152766 75.14% 91.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 244877 8.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46816435 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065676196 59.73% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 478957046 26.84% 89.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192714634 10.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46817146 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065882672 59.73% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479009051 26.84% 89.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192708895 10.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784164311 # Type of FU issued -system.cpu.iq.rate 1.462915 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2903795 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001628 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4791061390 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2407739950 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1725073479 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 507 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1436 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740251451 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 220 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209520869 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1784417764 # Type of FU issued +system.cpu.iq.rate 1.463996 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2865087 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001606 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4790788107 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2402871988 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1725236233 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1508 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740465474 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209679766 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 124190639 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36910 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180735 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 32253827 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 122675266 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38585 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 181440 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 32162063 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2057 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 2083 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 65545318 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 120938 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15130 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2014742174 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63913352 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 543232760 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220439884 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7621 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180735 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2120344 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24738064 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26858408 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766248435 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474148133 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17915876 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 65042162 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 152720 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 14367 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2012299869 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63596984 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 541717387 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220348120 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6821 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 181440 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2121622 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24710303 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26831925 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766440348 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474226114 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17977416 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665987460 # number of memory reference insts executed -system.cpu.iew.exec_branches 110190116 # Number of branches executed -system.cpu.iew.exec_stores 191839327 # Number of stores executed -system.cpu.iew.exec_rate 1.448225 # Inst execution rate -system.cpu.iew.wb_sent 1726426595 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1725073583 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267591282 # num instructions producing a value -system.cpu.iew.wb_consumers 1828482722 # num instructions consuming a value +system.cpu.iew.exec_refs 666063645 # number of memory reference insts executed +system.cpu.iew.exec_branches 110217721 # Number of branches executed +system.cpu.iew.exec_stores 191837531 # Number of stores executed +system.cpu.iew.exec_rate 1.449247 # Inst execution rate +system.cpu.iew.wb_sent 1726559885 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1725236341 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267696731 # num instructions producing a value +system.cpu.iew.wb_consumers 1828647298 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.414464 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.693248 # average fanout of values written-back +system.cpu.iew.wb_rate 1.415442 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.693243 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 393250539 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 390808265 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26709142 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1154023796 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.405078 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.832959 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26683034 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1153784606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.405370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.832544 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 421087806 36.49% 36.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 412894237 35.78% 72.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87424698 7.58% 79.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122293813 10.60% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24525346 2.13% 92.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22502511 1.95% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19027826 1.65% 96.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12052514 1.04% 97.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32215045 2.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 420543726 36.45% 36.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 413309390 35.82% 72.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87337007 7.57% 79.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122231111 10.59% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24478385 2.12% 92.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22989251 1.99% 94.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18567232 1.61% 96.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12074031 1.05% 97.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32254473 2.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1154023796 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1153784606 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -281,68 +439,68 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32215045 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32254473 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3136553215 # The number of ROB reads -system.cpu.rob.rob_writes 4095072141 # The number of ROB writes -system.cpu.timesIdled 539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26024 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3133832323 # The number of ROB reads +system.cpu.rob.rob_writes 4089684452 # The number of ROB writes +system.cpu.timesIdled 614 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.385864 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.385864 # CPI: Total CPI of All Threads -system.cpu.ipc 0.721572 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.721572 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3541346034 # number of integer regfile reads -system.cpu.int_regfile_writes 1975100349 # number of integer regfile writes -system.cpu.fp_regfile_reads 104 # number of floating regfile reads -system.cpu.misc_regfile_reads 910400266 # number of misc regfile reads +system.cpu.cpi 1.385037 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.385037 # CPI: Total CPI of All Threads +system.cpu.ipc 0.722002 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.722002 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3541814029 # number of integer regfile reads +system.cpu.int_regfile_writes 1975313076 # number of integer regfile writes +system.cpu.fp_regfile_reads 108 # number of floating regfile reads +system.cpu.misc_regfile_reads 910517303 # number of misc regfile reads system.cpu.icache.replacements 21 # number of replacements -system.cpu.icache.tagsinuse 820.177123 # Cycle average of tags in use -system.cpu.icache.total_refs 185923597 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 817.668717 # Cycle average of tags in use +system.cpu.icache.total_refs 185203176 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 202310.769314 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 201526.850925 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 820.177123 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.400477 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.400477 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 185923597 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 185923597 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 185923597 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 185923597 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 185923597 # number of overall hits -system.cpu.icache.overall_hits::total 185923597 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1334 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1334 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1334 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1334 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1334 # number of overall misses -system.cpu.icache.overall_misses::total 1334 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44859000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44859000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44859000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44859000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44859000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44859000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 185924931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 185924931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 185924931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 185924931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 185924931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 185924931 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 817.668717 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.399252 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.399252 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 185203176 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 185203176 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 185203176 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 185203176 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 185203176 # number of overall hits +system.cpu.icache.overall_hits::total 185203176 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses +system.cpu.icache.overall_misses::total 1295 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39388000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39388000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39388000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39388000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39388000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39388000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 185204471 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 185204471 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 185204471 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 185204471 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 185204471 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 185204471 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33627.436282 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33627.436282 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33627.436282 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33627.436282 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30415.444015 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30415.444015 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30415.444015 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30415.444015 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30415.444015 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30415.444015 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,78 +509,78 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 415 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 415 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 415 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 415 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 415 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 415 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 376 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 376 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 376 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 376 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 376 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 919 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 919 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 919 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 919 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33142500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33142500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33142500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33142500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33142500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33142500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30110000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30110000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30110000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30110000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30110000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30110000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36063.656148 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36063.656148 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36063.656148 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36063.656148 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36063.656148 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36063.656148 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32763.873776 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32763.873776 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32763.873776 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32763.873776 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32763.873776 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32763.873776 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445640 # number of replacements -system.cpu.dcache.tagsinuse 4093.409130 # Cycle average of tags in use -system.cpu.dcache.total_refs 452355828 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449736 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1005.825257 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 723009000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.409130 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999367 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999367 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264416053 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264416053 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939775 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939775 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452355828 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452355828 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452355828 # number of overall hits -system.cpu.dcache.overall_hits::total 452355828 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 208185 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 208185 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246282 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246282 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 454467 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 454467 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 454467 # number of overall misses -system.cpu.dcache.overall_misses::total 454467 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 988643000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 988643000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1714858500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1714858500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2703501500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2703501500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2703501500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2703501500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264624238 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264624238 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 445574 # number of replacements +system.cpu.dcache.tagsinuse 4093.370170 # Cycle average of tags in use +system.cpu.dcache.total_refs 452274995 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 449670 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1005.793126 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 737045000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.370170 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999358 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999358 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264335239 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264335239 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939756 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939756 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452274995 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452274995 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452274995 # number of overall hits +system.cpu.dcache.overall_hits::total 452274995 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 208073 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 208073 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246301 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246301 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 454374 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 454374 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 454374 # number of overall misses +system.cpu.dcache.overall_misses::total 454374 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1068376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1068376500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1644748000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1644748000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2713124500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2713124500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2713124500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2713124500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264543312 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264543312 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452810295 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452810295 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452810295 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452810295 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 452729369 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452729369 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452729369 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452729369 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000787 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000787 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses @@ -431,14 +589,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001004 system.cpu.dcache.demand_miss_rate::total 0.001004 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001004 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001004 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4748.867594 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 4748.867594 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 6962.987551 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 6962.987551 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 5948.730051 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 5948.730051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 5948.730051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 5948.730051 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5134.623425 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5134.623425 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 6677.796680 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 6677.796680 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 5971.126209 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 5971.126209 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 5971.126209 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 5971.126209 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,32 +605,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428671 # number of writebacks -system.cpu.dcache.writebacks::total 428671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4720 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4720 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4729 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4729 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4729 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4729 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203465 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203465 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246273 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246273 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449738 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449738 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 449738 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 449738 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 561387500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 561387500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1222169500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1222169500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1783557000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1783557000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1783557000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1783557000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 428583 # number of writebacks +system.cpu.dcache.writebacks::total 428583 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4687 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4687 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4702 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4702 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4702 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4702 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203386 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203386 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246286 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246286 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449672 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449672 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 449672 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 449672 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 641587500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 641587500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1151947500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1151947500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1793535000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1793535000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1793535000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1793535000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000769 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000769 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -481,98 +639,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000993 system.cpu.dcache.demand_mshr_miss_rate::total 0.000993 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000993 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2759.135478 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2759.135478 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 4962.661355 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 4962.661355 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3965.768959 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3965.768959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3965.768959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3965.768959 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3154.531285 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3154.531285 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 4677.275606 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 4677.275606 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3988.540536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 3988.540536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3988.540536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 3988.540536 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2661 # number of replacements -system.cpu.l2cache.tagsinuse 22190.588854 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517940 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24220 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.384806 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2659 # number of replacements +system.cpu.l2cache.tagsinuse 22184.156099 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517708 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24213 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.381407 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20788.599128 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 725.869471 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 676.120254 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634418 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020634 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.677203 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 11 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 198908 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 198919 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428671 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428671 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224349 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224349 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 423257 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 423268 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 11 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 423257 # number of overall hits -system.cpu.l2cache.overall_hits::total 423268 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 908 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4552 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5460 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21929 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21929 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 908 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26481 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27389 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 908 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26481 # number of overall misses -system.cpu.l2cache.overall_misses::total 27389 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32192500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 157441500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 189634000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 751374000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 751374000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32192500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 908815500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 941008000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32192500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 908815500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 941008000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 20787.169449 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 726.088351 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 670.898299 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.634374 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.022158 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020474 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.677007 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 10 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 198821 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 198831 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 428583 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 428583 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224376 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 224376 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 10 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 423197 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 423207 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 10 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 423197 # number of overall hits +system.cpu.l2cache.overall_hits::total 423207 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 909 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4554 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5463 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21921 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21921 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 909 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26475 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27384 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 909 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26475 # number of overall misses +system.cpu.l2cache.overall_misses::total 27384 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29166500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 237800500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 266967000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 681146000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 681146000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 29166500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 918946500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 948113000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 29166500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 918946500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 948113000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 919 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 203460 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 204379 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 428671 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 428671 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 203375 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 204294 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 428583 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 428583 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246297 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246297 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 919 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 449738 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 450657 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 449672 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 450591 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 919 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 449738 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 450657 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.988030 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022373 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.026715 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089042 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089042 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.988030 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058881 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060776 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.988030 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058881 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060776 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35454.295154 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34587.324253 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34731.501832 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34263.942724 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34263.942724 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35454.295154 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34319.530984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34357.150681 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35454.295154 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34319.530984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34357.150681 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 449672 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 450591 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989119 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022392 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.026741 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089002 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089002 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989119 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058876 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060774 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989119 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058876 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060774 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32086.358636 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52217.940272 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48868.204283 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 31072.761279 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 31072.761279 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32086.358636 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34709.971671 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34622.881975 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32086.358636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34709.971671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34622.881975 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,50 +741,50 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 2544 # number of writebacks system.cpu.l2cache.writebacks::total 2544 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4552 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21929 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21929 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26481 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26481 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27389 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29285500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141665500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 170951000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 682609000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 682609000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29285500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 824274500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 853560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29285500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 824274500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 853560000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022373 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026715 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089042 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089042 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058881 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060776 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058881 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060776 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32252.753304 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31121.594903 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31309.706960 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31128.140818 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31128.140818 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32252.753304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31127.015596 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.336047 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32252.753304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31127.015596 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.336047 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 909 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4554 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5463 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21921 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21921 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 909 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27384 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 909 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26475 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27384 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25917391 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 220807955 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 246725346 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 596009194 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 596009194 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25917391 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 816817149 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 842734540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25917391 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 816817149 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 842734540 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989119 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022392 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026741 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089002 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089002 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058876 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060774 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989119 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058876 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060774 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28511.981298 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48486.595301 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45162.977485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27188.960084 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27188.960084 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28511.981298 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 30852.394674 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30774.705668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28511.981298 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30852.394674 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30774.705668 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |