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authorAli Saidi <Ali.Saidi@ARM.com>2013-02-15 17:40:14 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2013-02-15 17:40:14 -0500
commitbd31a5dc18def5972967a595d65266d1f9ff05cb (patch)
tree62897fcc906dfb88f50c52d4ba2129be7ccdc114 /tests/long/se/00.gzip
parent8cef39fb6742d834e383f533539ba90f72bbc7d9 (diff)
downloadgem5-bd31a5dc18def5972967a595d65266d1f9ff05cb.tar.xz
stats: update regressions for o3 changes in renaming and translation.
Diffstat (limited to 'tests/long/se/00.gzip')
-rw-r--r--tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini20
-rwxr-xr-xtests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout10
-rw-r--r--tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt12
3 files changed, 22 insertions, 20 deletions
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
index a9b3fe841..3e0d99c0f 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -479,6 +479,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@@ -495,7 +496,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -511,6 +512,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
@@ -518,25 +520,27 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
index 1884422eb..677217bc4 100755
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 15:52:06
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 13 2013 11:20:14
+gem5 started Feb 13 2013 14:16:35
+gem5 executing on u200540-lin
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -40,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 387279743500 because target called exit()
+Exiting @ tick 387315507500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index a9ed274c0..dd62eb55a 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.387316 # Nu
sim_ticks 387315507500 # Number of ticks simulated
final_tick 387315507500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 205717 # Simulator instruction rate (inst/s)
-host_op_rate 206366 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56864239 # Simulator tick rate (ticks/s)
-host_mem_usage 235456 # Number of bytes of host memory used
-host_seconds 6811.23 # Real time elapsed on the host
+host_inst_rate 183094 # Simulator instruction rate (inst/s)
+host_op_rate 183671 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50610731 # Simulator tick rate (ticks/s)
+host_mem_usage 233664 # Number of bytes of host memory used
+host_seconds 7652.83 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 76544 # Number of bytes read from this memory
@@ -259,7 +259,7 @@ system.cpu.rename.int_rename_lookups 2712307786 # Nu
system.cpu.rename.fp_rename_lookups 34121307 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 111594753 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2643942 # count of serializing insts renamed
+system.cpu.rename.serializingInsts 2643851 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2663506 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 271777312 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 436941235 # Number of loads inserted to the mem dependence unit.