Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.

4 files changed, 90 insertions, 90 deletions

diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
index 011acdd4e..182ad7ea2 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.271545                       # Nu
 sim_ticks                                271544682500                       # Number of ticks simulated
 final_tick                               271544682500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 105483                       # Simulator instruction rate (inst/s)
-host_op_rate                                   105483                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               47591638                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219440                       # Number of bytes of host memory used
-host_seconds                                  5705.72                       # Real time elapsed on the host
+host_inst_rate                                 142205                       # Simulator instruction rate (inst/s)
+host_op_rate                                   142205                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               64159611                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212920                       # Number of bytes of host memory used
+host_seconds                                  4232.33                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             53824                       # Number of bytes read from this memory
@@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 55134.540117
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total 55134.540117                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets        87500                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          175                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    58.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          167                       # number of ReadReq MSHR hits
@@ -276,12 +276,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545
 system.cpu.dcache.demand_avg_miss_latency::total 14281.915545                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 14281.915545                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     21072500                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets   2046602500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs        42145                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      4093205                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              3164                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets          211457                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  6660.082174                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets  9678.575313                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.320164                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    19.357151                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       436902                       # number of writebacks
@@ -410,11 +410,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs       108500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs          217                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                8                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 13562.500000                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs    27.125000                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 73ec0cee6..66988a872 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.133202                       # Nu
 sim_ticks                                133202081500                       # Number of ticks simulated
 final_tick                               133202081500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 189557                       # Simulator instruction rate (inst/s)
-host_op_rate                                   189557                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               44645563                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220464                       # Number of bytes of host memory used
-host_seconds                                  2983.55                       # Real time elapsed on the host
+host_inst_rate                                 258977                       # Simulator instruction rate (inst/s)
+host_op_rate                                   258977                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               60995759                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213944                       # Number of bytes of host memory used
+host_seconds                                  2183.79                       # Real time elapsed on the host
 sim_insts                                   565552443                       # Number of instructions simulated
 sim_ops                                     565552443                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             61312                       # Number of bytes read from this memory
@@ -480,12 +480,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data  7340.245420
 system.cpu.dcache.demand_avg_miss_latency::total  7340.245420                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data  7340.245420                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total  7340.245420                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       483496                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       206500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs          963                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          413                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs               102                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4740.156863                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 18772.727273                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.441176                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    37.545455                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       444931                       # number of writebacks
@@ -571,14 +571,14 @@ system.cpu.l2cache.overall_misses::total        26388                       # nu
 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     34437000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data    148748500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total    183185500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    844656996                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    844656996                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    844655000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    844655000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     34437000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    993405496                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1027842496                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    993403500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1027840500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     34437000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    993405496                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1027842496                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    993403500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1027840500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          979                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data       210276                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       211255                       # number of ReadReq accesses(hits+misses)
@@ -606,19 +606,19 @@ system.cpu.l2cache.overall_miss_rate::total     0.056655                       #
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35946.764092                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34657.152842                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 34892.476190                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.172864                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.172864                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.078437                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.078437                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35946.764092                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.313645                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 38951.132939                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.235155                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 38951.057299                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35946.764092                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.313645                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 38951.132939                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs       100996                       # number of cycles access was blocked
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.235155                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 38951.057299                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs          198                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs               81                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  1246.864198                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     2.444444                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
@@ -638,14 +638,14 @@ system.cpu.l2cache.overall_mshr_misses::total        26388
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     31379500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    135795500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total    167175000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    778051996                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    778051996                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    778050000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    778050000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     31379500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    913847496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    945226996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    913845500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    945225000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     31379500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    913847496                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    945226996                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    913845500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    945225000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.978550                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.020411                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.024851                       # mshr miss rate for ReadReq accesses
@@ -660,14 +660,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total     0.056655
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32755.219207                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31639.212488                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31842.857143                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.212508                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.212508                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.118081                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.118081                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32755.219207                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.804011                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.334849                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.725521                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.259209                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32755.219207                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.804011                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.334849                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.725521                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.259209                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 20eccd335..c6b30ffc7 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.163008                       # Nu
 sim_ticks                                163008222000                       # Number of ticks simulated
 final_tick                               163008222000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 104701                       # Simulator instruction rate (inst/s)
-host_op_rate                                   110635                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               29939476                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234836                       # Number of bytes of host memory used
-host_seconds                                  5444.59                       # Real time elapsed on the host
+host_inst_rate                                 178133                       # Simulator instruction rate (inst/s)
+host_op_rate                                   188229                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               50937760                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228580                       # Number of bytes of host memory used
+host_seconds                                  3200.15                       # Real time elapsed on the host
 sim_insts                                   570052710                       # Number of instructions simulated
 sim_ops                                     602360916                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             48064                       # Number of bytes read from this memory
@@ -502,12 +502,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data  8537.033204
 system.cpu.dcache.demand_avg_miss_latency::total  8537.033204                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data  8537.033204                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total  8537.033204                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     28514592                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         2000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs        54626                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            4                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              3014                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  9460.714001                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets         1000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    18.124088                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets            2                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       421091                       # number of writebacks
@@ -595,14 +595,14 @@ system.cpu.l2cache.overall_misses::total        28446                       # nu
 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     27249500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data    189324500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total    216574000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    974455801                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    974455801                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    974356500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    974356500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     27249500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1163780301                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1191029801                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1163681000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1190930500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     27249500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1163780301                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1191029801                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1163681000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1190930500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          818                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data       197352                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       198170                       # number of ReadReq accesses(hits+misses)
@@ -630,19 +630,19 @@ system.cpu.l2cache.overall_miss_rate::total     0.063881                       #
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36092.052980                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.870616                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 34607.542346                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43918.144988                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43918.144988                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43913.669551                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43913.669551                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36092.052980                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42027.384385                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 41869.851684                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42023.798346                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 41866.360824                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36092.052980                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42027.384385                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 41869.851684                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs     13672801                       # number of cycles access was blocked
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42023.798346                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 41866.360824                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs        27147                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs             2920                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  4682.466096                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     9.296918                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
@@ -671,14 +671,14 @@ system.cpu.l2cache.overall_mshr_misses::total        28433
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     24797500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    172259500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total    197057000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    900047801                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    900047801                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    899948500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    899948500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24797500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1072307301                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1097104801                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1072208000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1097005500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24797500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1072307301                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1097104801                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1072208000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1097005500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.918093                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.027839                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.031513                       # mshr miss rate for ReadReq accesses
@@ -693,14 +693,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total     0.063852
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33019.307590                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.113578                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31554.363491                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40564.620561                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40564.620561                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40560.145123                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40560.145123                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33019.307590                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38736.626725                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38585.615341                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38733.039520                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38582.122885                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33019.307590                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38736.626725                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38585.615341                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38733.039520                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38582.122885                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index b8b444d29..293c634b6 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.386987                       # Nu
 sim_ticks                                386986985000                       # Number of ticks simulated
 final_tick                               386986985000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 135169                       # Simulator instruction rate (inst/s)
-host_op_rate                                   135595                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               37331500                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223688                       # Number of bytes of host memory used
-host_seconds                                 10366.23                       # Real time elapsed on the host
+host_inst_rate                                 190632                       # Simulator instruction rate (inst/s)
+host_op_rate                                   191233                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52649747                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217240                       # Number of bytes of host memory used
+host_seconds                                  7350.22                       # Real time elapsed on the host
 sim_insts                                  1401188945                       # Number of instructions simulated
 sim_ops                                    1405604139                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             78784                       # Number of bytes read from this memory
@@ -453,11 +453,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data  6577.376711
 system.cpu.dcache.demand_avg_miss_latency::total  6577.376711                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data  6577.376711                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total  6577.376711                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         2000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs            4                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs         2000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed