diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/se/00.gzip | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/se/00.gzip')
27 files changed, 2824 insertions, 2823 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 201ee02a7..0e8616cf5 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 4b4f6933d..282b60660 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:24 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:09:56 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 271948359500 because target called exit() +Exiting @ tick 274137499500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index c0f2578f2..5b9902e79 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.271948 # Number of seconds simulated -sim_ticks 271948359500 # Number of ticks simulated -final_tick 271948359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.274137 # Number of seconds simulated +sim_ticks 274137499500 # Number of ticks simulated +final_tick 274137499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167086 # Simulator instruction rate (inst/s) -host_op_rate 167086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75497413 # Simulator tick rate (ticks/s) -host_mem_usage 219024 # Number of bytes of host memory used -host_seconds 3602.09 # Real time elapsed on the host +host_inst_rate 167497 # Simulator instruction rate (inst/s) +host_op_rate 167497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76292716 # Simulator tick rate (ticks/s) +host_mem_usage 218988 # Number of bytes of host memory used +host_seconds 3593.23 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,37 +23,37 @@ system.physmem.num_reads::cpu.data 25316 # Nu system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5957837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6155757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197920 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197920 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 209687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 209687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 209687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5957837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6365444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5910260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6106600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5910260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6314612 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517207 # DTB read hits +system.cpu.dtb.read_hits 114518785 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114519838 # DTB read accesses -system.cpu.dtb.write_hits 39661898 # DTB write hits +system.cpu.dtb.read_accesses 114521416 # DTB read accesses +system.cpu.dtb.write_hits 39662429 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664200 # DTB write accesses -system.cpu.dtb.data_hits 154179105 # DTB hits +system.cpu.dtb.write_accesses 39664731 # DTB write accesses +system.cpu.dtb.data_hits 154181214 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154184038 # DTB accesses -system.cpu.itb.fetch_hits 25013413 # ITB hits +system.cpu.dtb.data_accesses 154186147 # DTB accesses +system.cpu.itb.fetch_hits 25086764 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25013435 # ITB accesses +system.cpu.itb.fetch_accesses 25086786 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 543896720 # number of cpu cycles simulated +system.cpu.numCycles 548275000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86316674 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81371545 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36360802 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52676212 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34326876 # Number of BTB hits +system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81377487 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36366052 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52958494 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34331818 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 65.165802 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36904283 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49412391 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541655345 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541561070 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005510191 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1005415916 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 254971320 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155049936 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33767521 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2588294 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36355815 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26192089 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.124753 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412333421 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 255070177 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155050348 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36361065 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26186838 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.133148 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334459 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538321020 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 539843930 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 407697 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 54736228 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489160492 # Number of cycles cpu stages are processed. -system.cpu.activity 89.936283 # Percentage of cycles cpu is active +system.cpu.timesIdled 672410 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59138192 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489136808 # Number of cycles cpu stages are processed. +system.cpu.activity 89.213772 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.903698 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.910972 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.903698 # CPI: Total CPI of All Threads -system.cpu.ipc 1.106565 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.910972 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.106565 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 205017879 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338878841 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.305734 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 233023029 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310873691 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.156750 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 202072445 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341824275 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.847276 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 432365235 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111531485 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.506004 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 196896047 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347000673 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.799001 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 209383014 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338891986 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.810585 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 237433241 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310841759 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.694498 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 206489440 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341785560 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.338345 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 436702963 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.349649 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201266098 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347008902 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.291031 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.555018 # Cycle average of tags in use -system.cpu.icache.total_refs 25012389 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 728.512372 # Cycle average of tags in use +system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29254.256140 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.555018 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355740 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355740 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25012389 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25012389 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25012389 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25012389 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25012389 # number of overall hits -system.cpu.icache.overall_hits::total 25012389 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses -system.cpu.icache.overall_misses::total 1022 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56014500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56014500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56014500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56014500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56014500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56014500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25013411 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25013411 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25013411 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25013411 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25013411 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25013411 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 728.512372 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25085741 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25085741 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25085741 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25085741 # number of overall hits +system.cpu.icache.overall_hits::total 25085741 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses +system.cpu.icache.overall_misses::total 1021 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 57700000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 57700000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 57700000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 57700000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 57700000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 57700000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25086762 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25086762 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25086762 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25086762 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25086762 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25086762 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54808.708415 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54808.708415 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54808.708415 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54808.708415 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56513.222331 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56513.222331 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56513.222331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56513.222331 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45159500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45159500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45159500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45159500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45159500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45159500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46832500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46832500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46832500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46832500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46832500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46832500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52818.128655 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52818.128655 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54774.853801 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54774.853801 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.146809 # Cycle average of tags in use -system.cpu.dcache.total_refs 152406141 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.836595 # Cycle average of tags in use +system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.668016 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 260481000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.146809 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999548 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999548 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38285634 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38285634 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152406141 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152406141 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152406141 # number of overall hits -system.cpu.dcache.overall_hits::total 152406141 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1165687 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1165687 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1559222 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1559222 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1559222 # number of overall misses -system.cpu.dcache.overall_misses::total 1559222 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5944936500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5944936500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18222826500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18222826500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24167763000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24167763000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24167763000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24167763000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.836595 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120497 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38285544 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38285544 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152406041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152406041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152406041 # number of overall hits +system.cpu.dcache.overall_hits::total 152406041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393545 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393545 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1165777 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1165777 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1559322 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses +system.cpu.dcache.overall_misses::total 1559322 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7771987500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228669000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30228669000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38000656500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38000656500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38000656500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38000656500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363 system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15106.500057 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15106.500057 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15632.692567 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15632.692567 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15499.885841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15499.885841 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10505000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2188634000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2561 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 211460 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4101.913315 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10350.108768 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029550 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029550 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.662796 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.662796 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25930.061238 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25930.061238 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24369.986763 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24369.986763 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28255500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3561 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7934.709351 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks system.cpu.dcache.writebacks::total 436902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911524 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911524 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1103827 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1103827 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1103827 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1103827 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192313 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192313 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911614 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911614 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1103927 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1103927 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1103927 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1103927 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2433186000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2433186000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3829787500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3829787500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6262973500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6262973500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6262973500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6262973500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136800000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136800000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820778500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7820778500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820778500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7820778500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,35 +318,35 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12091.446688 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12091.446688 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15068.233771 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15068.233771 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.732070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.732070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.652219 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.652219 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 917 # number of replacements -system.cpu.l2cache.tagsinuse 22852.415153 # Cycle average of tags in use -system.cpu.l2cache.total_refs 538842 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22837.818259 # Cycle average of tags in use +system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.284159 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21652.224350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 719.469676 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 480.721127 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660773 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021956 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014670 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697400 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21635.297134 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 719.415397 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 483.105728 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.696955 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197093 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197107 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 197099 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 197113 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232986 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232986 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232980 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232980 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits @@ -364,24 +364,24 @@ system.cpu.l2cache.demand_misses::total 26157 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44029000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214315000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 258344000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1104963500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1104963500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44029000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1319278500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1363307500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44029000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1319278500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1363307500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 260244500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215316500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1215316500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1430177000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1475561000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1430177000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1475561000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254176 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254176 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses @@ -389,32 +389,32 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024551 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083389 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083389 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020475 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024550 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083391 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52353.151011 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52018.203883 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.984882 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52130.755803 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52130.755803 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52120.178155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52120.178155 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 766500 # number of cycles access was blocked +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.606796 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52458.072969 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57337.068315 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57337.068315 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56411.706235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56411.706235 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3459500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 116 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9462.962963 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29823.275862 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -431,39 +431,39 @@ system.cpu.l2cache.demand_mshr_misses::total 26157 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33775500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 164851000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198626500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 849849500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 849849500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33775500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1014700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1048476000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33775500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1014700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1048476000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954428500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954428500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119789500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1154935500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119789500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1154935500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024551 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083389 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40161.117717 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40012.378641 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40037.593227 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40094.805624 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40094.805624 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45028.708247 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45028.708247 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 53e4b73f0..5bc85930f 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index 21003a7f0..ddf76222f 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:29 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:10:10 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 133563007500 because target called exit() +Exiting @ tick 135504709500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 38226af10..9f9fc3c8f 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133563 # Number of seconds simulated -sim_ticks 133563007500 # Number of ticks simulated -final_tick 133563007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.135505 # Number of seconds simulated +sim_ticks 135504709500 # Number of ticks simulated +final_tick 135504709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 301381 # Simulator instruction rate (inst/s) -host_op_rate 301381 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71175252 # Simulator tick rate (ticks/s) -host_mem_usage 220044 # Number of bytes of host memory used -host_seconds 1876.54 # Real time elapsed on the host +host_inst_rate 302966 # Simulator instruction rate (inst/s) +host_op_rate 302966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72589653 # Simulator tick rate (ticks/s) +host_mem_usage 220016 # Number of bytes of host memory used +host_seconds 1866.72 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory -system.physmem.bytes_read::total 1688512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 58688 # Number of bytes written to this memory -system.physmem.bytes_written::total 58688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26383 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 917 # Number of write requests responded to by this memory -system.physmem.num_writes::total 917 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 457612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12184452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12642063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 457612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 457612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 439403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 439403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 439403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 457612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12184452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13081466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627200 # Number of bytes read from this memory +system.physmem.bytes_read::total 1688960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58880 # Number of bytes written to this memory +system.physmem.bytes_written::total 58880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25425 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26390 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 920 # Number of write requests responded to by this memory +system.physmem.num_writes::total 920 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 455778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12008439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12464216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 455778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 434524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 434524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 434524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 455778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12008439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12898740 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123849413 # DTB read hits -system.cpu.dtb.read_misses 20691 # DTB read misses +system.cpu.dtb.read_hits 123973202 # DTB read hits +system.cpu.dtb.read_misses 28801 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123870104 # DTB read accesses -system.cpu.dtb.write_hits 40835064 # DTB write hits -system.cpu.dtb.write_misses 30091 # DTB write misses +system.cpu.dtb.read_accesses 124002003 # DTB read accesses +system.cpu.dtb.write_hits 40826098 # DTB write hits +system.cpu.dtb.write_misses 43038 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40865155 # DTB write accesses -system.cpu.dtb.data_hits 164684477 # DTB hits -system.cpu.dtb.data_misses 50782 # DTB misses +system.cpu.dtb.write_accesses 40869136 # DTB write accesses +system.cpu.dtb.data_hits 164799300 # DTB hits +system.cpu.dtb.data_misses 71839 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164735259 # DTB accesses -system.cpu.itb.fetch_hits 66492910 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 164871139 # DTB accesses +system.cpu.itb.fetch_hits 66654125 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66492948 # ITB accesses +system.cpu.itb.fetch_accesses 66654164 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,247 +67,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267126016 # number of cpu cycles simulated +system.cpu.numCycles 271009420 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78502606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72859176 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3048930 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42879233 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41644328 # Number of BTB hits +system.cpu.BPredUnit.lookups 78550084 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72909802 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3049618 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42960098 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41697412 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1629564 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 215 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68435581 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 710898129 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78502606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43273892 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119207604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12936161 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 69569484 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1627945 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 225 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68633140 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 712310900 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78550084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43325357 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119402153 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13096957 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72942972 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 914 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66492910 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 942940 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267090859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.661634 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.464377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66654125 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 952316 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 270973447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.628711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.455670 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 147883255 55.37% 55.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10367188 3.88% 59.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11844651 4.43% 63.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10612793 3.97% 67.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6990815 2.62% 70.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2667876 1.00% 71.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3494727 1.31% 72.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3104174 1.16% 73.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70125380 26.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151571294 55.94% 55.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10370513 3.83% 59.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11843929 4.37% 64.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10611726 3.92% 68.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6997698 2.58% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2669321 0.99% 71.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3542857 1.31% 72.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3106060 1.15% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70260049 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267090859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293879 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.661284 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85625908 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 53897418 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104721883 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12969411 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9876239 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3910148 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702131172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4692 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9876239 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93864195 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11132886 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1433 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104174566 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48041540 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690226135 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36911224 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4900299 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527321421 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 906904042 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 906901104 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2938 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 270973447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289843 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.628362 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 86239898 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56889648 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104078394 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13772489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9993018 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3907857 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1149 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703284399 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4152 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9993018 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 94515684 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12291800 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1567 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104313558 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49857820 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 691204157 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5604 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37465189 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 6251536 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527653035 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 907560525 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 907557502 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3023 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63466532 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 116 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 106984731 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129019631 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42434130 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14712304 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9648397 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626510721 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 98 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608418192 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 334492 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60261200 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33473416 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 81 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267090859 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.277945 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.835634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63798146 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 98 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 109 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 110554649 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129201281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42494660 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14706454 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9724071 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626942555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608726605 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 349964 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60693556 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33842727 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 71 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270973447 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.246444 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.833475 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52595450 19.69% 19.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54748440 20.50% 40.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53400082 19.99% 60.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36696955 13.74% 73.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30804090 11.53% 85.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24162728 9.05% 94.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10693904 4.00% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3328381 1.25% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 660829 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55588929 20.51% 20.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55068872 20.32% 40.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 54063102 19.95% 60.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36829632 13.59% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31174989 11.50% 85.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23761374 8.77% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10484912 3.87% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3386761 1.25% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 614876 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267090859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270973447 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2950080 75.40% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 582636 14.89% 90.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 379789 9.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2718607 75.19% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 33 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 573635 15.86% 91.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323505 8.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441018930 72.49% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7345 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126131577 20.73% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41260299 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441168683 72.47% 72.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7348 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126287390 20.75% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41263140 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608418192 # Type of FU issued -system.cpu.iq.rate 2.277645 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3912544 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006431 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1488170355 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 686774500 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598832188 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2359 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1719 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612328769 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1967 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12182137 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608726605 # Type of FU issued +system.cpu.iq.rate 2.246146 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3615780 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005940 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1492388483 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 687638825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598965859 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3918 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2476 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1713 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612340430 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1955 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12180256 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14505589 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 34191 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4885 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2982809 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14687239 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33196 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5150 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3043339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6785 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 71183 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6743 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 162277 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9876239 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 295412 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670453714 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1691855 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129019631 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42434130 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 98 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 899 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7278 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4885 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1348504 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2206028 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3554532 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602596052 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123870207 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5822140 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9993018 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 593522 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 81920 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 671227772 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1733098 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129201281 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42494660 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9721 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 904 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5150 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1349008 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2205914 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3554922 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602873827 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 124002105 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5852778 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43942895 # number of nop insts executed -system.cpu.iew.exec_refs 164752686 # number of memory reference insts executed -system.cpu.iew.exec_branches 67005259 # Number of branches executed -system.cpu.iew.exec_stores 40882479 # Number of stores executed -system.cpu.iew.exec_rate 2.255849 # Inst execution rate -system.cpu.iew.wb_sent 600080079 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598833907 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417539542 # num instructions producing a value -system.cpu.iew.wb_consumers 531416482 # num instructions consuming a value +system.cpu.iew.exec_nop 44285129 # number of nop insts executed +system.cpu.iew.exec_refs 164888589 # number of memory reference insts executed +system.cpu.iew.exec_branches 67046898 # Number of branches executed +system.cpu.iew.exec_stores 40886484 # Number of stores executed +system.cpu.iew.exec_rate 2.224549 # Inst execution rate +system.cpu.iew.wb_sent 600233130 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598967572 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417280903 # num instructions producing a value +system.cpu.iew.wb_consumers 532263406 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.241766 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.785711 # average fanout of values written-back +system.cpu.iew.wb_rate 2.210136 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.783974 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 68437583 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69254422 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3047922 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 257214620 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.339902 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.706449 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3048560 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 260980429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.306138 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.692981 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78375558 30.47% 30.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72865724 28.33% 58.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26619590 10.35% 69.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8074736 3.14% 72.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10311668 4.01% 76.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20443429 7.95% 84.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6319286 2.46% 86.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3488714 1.36% 88.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30715915 11.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82002311 31.42% 31.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72802901 27.90% 59.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26180796 10.03% 69.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8233037 3.15% 72.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10839669 4.15% 76.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20863917 7.99% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6243794 2.39% 87.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3659698 1.40% 88.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30154306 11.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 257214620 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 260980429 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30715915 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30154306 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 896728862 # The number of ROB reads -system.cpu.rob.rob_writes 1350487768 # The number of ROB writes -system.cpu.timesIdled 758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35157 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 901873119 # The number of ROB reads +system.cpu.rob.rob_writes 1352238413 # The number of ROB writes +system.cpu.timesIdled 924 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35973 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.472328 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.472328 # CPI: Total CPI of All Threads -system.cpu.ipc 2.117175 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.117175 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848664377 # number of integer regfile reads -system.cpu.int_regfile_writes 492741272 # number of integer regfile writes -system.cpu.fp_regfile_reads 384 # number of floating regfile reads -system.cpu.fp_regfile_writes 47 # number of floating regfile writes +system.cpu.cpi 0.479194 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.479194 # CPI: Total CPI of All Threads +system.cpu.ipc 2.086837 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.086837 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848955638 # number of integer regfile reads +system.cpu.int_regfile_writes 492807399 # number of integer regfile writes +system.cpu.fp_regfile_reads 373 # number of floating regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 44 # number of replacements -system.cpu.icache.tagsinuse 827.496665 # Cycle average of tags in use -system.cpu.icache.total_refs 66491540 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 975 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 68196.451282 # Average number of references to valid blocks. +system.cpu.icache.replacements 45 # number of replacements +system.cpu.icache.tagsinuse 834.184340 # Cycle average of tags in use +system.cpu.icache.total_refs 66652701 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 988 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67462.247976 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 827.496665 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.404051 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.404051 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66491540 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66491540 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66491540 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66491540 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66491540 # number of overall hits -system.cpu.icache.overall_hits::total 66491540 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1370 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1370 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1370 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1370 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1370 # number of overall misses -system.cpu.icache.overall_misses::total 1370 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47830500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47830500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47830500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47830500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47830500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47830500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66492910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66492910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66492910 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66492910 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66492910 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66492910 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 834.184340 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.407317 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.407317 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66652701 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66652701 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66652701 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66652701 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66652701 # number of overall hits +system.cpu.icache.overall_hits::total 66652701 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1424 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1424 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1424 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1424 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1424 # number of overall misses +system.cpu.icache.overall_misses::total 1424 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 52187000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52187000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 52187000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52187000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 52187000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52187000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66654125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66654125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66654125 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66654125 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66654125 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66654125 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34912.773723 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34912.773723 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34912.773723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34912.773723 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36648.174157 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36648.174157 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36648.174157 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36648.174157 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36648.174157 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36648.174157 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,296 +390,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 395 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 395 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 395 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 395 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 395 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 395 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 975 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 975 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34096000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34096000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34096000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34096000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34096000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34096000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 988 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 988 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 988 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 988 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 988 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37189000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37189000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37189000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37189000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37189000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37189000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34970.256410 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34970.256410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34970.256410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34970.256410 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37640.688259 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37640.688259 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37640.688259 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37640.688259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37640.688259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37640.688259 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460470 # number of replacements -system.cpu.dcache.tagsinuse 4093.773805 # Cycle average of tags in use -system.cpu.dcache.total_refs 149240040 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464566 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 321.246152 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 124982000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.773805 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999456 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999456 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 111034129 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 111034129 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38205852 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38205852 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 59 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 59 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 149239981 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 149239981 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 149239981 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999361 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 111085210 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111085210 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37680869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37680869 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 148766079 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 148766079 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 148766079 # number of overall hits +system.cpu.dcache.overall_hits::total 148766079 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 577881 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 577881 # 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number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 7000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 7000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17349599733 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17349599733 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17349599733 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17349599733 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 111654544 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 111654544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2348333 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2348333 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2348333 # number of overall misses +system.cpu.dcache.overall_misses::total 2348333 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8220967500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8220967500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 45275400067 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45275400067 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 31000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 31000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53496367567 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53496367567 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53496367567 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53496367567 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111663091 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111663091 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151105865 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151105865 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151105865 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151105865 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005557 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005557 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031570 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031570 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.032787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.012348 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.012348 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.012348 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.012348 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7598.426054 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7598.426054 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10145.111788 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10145.111788 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9298.327084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9298.327084 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 113496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 187500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 51 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 51 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151114412 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151114412 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151114412 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151114412 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005175 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005175 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.044877 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.044877 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.039216 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.039216 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015540 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015540 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015540 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015540 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14226.056057 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14226.056057 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25572.791619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25572.791619 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22780.571396 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22780.571396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22780.571396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22780.571396 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 267496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 204500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4934.608696 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18750 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2286.290598 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20450 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444730 # number of writebacks -system.cpu.dcache.writebacks::total 444730 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 410277 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 410277 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 991041 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 991041 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 444923 # number of writebacks +system.cpu.dcache.writebacks::total 444923 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367661 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 367661 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2620523462 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006449 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006449 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3517.450437 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3517.450437 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7394.522073 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7394.522073 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1883609 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1883609 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1883609 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1883609 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210220 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6787885842 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6787885842 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6787885842 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6787885842 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003075 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003075 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7915.148416 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7915.148416 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20133.134811 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20133.134811 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14606.273491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14606.273491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14606.273491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14606.273491 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 820.682242 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 617.081022 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.656803 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025045 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018832 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.700680 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 205851 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 205871 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 444730 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 444730 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233287 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.979487 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054735 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056672 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.979487 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054735 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056672 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.314136 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34280.499184 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34291.396414 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34703.396244 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34703.396244 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1002606996 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 988 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 210216 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 211204 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 444923 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 444923 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254508 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254508 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 988 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 464724 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 465712 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 988 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 464724 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 465712 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.976721 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020431 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083023 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083023 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976721 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.054710 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.056666 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976721 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.054710 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.056666 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35878.238342 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34692.433062 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34909.980989 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38759.133743 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38759.133743 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35878.238342 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38072.153235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37991.928609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35878.238342 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38072.153235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37991.928609 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 81496 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10187 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 917 # number of writebacks -system.cpu.l2cache.writebacks::total 917 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 955 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4287 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5242 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21141 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21141 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 955 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25428 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26383 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 955 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25428 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26383 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29726000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 133026000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 162752000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 668424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 668424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29726000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 801450000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 831176000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29726000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 801450000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 831176000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020401 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024830 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083092 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083092 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056672 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056672 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31126.701571 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31030.090973 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31047.691721 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31617.425855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31617.425855 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 920 # number of writebacks +system.cpu.l2cache.writebacks::total 920 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4295 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5260 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21130 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21130 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25425 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26390 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25425 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26390 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31552000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135966500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167518500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 754186996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 754186996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31552000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 890153496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 921705496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31552000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 890153496 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 921705496 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.976721 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020431 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976721 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054710 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056666 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976721 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054710 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056666 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32696.373057 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31656.926659 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31847.623574 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35692.711595 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35692.711595 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32696.373057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35010.953628 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34926.316635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32696.373057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35010.953628 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34926.316635 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 265a2a956..a9c226ca1 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index be37b32c1..fcee711f2 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:37 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:11:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 762853846000 because target called exit() +Exiting @ tick 764109115000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index a7b4a0a92..6b056dd7e 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.762854 # Number of seconds simulated -sim_ticks 762853846000 # Number of ticks simulated -final_tick 762853846000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.764109 # Number of seconds simulated +sim_ticks 764109115000 # Number of ticks simulated +final_tick 764109115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2331221 # Simulator instruction rate (inst/s) -host_op_rate 2331221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2954822927 # Simulator tick rate (ticks/s) -host_mem_usage 219024 # Number of bytes of host memory used -host_seconds 258.17 # Real time elapsed on the host +host_inst_rate 2465110 # Simulator instruction rate (inst/s) +host_op_rate 2465110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3129668646 # Simulator tick rate (ticks/s) +host_mem_usage 218984 # Number of bytes of host memory used +host_seconds 244.15 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25315 # Nu system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory system.physmem.num_writes::total 883 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 65690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2123814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2189505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 65690 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 65690 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 74080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 74080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 74080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 65690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2123814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2263584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 65582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2120325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2185908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 65582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 65582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 73958 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 73958 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 73958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 65582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2120325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2259866 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1525707692 # number of cpu cycles simulated +system.cpu.numCycles 1528218230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1525707692 # Number of busy cycles +system.cpu.num_busy_cycles 1528218230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.359193 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.286058 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.359193 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328789 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328789 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.286058 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328753 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328753 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44016000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44016000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44016000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44016000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44016000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44016000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44165000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44165000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44165000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44165000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44165000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44165000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55366.037736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55366.037736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55366.037736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55366.037736 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55553.459119 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55553.459119 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55553.459119 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55553.459119 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41780000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41780000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41780000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41780000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41780000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41780000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52553.459119 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52553.459119 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.177385 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.128141 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 571210000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.177385 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999555 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999555 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 590218000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.128141 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2990372000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2990372000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4448388000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4448388000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7438760000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7438760000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7438760000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7438760000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2991812000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2991812000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4452609000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4452609000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7444421000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7444421000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7444421000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7444421000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14860.320426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14860.320426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17502.106916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17502.106916 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16334.742367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16334.742367 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14867.476346 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14867.476346 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17518.714368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17518.714368 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16347.173333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16347.173333 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2388116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2388116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3690120000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3690120000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078236000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6078236000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078236000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6078236000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11867.476346 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11867.476346 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14518.714368 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14518.714368 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 903 # number of replacements -system.cpu.l2cache.tagsinuse 22842.001450 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22839.375690 # Cycle average of tags in use system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21648.658638 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 668.310399 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 525.032413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660665 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.020395 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016023 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697083 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21645.673483 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 668.235332 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 525.466875 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660574 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.020393 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016036 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697002 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index d26a36061..3e3a921c2 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 2a1e3a459..71d01f629 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:37:13 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:22:13 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 163291004000 because target called exit() +Exiting @ tick 164812294500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 4e7834f0d..ad067cb13 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.163291 # Number of seconds simulated -sim_ticks 163291004000 # Number of ticks simulated -final_tick 163291004000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164812 # Number of seconds simulated +sim_ticks 164812294500 # Number of ticks simulated +final_tick 164812294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225808 # Simulator instruction rate (inst/s) -host_op_rate 238605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64682367 # Simulator tick rate (ticks/s) -host_mem_usage 234804 # Number of bytes of host memory used -host_seconds 2524.51 # Real time elapsed on the host -sim_insts 570052735 # Number of instructions simulated -sim_ops 602360941 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1770240 # Number of bytes read from this memory -system.physmem.bytes_read::total 1818112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 203264 # Number of bytes written to this memory -system.physmem.bytes_written::total 203264 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27660 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28408 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3176 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3176 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 293170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10841014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11134183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 293170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 293170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1244796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1244796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1244796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 293170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10841014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12378980 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 186522 # Simulator instruction rate (inst/s) +host_op_rate 197094 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53926880 # Simulator tick rate (ticks/s) +host_mem_usage 234728 # Number of bytes of host memory used +host_seconds 3056.22 # Real time elapsed on the host +sim_insts 570052720 # Number of instructions simulated +sim_ops 602360926 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1770688 # Number of bytes read from this memory +system.physmem.bytes_read::total 1818880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 203712 # Number of bytes written to this memory +system.physmem.bytes_written::total 203712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 753 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27667 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28420 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3183 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3183 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 292405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10743665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11036070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 292405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 292405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1236024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1236024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1236024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 292405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10743665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12272094 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 326582009 # number of cpu cycles simulated +system.cpu.numCycles 329624590 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85496783 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80297868 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2361759 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47129611 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46810915 # Number of BTB hits +system.cpu.BPredUnit.lookups 85521151 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80320824 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2362426 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47149352 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46837857 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1442822 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 939 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68930661 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669745010 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85496783 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48253737 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130048027 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13475244 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 116341672 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1443093 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 967 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68941793 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669884423 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85521151 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48280950 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130081078 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13500418 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119459363 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 687 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67499108 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 807540 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 326356874 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.186850 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.203825 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67507706 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807322 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 329533342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166395 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.195647 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 196309073 60.15% 60.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20957347 6.42% 66.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4946491 1.52% 68.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14317000 4.39% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8978746 2.75% 75.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9407391 2.88% 78.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4385745 1.34% 79.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5814869 1.78% 81.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61240212 18.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 199452502 60.53% 60.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20948711 6.36% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4950582 1.50% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14318865 4.35% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8979173 2.72% 75.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9434613 2.86% 78.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4385548 1.33% 79.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5816824 1.77% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61246524 18.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 326356874 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261793 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.050771 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93064197 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93574356 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108736934 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19947205 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11034182 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4784985 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1738 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706036905 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6288 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11034182 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107346412 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13092326 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46822 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114338400 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80498732 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697255622 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59224108 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19051405 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 625 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723858007 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241539667 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241539539 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 329533342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259450 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.032265 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93614628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96158900 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108189069 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20521940 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11048805 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4786965 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1741 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 706200361 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6232 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11048805 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107837275 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14152380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114426981 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82018229 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697376779 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 154 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59681814 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20119568 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 658 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723981883 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3242139777 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3242139649 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419213 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96438794 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6501 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6457 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169431016 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172916819 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80629893 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21434071 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 27751379 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 682016489 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4774 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646845145 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1424192 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79472523 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197906343 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1840 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 326356874 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.982018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.741007 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96562694 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6452 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6400 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169999822 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172950765 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80642212 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21622434 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28168591 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 682111188 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4787 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646911424 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1425738 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79572817 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 198257861 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1856 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 329533342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.963114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.727328 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 67525997 20.69% 20.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84702389 25.95% 46.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 74951613 22.97% 69.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40526195 12.42% 82.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28606192 8.77% 90.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15221367 4.66% 95.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5979021 1.83% 97.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6497584 1.99% 99.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2346516 0.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69109124 20.97% 20.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85502964 25.95% 46.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75902592 23.03% 69.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 41003361 12.44% 82.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28586147 8.67% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15096087 4.58% 95.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5691070 1.73% 97.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6514226 1.98% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2127771 0.65% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 326356874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 329533342 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 204976 4.99% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2983992 72.63% 77.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 919347 22.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205938 5.35% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2629007 68.31% 73.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1013747 26.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403923414 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403964135 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6565 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,159 +239,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166112206 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76802956 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166144548 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76796173 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646845145 # Type of FU issued -system.cpu.iq.rate 1.980651 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4108315 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006351 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1625579635 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761505232 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638567907 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646911424 # Type of FU issued +system.cpu.iq.rate 1.962570 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3848692 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005949 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1628630584 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761700595 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638589501 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650953440 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650760096 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30447417 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30444381 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23963996 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 129674 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11684 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10408650 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23997945 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 128330 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12058 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10420972 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12812 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 13814 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12743 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 33964 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11034182 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 314683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 40041 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682087415 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 655237 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172916819 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80629893 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3420 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12514 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1466 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11684 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1312850 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1582780 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2895630 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642706502 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163991051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4138643 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11048805 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 670880 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 80193 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682182162 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 671811 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172950765 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80642212 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3436 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21821 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3936 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12058 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1313101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1582689 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2895790 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642749974 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 164016211 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4161450 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66152 # number of nop insts executed -system.cpu.iew.exec_refs 240011876 # number of memory reference insts executed -system.cpu.iew.exec_branches 74666851 # Number of branches executed -system.cpu.iew.exec_stores 76020825 # Number of stores executed -system.cpu.iew.exec_rate 1.967979 # Inst execution rate -system.cpu.iew.wb_sent 640060409 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638567923 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420584081 # num instructions producing a value -system.cpu.iew.wb_consumers 656222195 # num instructions consuming a value +system.cpu.iew.exec_nop 66187 # number of nop insts executed +system.cpu.iew.exec_refs 240022824 # number of memory reference insts executed +system.cpu.iew.exec_branches 74673150 # Number of branches executed +system.cpu.iew.exec_stores 76006613 # Number of stores executed +system.cpu.iew.exec_rate 1.949945 # Inst execution rate +system.cpu.iew.wb_sent 640083965 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638589517 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419034564 # num instructions producing a value +system.cpu.iew.wb_consumers 650591569 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.955306 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.640917 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937324 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644082 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570052786 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602360992 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 79735934 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2934 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2422217 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 315322693 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.910300 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.242360 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570052771 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602360977 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79830456 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2422889 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 318484538 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.891335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233401 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91618801 29.06% 29.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103774162 32.91% 61.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42992063 13.63% 75.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8898067 2.82% 78.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25658030 8.14% 86.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13146506 4.17% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7589457 2.41% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1157745 0.37% 93.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20487862 6.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93876011 29.48% 29.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104566020 32.83% 62.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43293403 13.59% 75.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8795442 2.76% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26035150 8.17% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12750697 4.00% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7572699 2.38% 93.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1269382 0.40% 93.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20325734 6.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 315322693 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052786 # Number of instructions committed -system.cpu.commit.committedOps 602360992 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 318484538 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052771 # Number of instructions committed +system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174066 # Number of memory references committed -system.cpu.commit.loads 148952823 # Number of loads committed +system.cpu.commit.refs 219174060 # Number of memory references committed +system.cpu.commit.loads 148952820 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828830 # Number of branches committed +system.cpu.commit.branches 70828827 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523551 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20487862 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20325734 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 976931145 # The number of ROB reads -system.cpu.rob.rob_writes 1375260810 # The number of ROB writes -system.cpu.timesIdled 9894 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 225135 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052735 # Number of Instructions Simulated -system.cpu.committedOps 602360941 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052735 # Number of Instructions Simulated -system.cpu.cpi 0.572898 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.572898 # CPI: Total CPI of All Threads -system.cpu.ipc 1.745512 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.745512 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210543463 # number of integer regfile reads -system.cpu.int_regfile_writes 664223214 # number of integer regfile writes +system.cpu.rob.rob_reads 980349625 # The number of ROB reads +system.cpu.rob.rob_writes 1375464218 # The number of ROB writes +system.cpu.timesIdled 6594 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 91248 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052720 # Number of Instructions Simulated +system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated +system.cpu.cpi 0.578235 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.578235 # CPI: Total CPI of All Threads +system.cpu.ipc 1.729400 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.729400 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210711882 # number of integer regfile reads +system.cpu.int_regfile_writes 664273083 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905101471 # number of misc regfile reads -system.cpu.misc_regfile_writes 3116 # number of misc regfile writes -system.cpu.icache.replacements 67 # number of replacements -system.cpu.icache.tagsinuse 689.277263 # Cycle average of tags in use -system.cpu.icache.total_refs 67498009 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 823 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 82014.591738 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905231466 # number of misc regfile reads +system.cpu.misc_regfile_writes 3110 # number of misc regfile writes +system.cpu.icache.replacements 57 # number of replacements +system.cpu.icache.tagsinuse 692.699547 # Cycle average of tags in use +system.cpu.icache.total_refs 67506606 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 819 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 82425.648352 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 689.277263 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.336561 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.336561 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67498009 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67498009 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67498009 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67498009 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67498009 # number of overall hits -system.cpu.icache.overall_hits::total 67498009 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1099 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1099 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1099 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1099 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1099 # number of overall misses -system.cpu.icache.overall_misses::total 1099 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 36702500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 36702500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 36702500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 36702500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 36702500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 36702500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67499108 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67499108 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67499108 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67499108 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67499108 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67499108 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 692.699547 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.338232 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.338232 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67506606 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002278 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002278 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036878 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.036878 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012231 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012231 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014185 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014185 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014185 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014185 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12252.420824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12252.420824 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15781.014745 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15781.014745 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11285.714286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11285.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15409.281291 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15409.281291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15409.281291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15409.281291 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30249535 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 47000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3035 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9966.897858 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421148 # number of writebacks -system.cpu.dcache.writebacks::total 421148 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 30933 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 30933 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1043483 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1043483 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1074416 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1074416 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1074416 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1074416 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197467 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197467 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247123 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247123 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444590 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444590 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444590 # 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mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001493 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 420982 # number of writebacks +system.cpu.dcache.writebacks::total 420982 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104126 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2312844 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2312844 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 21 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 21 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2416970 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2416970 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2416970 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2416970 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197321 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197321 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247125 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247125 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444446 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444446 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444446 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444446 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1545858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1545858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2729554035 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2729554035 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4275412035 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4275412035 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4275412035 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4275412035 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001491 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4769.249985 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002203 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002203 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002203 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002203 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7834.229504 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7834.229504 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11045.236358 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11045.236358 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9619.643410 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 819 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 444446 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 445265 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 819 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 444446 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 445265 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.923077 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027874 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.031574 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089738 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089738 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.923077 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.062273 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063856 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.923077 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.062273 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063856 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35803.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35271.454545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35335.757673 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39649.108761 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39649.108761 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35803.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38779.177115 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38700.059262 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35803.571429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38779.177115 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38700.059262 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 5679785 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 322 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 478 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6312.111801 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11882.395397 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 3176 # number of writebacks -system.cpu.l2cache.writebacks::total 3176 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 748 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 3183 # number of writebacks +system.cpu.l2cache.writebacks::total 3183 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 753 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5490 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 6238 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22170 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 22170 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 748 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 27660 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 28408 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 748 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 27660 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 28408 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23297500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 171301000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 194598500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 698565000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 698565000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23297500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 869866000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 893163500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23297500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 869866000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 893163500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.908870 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027802 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031459 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089712 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089712 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.908870 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062215 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063779 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.908870 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062215 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063779 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31146.390374 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.367942 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.655659 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31509.472260 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31509.472260 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31146.390374 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448.517715 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31440.562518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31146.390374 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448.517715 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31440.562518 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 6243 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22177 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 22177 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 27667 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 28420 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 753 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 27667 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 28420 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24642000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 175481000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200123000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 812123285 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 812123285 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24642000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 987604285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1012246285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24642000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 987604285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1012246285 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919414 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027823 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031509 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089738 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089738 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919414 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062251 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063827 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919414 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062251 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063827 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32725.099602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31963.752277 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32055.582252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36620.069667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36620.069667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32725.099602 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35696.110348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35617.392153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32725.099602 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35696.110348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35617.392153 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 02db72141..a10276e4b 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index b63306c7d..149dba9b1 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:38:23 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:28:47 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 794147534000 because target called exit() +Exiting @ tick 795270546000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 759b7639a..79ebe936b 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.794148 # Number of seconds simulated -sim_ticks 794147534000 # Number of ticks simulated -final_tick 794147534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.795271 # Number of seconds simulated +sim_ticks 795270546000 # Number of ticks simulated +final_tick 795270546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1549107 # Simulator instruction rate (inst/s) -host_op_rate 1635914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2163825213 # Simulator tick rate (ticks/s) -host_mem_usage 232760 # Number of bytes of host memory used -host_seconds 367.01 # Real time elapsed on the host +host_inst_rate 873454 # Simulator instruction rate (inst/s) +host_op_rate 922399 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1221783566 # Simulator tick rate (ticks/s) +host_mem_usage 232680 # Number of bytes of host memory used +host_seconds 650.91 # Real time elapsed on the host sim_insts 568539335 # Number of instructions simulated sim_ops 600398272 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 27110 # Nu system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2184783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2234023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 245234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 245234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 245234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2184783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2479257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 49171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2181698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2230868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49171 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49171 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 244888 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 244888 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 244888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2181698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2475756 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1588295068 # number of cpu cycles simulated +system.cpu.numCycles 1590541092 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 568539335 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 219173606 # nu system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1588295068 # Number of busy cycles +system.cpu.num_busy_cycles 1590541092 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 577.753136 # Cycle average of tags in use +system.cpu.icache.tagsinuse 577.715333 # Cycle average of tags in use system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 577.753136 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.282106 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.282106 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 577.715333 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.282088 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.282088 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 643 # n system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses system.cpu.icache.overall_misses::total 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34664000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34664000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34664000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34664000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34792000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34792000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34792000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34792000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34792000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34792000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53909.797823 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53909.797823 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53909.797823 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53909.797823 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54108.864697 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54108.864697 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54108.864697 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54108.864697 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643 system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32863000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32863000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32863000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32863000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32863000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32863000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51108.864697 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51108.864697 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements -system.cpu.dcache.tagsinuse 4094.217417 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.191707 # Cycle average of tags in use system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 536853000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.217417 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999565 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999565 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 547974000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.191707 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999559 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999559 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses system.cpu.dcache.overall_misses::total 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2865114000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2865114000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4399402000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4399402000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7264516000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7264516000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7264516000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7264516000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2866972000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2866972000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4400884000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4400884000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7267856000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7267856000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7267856000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7267856000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15094.164875 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15094.164875 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17757.568174 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17757.568174 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16602.179338 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16602.179338 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.953302 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.953302 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17763.550059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17763.550059 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16609.812507 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16609.812507 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564 system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295666000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295666000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5951824000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5951824000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5951824000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5951824000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2297524000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2297524000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3657640000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3657640000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5955164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5955164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5955164000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5955164000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12094.164875 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12094.164875 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.953302 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.953302 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14763.550059 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14763.550059 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 3963 # number of replacements -system.cpu.l2cache.tagsinuse 21581.956920 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 21579.150724 # Cycle average of tags in use system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20942.700989 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 130.076740 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 509.179191 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.639121 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 20939.895204 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 130.071130 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 509.184390 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.639035 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.003969 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015539 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.658629 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.658543 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 3fe84dba1..647cf0cf8 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 476c2fbae..196024f42 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:06:58 -gem5 started Jun 28 2012 22:54:22 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:32:18 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 387353399000 because target called exit() +Exiting @ tick 389181871500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index aefb16cc5..09d53c6a6 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,173 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387353 # Number of seconds simulated -sim_ticks 387353399000 # Number of ticks simulated -final_tick 387353399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.389182 # Number of seconds simulated +sim_ticks 389181871500 # Number of ticks simulated +final_tick 389181871500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 249730 # Simulator instruction rate (inst/s) -host_op_rate 250517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69036992 # Simulator tick rate (ticks/s) -host_mem_usage 223172 # Number of bytes of host memory used -host_seconds 5610.81 # Real time elapsed on the host +host_inst_rate 233275 # Simulator instruction rate (inst/s) +host_op_rate 234010 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64792479 # Simulator tick rate (ticks/s) +host_mem_usage 223132 # Number of bytes of host memory used +host_seconds 6006.59 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1679296 # Number of bytes read from this memory -system.physmem.bytes_read::total 1758080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 78784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 78784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163648 # Number of bytes written to this memory -system.physmem.bytes_written::total 163648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26239 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27470 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2557 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2557 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 203390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4335307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4538698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 203390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 203390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 422477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 422477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 422477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 203390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4335307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4961175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 78592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1679360 # Number of bytes read from this memory +system.physmem.bytes_read::total 1757952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 78592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 78592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163456 # Number of bytes written to this memory +system.physmem.bytes_written::total 163456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1228 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26240 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27468 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 201942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4315103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4517045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201942 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201942 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 419999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 419999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 419999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4315103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4937044 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774706799 # number of cpu cycles simulated +system.cpu.numCycles 778363744 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98185703 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88410338 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3780922 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66067142 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65660680 # Number of BTB hits +system.cpu.BPredUnit.lookups 98202538 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88418167 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3786555 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66007710 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65666961 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1350 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 222 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165873006 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648740209 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98185703 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65662030 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330401804 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21677633 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 260655576 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 134 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2710 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162813671 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754240 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774625436 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.134374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.150186 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1332 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165889798 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648919647 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98202538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65668293 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330430884 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21692843 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 264292230 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2686 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162826473 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 754831 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 778319405 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.124393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146166 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 444223632 57.35% 57.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74371089 9.60% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37975725 4.90% 71.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9081691 1.17% 73.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28157593 3.63% 76.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18825345 2.43% 79.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11518334 1.49% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3870567 0.50% 81.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146601460 18.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 447888521 57.55% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74380250 9.56% 67.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37976870 4.88% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9085355 1.17% 73.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28165073 3.62% 76.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18828553 2.42% 79.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11512004 1.48% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3871007 0.50% 81.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146611772 18.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774625436 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126739 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.128212 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217582243 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 211191171 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285367331 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42792485 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17692206 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642537043 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17692206 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241610870 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34893000 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51906533 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303032306 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 125490521 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631238728 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 30863889 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 72608286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3100712 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360952696 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755863339 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2721765470 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34097869 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 778319405 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126165 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.118444 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217790097 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214638982 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285156910 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 43029734 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17703682 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642636299 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17703682 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241734353 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36955708 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 51946820 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303044657 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126934185 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631312586 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 31546408 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73332264 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3116970 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360939473 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755912805 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2722068159 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33844646 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116182244 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2679261 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2694678 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271420357 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438695813 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180248477 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255317958 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83005231 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517026367 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2634412 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460842230 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78451 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113716292 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136734652 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 390741 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774625436 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.885869 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.429732 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116169021 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2679381 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2694981 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 272918574 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438732735 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180262547 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255381650 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82499363 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517064379 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2634738 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460855259 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54931 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113760463 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136767182 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 391067 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 778319405 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.876935 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.427664 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145113160 18.73% 18.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184290714 23.79% 42.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210981910 27.24% 69.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131056815 16.92% 86.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70797961 9.14% 95.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20401058 2.63% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7831654 1.01% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3987119 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 165045 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147026932 18.89% 18.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 186493885 23.96% 42.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 211074443 27.12% 69.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 130841076 16.81% 86.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70678954 9.08% 95.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20414805 2.62% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7717737 0.99% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3979587 0.51% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 91986 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774625436 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 778319405 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 85311 4.91% 4.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 160602 9.25% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1164457 67.05% 81.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326416 18.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 100522 6.26% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 166576 10.38% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1142590 71.19% 87.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 195193 12.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867158495 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867158324 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2649765 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2642655 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -193,86 +193,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419768740 28.73% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171265230 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419786972 28.74% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171267308 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460842230 # Type of FU issued -system.cpu.iq.rate 1.885671 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1736786 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001189 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3680238914 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624378157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444420049 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17886219 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9235235 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8548145 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453389871 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9189145 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215326368 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460855259 # Type of FU issued +system.cpu.iq.rate 1.876829 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1604881 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001099 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3684016874 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624580550 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444446185 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17672861 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9115596 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8537125 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453449423 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9010717 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215321766 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36182969 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54134 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 244807 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13400335 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36219891 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54743 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 244893 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13414405 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3669 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 64278 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3575 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 58855 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17692206 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 786779 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 100697 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613841065 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4120499 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438695813 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180248477 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2548675 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 22528 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11302 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 244807 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2356307 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1558704 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3915011 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455294659 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417049506 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5547571 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17703682 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1537187 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 135114 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613898993 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4122313 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438732735 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180262547 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2549072 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 88195 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3279 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 244893 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2354936 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1566356 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3921292 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455308115 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417068435 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5547144 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94180286 # number of nop insts executed -system.cpu.iew.exec_refs 587622925 # number of memory reference insts executed -system.cpu.iew.exec_branches 89107301 # Number of branches executed -system.cpu.iew.exec_stores 170573419 # Number of stores executed -system.cpu.iew.exec_rate 1.878510 # Inst execution rate -system.cpu.iew.wb_sent 1453892295 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452968194 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154379658 # num instructions producing a value -system.cpu.iew.wb_consumers 1205415324 # num instructions consuming a value +system.cpu.iew.exec_nop 94199876 # number of nop insts executed +system.cpu.iew.exec_refs 587640720 # number of memory reference insts executed +system.cpu.iew.exec_branches 89112594 # Number of branches executed +system.cpu.iew.exec_stores 170572285 # Number of stores executed +system.cpu.iew.exec_rate 1.869702 # Inst execution rate +system.cpu.iew.wb_sent 1453906115 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452983310 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154403216 # num instructions producing a value +system.cpu.iew.wb_consumers 1205257004 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.875507 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957661 # average fanout of values written-back +system.cpu.iew.wb_rate 1.866715 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957807 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 124212585 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124289069 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3780922 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 756933841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.967838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.506392 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3786555 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 760616334 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.958311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.503558 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 238474723 31.51% 31.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276385043 36.51% 68.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43107077 5.69% 73.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54927770 7.26% 80.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19677668 2.60% 83.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13341628 1.76% 85.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30470034 4.03% 89.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10497412 1.39% 90.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70052486 9.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 241729742 31.78% 31.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276918822 36.41% 68.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43178321 5.68% 73.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54835847 7.21% 81.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19622698 2.58% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13346857 1.75% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30466514 4.01% 89.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10424135 1.37% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70093398 9.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 756933841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 760616334 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108101 # Number of instructions committed system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -283,70 +283,70 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70052486 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70093398 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2300552365 # The number of ROB reads -system.cpu.rob.rob_writes 3245186964 # The number of ROB writes -system.cpu.timesIdled 3424 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 81363 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2304270430 # The number of ROB reads +system.cpu.rob.rob_writes 3245352893 # The number of ROB writes +system.cpu.timesIdled 1469 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44339 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188958 # Number of Instructions Simulated system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated -system.cpu.cpi 0.552892 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552892 # CPI: Total CPI of All Threads -system.cpu.ipc 1.808670 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.808670 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980590719 # number of integer regfile reads -system.cpu.int_regfile_writes 1276263729 # number of integer regfile writes -system.cpu.fp_regfile_reads 16980710 # number of floating regfile reads -system.cpu.fp_regfile_writes 10502370 # number of floating regfile writes -system.cpu.misc_regfile_reads 593296241 # number of misc regfile reads +system.cpu.cpi 0.555502 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.555502 # CPI: Total CPI of All Threads +system.cpu.ipc 1.800172 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.800172 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980619061 # number of integer regfile reads +system.cpu.int_regfile_writes 1276279795 # number of integer regfile writes +system.cpu.fp_regfile_reads 16952700 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491726 # number of floating regfile writes +system.cpu.misc_regfile_reads 593312421 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 213 # number of replacements -system.cpu.icache.tagsinuse 1045.821443 # Cycle average of tags in use -system.cpu.icache.total_refs 162811755 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1361 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119626.565026 # Average number of references to valid blocks. +system.cpu.icache.replacements 216 # number of replacements +system.cpu.icache.tagsinuse 1046.067933 # Cycle average of tags in use +system.cpu.icache.total_refs 162824561 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1364 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119372.845308 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1045.821443 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.510655 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.510655 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162811755 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162811755 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162811755 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162811755 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162811755 # number of overall hits -system.cpu.icache.overall_hits::total 162811755 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1916 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1916 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1916 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1916 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1916 # number of overall misses -system.cpu.icache.overall_misses::total 1916 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62211500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62211500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62211500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62211500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62211500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62211500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162813671 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162813671 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162813671 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162813671 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162813671 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162813671 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1046.067933 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.510775 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.510775 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162824561 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162824561 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162824561 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162824561 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162824561 # number of overall hits +system.cpu.icache.overall_hits::total 162824561 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1912 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1912 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1912 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1912 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1912 # number of overall misses +system.cpu.icache.overall_misses::total 1912 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62993000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62993000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62993000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62993000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62993000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62993000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162826473 # 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Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.115270 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200904892 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200904892 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164979300 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164979300 # number of WriteReq hits +system.cpu.dcache.replacements 458041 # number of replacements +system.cpu.dcache.tagsinuse 4094.912001 # Cycle average of tags in use +system.cpu.dcache.total_refs 365776449 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 462137 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.489210 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 160490000 # 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miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368547239 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368547239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368547239 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368547239 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004464 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004464 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011218 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011218 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007149 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007149 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.899634 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.056780 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059269 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.903818 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.059262 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.899634 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.056780 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059269 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34233.956133 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34035.143050 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34078.306878 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34344.816514 # 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average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.042609 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.042609 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34792.752443 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.260671 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37769.932285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34792.752443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.260671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37769.932285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -605,52 +605,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2557 # number of writebacks -system.cpu.l2cache.writebacks::total 2557 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1231 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4439 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5670 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21800 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21800 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1231 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26239 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27470 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1231 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26239 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27470 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38155500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 137662500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175818000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 681082000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 681082000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38155500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 818744500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 856900000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38155500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 818744500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 856900000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022188 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028149 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083190 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083190 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for demand accesses +system.cpu.l2cache.writebacks::writebacks 2554 # number of writebacks +system.cpu.l2cache.writebacks::total 2554 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1228 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4437 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5665 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21803 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21803 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26240 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1228 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26240 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27468 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38798500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 138491500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 177290000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 776754500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 776754500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38798500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 915246000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 954044500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38798500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 915246000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 954044500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022175 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028121 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083201 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083201 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899634 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059269 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059262 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059269 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30995.532088 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31012.052264 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31008.465608 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31242.293578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31242.293578 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30995.532088 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31203.342353 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31194.029851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30995.532088 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31203.342353 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31194.029851 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059262 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31594.869707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31212.869056 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31295.675199 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35626.037701 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35626.037701 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31594.869707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34879.801829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34732.943789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31594.869707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34879.801829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34732.943789 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index e273f1b51..ed5d7509c 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index a6ed8a59a..7b12cccb1 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:06:58 -gem5 started Jun 28 2012 22:54:27 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 12:13:11 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2061521023000 because target called exit() +Exiting @ tick 2063177751000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 921624c02..607412a81 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.061521 # Number of seconds simulated -sim_ticks 2061521023000 # Number of ticks simulated -final_tick 2061521023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.063178 # Number of seconds simulated +sim_ticks 2063177751000 # Number of ticks simulated +final_tick 2063177751000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2065708 # Simulator instruction rate (inst/s) -host_op_rate 2071849 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2867468443 # Simulator tick rate (ticks/s) -host_mem_usage 221124 # Number of bytes of host memory used -host_seconds 718.93 # Real time elapsed on the host +host_inst_rate 1349558 # Simulator instruction rate (inst/s) +host_op_rate 1353570 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1874864984 # Simulator tick rate (ticks/s) +host_mem_usage 222108 # Number of bytes of host memory used +host_seconds 1100.44 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26134 # Nu system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 31883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 811331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 843214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 31883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 31883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78327 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78327 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 31883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 811331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 921541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 31858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 810680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 842537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 31858 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 31858 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 31858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 810680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 920801 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4123042046 # number of cpu cycles simulated +system.cpu.numCycles 4126355502 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1485108101 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 569365767 # nu system.cpu.num_load_insts 402515346 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4123042046 # Number of busy cycles +system.cpu.num_busy_cycles 4126355502 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.456939 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.409372 # Cycle average of tags in use system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.456939 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.442606 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.442606 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 906.409372 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.442583 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.442583 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses system.cpu.icache.overall_misses::total 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58632000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58632000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58632000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58632000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58632000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58632000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58777000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58777000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58777000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58777000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58777000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58777000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52964.769648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52964.769648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52964.769648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52964.769648 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53095.754291 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53095.754291 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53095.754291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53095.754291 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107 system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55311000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 55311000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55311000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 55311000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55311000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 55311000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55456000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 55456000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55456000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 55456000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55456000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 55456000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49964.769648 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49964.769648 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50095.754291 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50095.754291 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.226004 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.205153 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 566952000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.226004 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 588945000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.205153 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 453214 # n system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses system.cpu.dcache.overall_misses::total 453214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888312000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2888312000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554270000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4554270000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888728000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2888728000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554574000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4554574000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7442582000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7442582000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7442582000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7442582000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7443302000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7443302000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7443302000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7443302000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14927.757047 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14927.757047 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17534.767141 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17534.767141 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14929.907073 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14929.907073 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17535.937596 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17535.937596 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16421.783087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16421.783087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16423.371741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16423.371741 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 453214 system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2308270000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2308270000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775390000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775390000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6083660000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6083660000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6083660000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6083660000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses @@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11929.907073 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11929.907073 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14535.937596 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14535.937596 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2614 # number of replacements -system.cpu.l2cache.tagsinuse 22186.870278 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22185.384662 # Cycle average of tags in use system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20830.127393 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 857.488075 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 499.254810 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.635685 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.026168 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015236 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.677090 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 20828.536366 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 857.441703 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 499.406594 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635636 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.026167 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.677044 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 994a9cc44..9d85601cf 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -532,7 +532,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 486e549a7..e9fade7f1 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 28 2012 23:06:37 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 12:44:41 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -24,6 +24,7 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 +info: Increasing stack size by one page. Compressed data 83382 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -39,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 636762784500 because target called exit() +Exiting @ tick 636963896500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 608862386..5a09d9960 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.636763 # Number of seconds simulated -sim_ticks 636762784500 # Number of ticks simulated -final_tick 636762784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.636964 # Number of seconds simulated +sim_ticks 636963896500 # Number of ticks simulated +final_tick 636963896500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102830 # Simulator instruction rate (inst/s) -host_op_rate 189469 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74404788 # Simulator tick rate (ticks/s) -host_mem_usage 230588 # Number of bytes of host memory used -host_seconds 8558.09 # Real time elapsed on the host +host_inst_rate 94339 # Simulator instruction rate (inst/s) +host_op_rate 173825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68282764 # Simulator tick rate (ticks/s) +host_mem_usage 230548 # Number of bytes of host memory used +host_seconds 9328.33 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1694912 # Number of bytes read from this memory -system.physmem.bytes_read::total 1753728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162944 # Number of bytes written to this memory -system.physmem.bytes_written::total 162944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 919 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26483 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27402 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2546 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2546 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2661764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2754131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 255894 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 255894 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 255894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2661764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3010025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 59072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1694720 # Number of bytes read from this memory +system.physmem.bytes_read::total 1753792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 59072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 59072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162752 # Number of bytes written to this memory +system.physmem.bytes_written::total 162752 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26480 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27403 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2543 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2543 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2660622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2753362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92740 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92740 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 255512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 255512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 255512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2660622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3008874 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1273525570 # number of cpu cycles simulated +system.cpu.numCycles 1273927794 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 155344135 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 155344135 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26655607 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77245204 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 76889704 # Number of BTB hits +system.cpu.BPredUnit.lookups 155476696 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 155476696 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26665974 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 76215157 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 75849392 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180802236 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1488442027 # Number of instructions fetch has processed -system.cpu.fetch.Branches 155344135 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 76889704 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 402274046 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 93385401 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 623851243 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1029 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 186094276 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8755292 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1273499648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.998943 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.233820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180766435 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1491872316 # Number of instructions fetch has processed +system.cpu.fetch.Branches 155476696 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 75849392 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 402325403 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 93614087 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 624018674 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1031 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 185889439 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8548075 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1273900868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.002953 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.238276 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 878442365 68.98% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24602632 1.93% 70.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15260428 1.20% 72.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18256548 1.43% 73.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26724815 2.10% 75.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18280477 1.44% 77.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29063774 2.28% 79.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39873032 3.13% 82.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 222995577 17.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 878792706 68.98% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24409433 1.92% 70.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14960209 1.17% 72.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18025508 1.41% 73.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26731742 2.10% 75.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18277101 1.43% 77.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28493019 2.24% 79.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39802935 3.12% 82.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 224408215 17.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1273499648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121980 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.168757 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 300474409 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 536583689 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 281514067 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88356524 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66570959 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2368586772 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 66570959 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 352813558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 123796819 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1672 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302654861 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 427661779 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2273830132 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 293323791 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 102919235 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 68 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3464511326 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7120107939 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7120100187 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1273900868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122045 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.171081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 300130332 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 537055352 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 281851498 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88074501 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 66789185 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2370363864 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 66789185 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 352614235 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124117956 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1807 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302560946 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 427816739 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2274265358 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 293377579 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 103041568 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 112 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3464406080 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7122244281 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 7122237233 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7048 # Number of floating rename lookups system.cpu.rename.CommittedMaps 2493860970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 970650356 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 98 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 745542263 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 545308074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222233244 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 351719357 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 147016761 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2026127683 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 554 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1785922004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 133826 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 404499601 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1046828617 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1273499648 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.402373 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.312278 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 970545110 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 88 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 88 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 745535849 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 545979333 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222242756 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 352158228 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 146951837 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2027253751 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1785885865 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 143298 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 405620982 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1049961378 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 506 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1273900868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.401903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.311945 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 346409167 27.20% 27.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 447658448 35.15% 62.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 243252093 19.10% 81.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151077765 11.86% 93.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 40789672 3.20% 96.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 32618177 2.56% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9933898 0.78% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1410310 0.11% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 350118 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 346798223 27.22% 27.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 447596849 35.14% 62.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 243149127 19.09% 81.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151409869 11.89% 93.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 40759247 3.20% 96.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32504128 2.55% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9931846 0.78% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1400181 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 351398 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1273499648 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1273900868 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 252918 9.83% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2142956 83.30% 93.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 176798 6.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 262837 10.20% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2136217 82.89% 93.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 178017 6.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46813783 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1067070411 59.75% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812745 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1067077874 59.75% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued @@ -194,86 +194,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479563179 26.85% 89.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192474631 10.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479524386 26.85% 89.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192470860 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1785922004 # Type of FU issued -system.cpu.iq.rate 1.402345 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2572672 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001441 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4848049464 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2430808619 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1727155501 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 690 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2256 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1741680668 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 208913373 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1785885865 # Type of FU issued +system.cpu.iq.rate 1.401874 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2577071 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001443 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4848392282 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2433055974 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1727031567 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 685 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2066 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1741649976 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 215 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 208887212 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 126265949 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36209 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 190191 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 34047187 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 126937208 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36775 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189921 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 34056699 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1764 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2072 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 462 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66570959 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 346337 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 84829 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2026128237 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63751416 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 545308074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222233244 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49329 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 412 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 190191 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2137841 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24642910 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26780751 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1767814472 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 473818516 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18107532 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 66789185 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 397482 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 85620 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2027254307 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63893728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 545979333 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222242756 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48032 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 669 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189921 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2137684 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24653436 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26791120 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1767797184 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 473889834 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18088681 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665662363 # number of memory reference insts executed -system.cpu.iew.exec_branches 109724389 # Number of branches executed -system.cpu.iew.exec_stores 191843847 # Number of stores executed -system.cpu.iew.exec_rate 1.388126 # Inst execution rate -system.cpu.iew.wb_sent 1728501294 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1727155577 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1262384078 # num instructions producing a value -system.cpu.iew.wb_consumers 2985492726 # num instructions consuming a value +system.cpu.iew.exec_refs 665730625 # number of memory reference insts executed +system.cpu.iew.exec_branches 109718993 # Number of branches executed +system.cpu.iew.exec_stores 191840791 # Number of stores executed +system.cpu.iew.exec_rate 1.387675 # Inst execution rate +system.cpu.iew.wb_sent 1728379028 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1727031635 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1262282896 # num instructions producing a value +system.cpu.iew.wb_consumers 2985352291 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.356200 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.422839 # average fanout of values written-back +system.cpu.iew.wb_rate 1.355675 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.422825 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 404636626 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 405765098 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26655738 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1206928689 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.343488 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.659364 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26666115 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1207111683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.343284 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.660206 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 436768152 36.19% 36.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 432905754 35.87% 72.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 93527824 7.75% 79.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 134952786 11.18% 90.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35694459 2.96% 93.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23721563 1.97% 95.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 25354378 2.10% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8867881 0.73% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15135892 1.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 437166011 36.22% 36.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 432802967 35.85% 72.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93484629 7.74% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 134841213 11.17% 90.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35727207 2.96% 93.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23483214 1.95% 95.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25551681 2.12% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8874954 0.74% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15179807 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1206928689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1207111683 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025312 # Number of instructions committed system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,68 +284,68 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15135892 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15179807 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3217923405 # The number of ROB reads -system.cpu.rob.rob_writes 4118849074 # The number of ROB writes -system.cpu.timesIdled 528 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25922 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3219190956 # The number of ROB reads +system.cpu.rob.rob_writes 4121324121 # The number of ROB writes +system.cpu.timesIdled 604 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26926 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025312 # Number of Instructions Simulated system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated -system.cpu.cpi 1.447147 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.447147 # CPI: Total CPI of All Threads -system.cpu.ipc 0.691015 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.691015 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4473867691 # number of integer regfile reads -system.cpu.int_regfile_writes 2590130278 # number of integer regfile writes -system.cpu.fp_regfile_reads 76 # number of floating regfile reads -system.cpu.misc_regfile_reads 911455321 # number of misc regfile reads -system.cpu.icache.replacements 19 # number of replacements -system.cpu.icache.tagsinuse 827.665584 # Cycle average of tags in use -system.cpu.icache.total_refs 186092930 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 926 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 200964.287257 # Average number of references to valid blocks. +system.cpu.cpi 1.447604 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.447604 # CPI: Total CPI of All Threads +system.cpu.ipc 0.690797 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.690797 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4473882728 # number of integer regfile reads +system.cpu.int_regfile_writes 2589957068 # number of integer regfile writes +system.cpu.fp_regfile_reads 68 # number of floating regfile reads +system.cpu.misc_regfile_reads 911502074 # number of misc regfile reads +system.cpu.icache.replacements 17 # number of replacements +system.cpu.icache.tagsinuse 828.056964 # Cycle average of tags in use +system.cpu.icache.total_refs 185888078 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 930 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 199879.653763 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 827.665584 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.404134 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.404134 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 186092930 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 186092930 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 186092930 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 186092930 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 186092930 # number of overall hits -system.cpu.icache.overall_hits::total 186092930 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1346 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1346 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1346 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1346 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1346 # number of overall misses -system.cpu.icache.overall_misses::total 1346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45797000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45797000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45797000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45797000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45797000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45797000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 186094276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 186094276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 186094276 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 186094276 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 186094276 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 186094276 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 828.056964 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404325 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404325 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 185888078 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 185888078 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 185888078 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 185888078 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 185888078 # number of overall hits +system.cpu.icache.overall_hits::total 185888078 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1361 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1361 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1361 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1361 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1361 # number of overall misses +system.cpu.icache.overall_misses::total 1361 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47861000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47861000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47861000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47861000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47861000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47861000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 185889439 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 185889439 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 185889439 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 185889439 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 185889439 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 185889439 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.517088 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34024.517088 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.517088 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34024.517088 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.517088 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34024.517088 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35166.054372 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35166.054372 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35166.054372 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35166.054372 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35166.054372 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35166.054372 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 420 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 420 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 420 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 420 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 420 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 926 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 926 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 926 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 926 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 926 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 926 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32563500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32563500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32563500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32563500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32563500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32563500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 431 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 431 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 431 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 431 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 431 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34220000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34220000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35165.766739 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35165.766739 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35165.766739 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35165.766739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35165.766739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35165.766739 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36795.698925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36795.698925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36795.698925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36795.698925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36795.698925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36795.698925 # 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number of replacements +system.cpu.dcache.tagsinuse 4093.428364 # Cycle average of tags in use +system.cpu.dcache.total_refs 452731874 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 449529 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1007.124955 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 738592000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.428364 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999372 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264792027 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264792027 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939847 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939847 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452731874 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2040839000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2040839000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 3341461500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 3341461500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 3341461500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 3341461500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264998696 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264998696 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 453088036 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 453088036 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 453088036 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 453088036 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000779 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000779 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 453184753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 453184753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 453184753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 453184753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000999 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000999 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000999 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000999 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5997.299811 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 5997.299811 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8181.910862 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8181.910862 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7185.489429 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7185.489429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7185.489429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7185.489429 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6293.263624 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6293.263624 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8289.017505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8289.017505 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7378.265497 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7378.265497 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7378.265497 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7378.265497 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,132 +450,132 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428484 # number of writebacks -system.cpu.dcache.writebacks::total 428484 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3123 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3138 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3138 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3138 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3138 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203344 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203344 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246188 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246188 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449532 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449532 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 449532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 449532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 611389500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 611389500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1275715500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1275715500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1887105000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1887105000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1887105000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1887105000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000768 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000768 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 428496 # number of writebacks +system.cpu.dcache.writebacks::total 428496 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3328 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3328 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 20 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 20 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3348 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3348 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3348 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3348 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203341 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203341 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246190 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246190 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449531 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449531 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 449531 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 449531 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 607771500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 607771500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1249776500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1249776500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1857548000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1857548000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1857548000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1857548000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3006.675879 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3006.675879 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5181.875234 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5181.875234 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4197.932516 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4197.932516 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4197.932516 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4197.932516 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2988.927467 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2988.927467 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5076.471425 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29745000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 821672000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 851417000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992473 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022417 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026834 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089041 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089041 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992473 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060833 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992473 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058906 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060833 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32226.435536 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31107.612988 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31296.022624 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.753307 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.753307 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32226.435536 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.909366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31070.211291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32226.435536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.909366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31070.211291 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 3c1333558..2eec436ef 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -169,7 +169,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -201,7 +201,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 9e79ba165..d6878297d 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 28 2012 23:10:36 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 13:03:08 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1800635309000 because target called exit() +Exiting @ tick 1801979727000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index a3d141ce0..79bdadab4 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.800635 # Number of seconds simulated -sim_ticks 1800635309000 # Number of ticks simulated -final_tick 1800635309000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.801980 # Number of seconds simulated +sim_ticks 1801979727000 # Number of ticks simulated +final_tick 1801979727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 904173 # Simulator instruction rate (inst/s) -host_op_rate 1665987 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1850044030 # Simulator tick rate (ticks/s) -host_mem_usage 228536 # Number of bytes of host memory used -host_seconds 973.29 # Real time elapsed on the host +host_inst_rate 622629 # Simulator instruction rate (inst/s) +host_op_rate 1147227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1274922997 # Simulator tick rate (ticks/s) +host_mem_usage 228496 # Number of bytes of host memory used +host_seconds 1413.40 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26287 # Nu system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 934319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 959981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 89213 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 89213 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 89213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 934319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1049194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 25643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 933622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 959265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25643 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25643 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 89146 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 89146 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 89146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 933622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1048411 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3601270618 # number of cpu cycles simulated +system.cpu.numCycles 3603959454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025313 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 607228182 # nu system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3601270618 # Number of busy cycles +system.cpu.num_busy_cycles 3603959454 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.189072 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.169533 # Cycle average of tags in use system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.189072 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.322358 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.322358 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 660.169533 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.322348 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.322348 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 722 # n system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses system.cpu.icache.overall_misses::total 722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40432000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40432000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40432000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40432000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40432000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40432000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40521000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40521000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40521000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40521000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40521000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40521000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56123.268698 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56123.268698 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56123.268698 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56123.268698 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 722 system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38355000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38355000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38355000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38355000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38355000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38355000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53123.268698 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53123.268698 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.895332 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.884021 # Cycle average of tags in use system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.895332 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999730 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999730 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 788858000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.884021 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999728 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999728 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 442048 # n system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses system.cpu.dcache.overall_misses::total 442048 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2943878000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2943878000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4348848000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4348848000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7292726000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7292726000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7292726000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7292726000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2948308000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2948308000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4362877000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4362877000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7311185000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7311185000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7311185000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7311185000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14918.855093 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14918.855093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17770.564150 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17770.564150 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16497.588497 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16497.588497 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.305251 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.305251 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17827.890423 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17827.890423 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16539.346406 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16539.346406 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 442048 system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3614682000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3614682000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5966582000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5966582000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5966582000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5966582000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2356330000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2356330000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3628711000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3628711000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5985041000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5985041000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5985041000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5985041000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14770.564150 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14770.564150 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11941.305251 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11941.305251 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14827.890423 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14827.890423 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2581 # number of replacements -system.cpu.l2cache.tagsinuse 22163.019096 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22161.849584 # Cycle average of tags in use system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21019.596332 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 596.850673 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 546.572092 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641467 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21018.400125 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 596.832039 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 546.617420 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641431 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016680 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.676362 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016681 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.676326 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits |