summaryrefslogtreecommitdiff
path: root/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
diff options
context:
space:
mode:
authorSteve Reinhardt <stever@gmail.com>2015-03-19 08:41:32 -0400
committerSteve Reinhardt <stever@gmail.com>2015-03-19 08:41:32 -0400
commit1483496803f8a8618f62adc5439ce435359b36fe (patch)
treea6134ff85d7e6e07e6d34293513f91b16ff94515 /tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
parentf1c3fda965dd4b28ab6b2e99f5f3210fa2089a17 (diff)
downloadgem5-1483496803f8a8618f62adc5439ce435359b36fe.tar.xz
stats: update Minor stats due to PF bug fix
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5) inadvertently fixed a bug in the Minor CPU model which caused it to treat software prefetches as regular loads. Prior to this changeset, Minor did an ad-hoc generation of memory commands that left out the PF check; because it now uses the common code that the other CPU models use, it generates prefetches properly. These stat changes reflect the fact that the Minor model now issues SoftPFReqs.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout')
-rwxr-xr-x[-rw-r--r--]tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout14
1 files changed, 6 insertions, 8 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
index aed824289..be80117c3 100644..100755
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 16:03:40
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x11aa5150
+ 0: system.cpu.isa: ISA system set to: 0 0x45a0240
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
@@ -26,4 +24,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 61276704500 because target called exit()
+Exiting @ tick 61589191500 because target called exit()