diff options
| author | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
| commit | 1483496803f8a8618f62adc5439ce435359b36fe (patch) | |
| tree | a6134ff85d7e6e07e6d34293513f91b16ff94515 /tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | |
| parent | f1c3fda965dd4b28ab6b2e99f5f3210fa2089a17 (diff) | |
| download | gem5-1483496803f8a8618f62adc5439ce435359b36fe.tar.xz | |
stats: update Minor stats due to PF bug fix
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads. Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly. These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 582 |
1 files changed, 299 insertions, 283 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 2c11d0b34..bce6e86b0 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061593 # Number of seconds simulated -sim_ticks 61592600500 # Number of ticks simulated -final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061589 # Number of seconds simulated +sim_ticks 61589191500 # Number of ticks simulated +final_tick 61589191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271325 # Simulator instruction rate (inst/s) -host_op_rate 272676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 184448880 # Simulator tick rate (ticks/s) -host_mem_usage 445184 # Number of bytes of host memory used -host_seconds 333.93 # Real time elapsed on the host +host_inst_rate 169101 # Simulator instruction rate (inst/s) +host_op_rate 169943 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 114949938 # Simulator tick rate (ticks/s) +host_mem_usage 374724 # Number of bytes of host memory used +host_seconds 535.79 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49600 # Nu system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 805336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15379322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16184658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15379322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16184658 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61592506000 # Total gap between requests +system.physmem.totGap 61589097000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation -system.physmem.totQLat 77242000 # Total ticks spent queuing -system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 642.728682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 437.613794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.141843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 250 16.15% 16.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 184 11.89% 28.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 91 5.88% 33.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 4.46% 38.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 77 4.97% 43.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 93 6.01% 49.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.78% 52.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.33% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1548 # Bytes accessed per row activation +system.physmem.totQLat 76265750 # Total ticks spent queuing +system.physmem.totMemAccLat 368297000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4896.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23646.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14018 # Number of row buffer hits during reads +system.physmem.readRowHits 14017 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3954575.02 # Average gap between requests +system.physmem.avgGap 3954356.15 # Average gap between requests system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 6365520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3473250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.572046 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states +system.physmem_0.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2552305815 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34710162000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41358171225 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.598278 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57736612750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2056340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1792195250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5322240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2904000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.509428 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states +system.physmem_1.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2572075980 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34692811500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41352777360 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.510839 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57709022500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2056340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1820633500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20789446 # Number of BP lookups -system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits +system.cpu.branchPred.lookups 20789992 # Number of BP lookups +system.cpu.branchPred.condPredicted 17092121 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765794 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8976081 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8866607 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.780381 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62695 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,89 +377,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 123185201 # number of cpu cycles simulated +system.cpu.numCycles 123178383 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602849 # Number of instructions committed system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2068275 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359617 # CPI: cycles per instruction -system.cpu.ipc 0.735501 # IPC: instructions per cycle -system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.359542 # CPI: cycles per instruction +system.cpu.ipc 0.735542 # IPC: instructions per cycle +system.cpu.tickCycles 109824698 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13353685 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946107 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3616.117477 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267654 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.644255 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.117477 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.882841 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.882841 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55463725 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463725 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21598560 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598560 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660812 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660812 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits -system.cpu.dcache.overall_hits::total 26259649 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 26259372 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259372 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26259880 # number of overall hits +system.cpu.dcache.overall_hits::total 26259880 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses -system.cpu.dcache.overall_misses::total 989105 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11918412494 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2568231500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2568231500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14486643994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14486643994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14486643994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14486643994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 74169 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74169 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 989103 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989103 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989107 # number of overall misses +system.cpu.dcache.overall_misses::total 989107 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918328994 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11918328994 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566867500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2566867500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14485196494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14485196494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14485196494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14485196494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22513494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513494 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248754 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248754 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27248754 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27248754 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27248475 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248475 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27248987 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27248987 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.527043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.527043 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34625.817368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34625.817368 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14646.214501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14646.214501 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.435780 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.435780 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34608.360636 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34608.360636 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.780669 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14644.780669 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.721445 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14644.721445 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -468,101 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks -system.cpu.dcache.writebacks::total 943286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11499 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11499 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27403 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27403 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38902 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38902 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38902 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38902 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses +system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks +system.cpu.dcache.writebacks::total 943285 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11501 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11501 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27402 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27402 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38903 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38903 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38903 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38903 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 950200 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950200 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413322256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413322256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877786756 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11877786756 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877786756 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11877786756 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413180006 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413180006 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1463830500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1463830500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877010506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11877010506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877166006 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11877166006 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.365766 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.365766 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31313.387359 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31313.387359 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.233828 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.233828 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31300.500353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31300.500353 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.484852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.484852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.609037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.609037 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.370829 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27857028 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.367878 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27855563 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34691.193026 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34689.368618 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.370829 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337095 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337095 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.367878 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337094 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337094 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55716465 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55716465 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27857028 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27857028 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27857028 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27857028 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27857028 # number of overall hits -system.cpu.icache.overall_hits::total 27857028 # number of overall hits +system.cpu.icache.tags.tag_accesses 55713535 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55713535 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27855563 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27855563 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27855563 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27855563 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27855563 # number of overall hits +system.cpu.icache.overall_hits::total 27855563 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.icache.overall_misses::total 803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61138997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61138997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61138997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61138997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61138997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61138997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27857831 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27857831 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27857831 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27857831 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27857831 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27857831 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60778747 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60778747 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60778747 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60778747 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60778747 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60778747 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27856366 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27856366 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27856366 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27856366 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27856366 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27856366 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76138.227895 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76138.227895 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76138.227895 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76138.227895 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75689.597758 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75689.597758 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75689.597758 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75689.597758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75689.597758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75689.597758 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803 system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59598503 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59598503 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59598503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59598503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59598503 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59598503 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59238753 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59238753 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59238753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59238753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59238753 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59238753 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74219.804483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74219.804483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73771.797011 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73771.797011 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73771.797011 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73771.797011 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73771.797011 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73771.797011 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10238.643668 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10238.331530 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9347.860585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.375683 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.407400 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285274 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9347.552494 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.372759 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.406276 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285265 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312459 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312449 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -616,15 +632,15 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 15216653 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15216653 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903198 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903174 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 943285 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 943285 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits @@ -642,24 +658,24 @@ system.cpu.l2cache.demand_misses::total 15584 # nu system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15584 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58533000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 80800750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073909000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1073909000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58533000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1096176750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1154709750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58533000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1096176750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1154709750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58173250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 80440250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073291000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1073291000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58173250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1095558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1153731250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58173250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1095558000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1153731250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 903436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 943285 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 943285 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses @@ -669,25 +685,25 @@ system.cpu.l2cache.overall_accesses::total 951006 # system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75235.218509 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84991.412214 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77693.028846 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73838.627613 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73838.627613 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74095.851514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74095.851514 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74772.814910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84988.549618 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77346.394231 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73796.135864 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73796.135864 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74033.062757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74033.062757 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,70 +732,70 @@ system.cpu.l2cache.demand_mshr_misses::total 15575 system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48659000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18669250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 67328250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 892098500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 892098500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910767750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 959426750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910767750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 959426750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48299750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18668000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66967750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891481000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891481000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48299750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910149000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 958448750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48299750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910149000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 958448750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62785.806452 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72926.757812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65303.831232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61337.905666 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61337.905666 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62322.258065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72921.875000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64954.170708 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61295.448295 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61295.448295 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 943285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843691 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2845297 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121234624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1894291 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1894291 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1894291 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1890430500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1372247 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428681994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1031 # Transaction distribution system.membus.trans_dist::ReadResp 1031 # Transaction distribution @@ -800,7 +816,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15575 # Request fanout histogram -system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21630500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |