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author | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-22 20:22:29 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-22 20:22:29 -0700 |
commit | 0cf36d94095aedef3c51447243c5a3cc14dd5d56 (patch) | |
tree | c0ed9e35fbbc5512f7fedf2947d4ae2702214f8e /tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout | |
parent | a70a83155bfe4c3877894c29f9dea720beb40f9c (diff) | |
download | gem5-0cf36d94095aedef3c51447243c5a3cc14dd5d56.tar.xz |
stats: update for previous changeset
Very small differences in IQ-specific O3 stats.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout')
-rwxr-xr-x | tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index f37d93ec9..eaa0003ec 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:33:12 +gem5 compiled Apr 22 2015 10:58:25 +gem5 started Apr 22 2015 11:34:28 gem5 executing on phenom command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x666d940 + 0: system.cpu.isa: ISA system set to: 0 0x299b730 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -24,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 26894328500 because target called exit() +Exiting @ tick 58202727500 because target called exit() |