diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1118 |
1 files changed, 558 insertions, 560 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 1a08f1a5c..b0555a54b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.028506 # Number of seconds simulated -sim_ticks 28505597000 # Number of ticks simulated -final_tick 28505597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025432 # Number of seconds simulated +sim_ticks 25432499000 # Number of ticks simulated +final_tick 25432499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145688 # Simulator instruction rate (inst/s) -host_op_rate 146734 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45838175 # Simulator tick rate (ticks/s) -host_mem_usage 362080 # Number of bytes of host memory used -host_seconds 621.87 # Real time elapsed on the host -sim_insts 90599368 # Number of instructions simulated -sim_ops 91249921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 993216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 712 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15519 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1598563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33244278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34842842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1598563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1598563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1598563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33244278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 34842842 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 141358 # Simulator instruction rate (inst/s) +host_op_rate 142373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39681246 # Simulator tick rate (ticks/s) +host_mem_usage 367916 # Number of bytes of host memory used +host_seconds 640.92 # Real time elapsed on the host +sim_insts 90599358 # Number of instructions simulated +sim_ops 91249911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory +system.physmem.bytes_read::total 992960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1786690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37256268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39042958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1786690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1786690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1786690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37256268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 39042958 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,320 +70,318 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 57011195 # number of cpu cycles simulated +system.cpu.numCycles 50864999 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27014403 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22277078 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 889929 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11548760 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11430884 # Number of BTB hits +system.cpu.BPredUnit.lookups 26815832 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22064400 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 887268 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11482840 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11353380 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 73122 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 372 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14508892 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 129672886 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27014403 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11504006 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24367767 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4991272 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14021743 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 72941 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 493 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14339573 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128641990 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26815832 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11426321 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24202315 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4802086 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8372764 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14122126 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 347107 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 56945823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.293943 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.179113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14019260 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 376949 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 50826068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.549806 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252225 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 32616008 57.28% 57.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3437208 6.04% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033940 3.57% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1577922 2.77% 69.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1684600 2.96% 72.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3016320 5.30% 77.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1478308 2.60% 80.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1110359 1.95% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9991158 17.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 26661639 52.46% 52.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3429294 6.75% 59.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2034587 4.00% 63.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1568872 3.09% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1675049 3.30% 69.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2962794 5.83% 75.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1484032 2.92% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1105241 2.17% 80.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9904560 19.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 56945823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.473844 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.274516 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17727827 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11442534 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22314035 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1422886 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4038541 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4486849 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8989 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 127753929 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42812 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4038541 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19463622 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5507295 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 178125 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21532560 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6225680 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124585344 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 540744 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4833961 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11275 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145162652 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 542774349 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 542766580 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37733154 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6541 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6539 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14204519 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29836795 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5560829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2097523 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1243222 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119152184 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10385 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105702713 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79311 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27697349 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68611569 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 56945823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.856198 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.856170 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 50826068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.527196 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.529087 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16897392 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6458273 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22716084 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 851770 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3902549 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4473858 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8976 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126855886 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42929 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3902549 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18614164 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1601921 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 162955 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21830794 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4713685 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123685119 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 281691 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3991082 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 144136379 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 538783715 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 538776344 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7371 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36706897 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6470 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6468 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 10859255 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29577544 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5541374 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2075747 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1267218 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118433426 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10344 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105554764 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 73541 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26995758 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 66330940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 50826068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.076784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.959181 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17311609 30.40% 30.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13029602 22.88% 53.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8527913 14.98% 68.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6948954 12.20% 80.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5271164 9.26% 89.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2793517 4.91% 94.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2152448 3.78% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 481434 0.85% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 429182 0.75% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13833219 27.22% 27.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10749724 21.15% 48.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7931783 15.61% 63.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6457025 12.70% 76.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4857915 9.56% 86.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3493885 6.87% 93.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2371067 4.67% 97.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 608688 1.20% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 522762 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 56945823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 50826068 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 40477 6.05% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 349114 52.21% 58.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 279085 41.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 142420 18.36% 18.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 354766 45.74% 64.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 278332 35.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74715129 70.68% 70.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10969 0.01% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 226 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 287 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25832645 24.44% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5143450 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74645911 70.72% 70.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10962 0.01% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 239 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 298 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25762945 24.41% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5134404 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105702713 # Type of FU issued -system.cpu.iq.rate 1.854069 # Inst issue rate -system.cpu.iq.fu_busy_cnt 668703 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006326 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 269098152 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146861999 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102960296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1111 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1652 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 475 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106370866 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 550 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 430808 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105554764 # Type of FU issued +system.cpu.iq.rate 2.075194 # Inst issue rate +system.cpu.iq.fu_busy_cnt 775545 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262783539 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 145440732 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102807034 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1143 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1553 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 495 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106329739 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 570 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 435536 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7260915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7599 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4486 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 814071 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7001666 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7849 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3639 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 794618 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 165011 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 13641 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4038541 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 891747 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 116973 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119175285 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342275 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29836795 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5560829 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6480 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49074 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15714 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4486 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 478618 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 473981 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 952599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104642381 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25500898 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1060332 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3902549 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 96175 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18780 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118456487 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 345131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29577544 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5541374 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6439 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4987 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4015 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3639 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 474441 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 478533 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 952974 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104393226 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25307547 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1161538 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12716 # number of nop insts executed -system.cpu.iew.exec_refs 30579562 # number of memory reference insts executed -system.cpu.iew.exec_branches 21366362 # Number of branches executed -system.cpu.iew.exec_stores 5078664 # Number of stores executed -system.cpu.iew.exec_rate 1.835471 # Inst execution rate -system.cpu.iew.wb_sent 103249709 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102960771 # cumulative count of insts written-back -system.cpu.iew.wb_producers 61941288 # num instructions producing a value -system.cpu.iew.wb_consumers 102916553 # num instructions consuming a value +system.cpu.iew.exec_nop 12717 # number of nop insts executed +system.cpu.iew.exec_refs 30377969 # number of memory reference insts executed +system.cpu.iew.exec_branches 21353332 # Number of branches executed +system.cpu.iew.exec_stores 5070422 # Number of stores executed +system.cpu.iew.exec_rate 2.052359 # Inst execution rate +system.cpu.iew.wb_sent 103118433 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102807529 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62180383 # num instructions producing a value +system.cpu.iew.wb_consumers 104132992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.805975 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.601859 # average fanout of values written-back +system.cpu.iew.wb_rate 2.021184 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.597125 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27915285 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 881077 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52907283 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.724952 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.476924 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 27194508 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 878429 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 46923520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.944921 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.520501 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22917585 43.32% 43.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13525297 25.56% 68.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4253401 8.04% 76.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3602316 6.81% 83.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1554565 2.94% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 724715 1.37% 88.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 894547 1.69% 89.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 264490 0.50% 90.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5170367 9.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16620645 35.42% 35.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13501207 28.77% 64.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4487454 9.56% 73.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3864489 8.24% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1521327 3.24% 85.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 782022 1.67% 86.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 855558 1.82% 88.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 262372 0.56% 89.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5028446 10.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52907283 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611977 # Number of instructions committed -system.cpu.commit.committedOps 91262530 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 46923520 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611967 # Number of instructions committed +system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322638 # Number of memory references committed -system.cpu.commit.loads 22575880 # Number of loads committed +system.cpu.commit.refs 27322634 # Number of memory references committed +system.cpu.commit.loads 22575878 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18734218 # Number of branches committed +system.cpu.commit.branches 18734216 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533330 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5170367 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5028446 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 166908997 # The number of ROB reads -system.cpu.rob.rob_writes 242415249 # The number of ROB writes -system.cpu.timesIdled 17140 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65372 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599368 # Number of Instructions Simulated -system.cpu.committedOps 91249921 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599368 # Number of Instructions Simulated -system.cpu.cpi 0.629267 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.629267 # CPI: Total CPI of All Threads -system.cpu.ipc 1.589150 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.589150 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 497539806 # number of integer regfile reads -system.cpu.int_regfile_writes 120848373 # number of integer regfile writes -system.cpu.fp_regfile_reads 239 # number of floating regfile reads -system.cpu.fp_regfile_writes 624 # number of floating regfile writes -system.cpu.misc_regfile_reads 183493284 # number of misc regfile reads -system.cpu.misc_regfile_writes 11612 # number of misc regfile writes +system.cpu.rob.rob_reads 160346368 # The number of ROB reads +system.cpu.rob.rob_writes 240838970 # The number of ROB writes +system.cpu.timesIdled 1282 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 38931 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599358 # Number of Instructions Simulated +system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated +system.cpu.cpi 0.561428 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561428 # CPI: Total CPI of All Threads +system.cpu.ipc 1.781173 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.781173 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496237676 # number of integer regfile reads +system.cpu.int_regfile_writes 120715642 # number of integer regfile writes +system.cpu.fp_regfile_reads 235 # number of floating regfile reads +system.cpu.fp_regfile_writes 643 # number of floating regfile writes +system.cpu.misc_regfile_reads 182128613 # number of misc regfile reads +system.cpu.misc_regfile_writes 11608 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 636.231301 # Cycle average of tags in use -system.cpu.icache.total_refs 14121140 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 635.871073 # Cycle average of tags in use +system.cpu.icache.total_refs 14018279 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 738 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19134.336043 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18994.957995 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 636.231301 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310660 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310660 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14121140 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14121140 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14121140 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14121140 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14121140 # number of overall hits -system.cpu.icache.overall_hits::total 14121140 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 986 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 986 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 986 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 986 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 986 # number of overall misses -system.cpu.icache.overall_misses::total 986 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35670500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35670500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35670500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35670500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35670500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35670500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14122126 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14122126 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14122126 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14122126 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14122126 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14122126 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 635.871073 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310484 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310484 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14018279 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14018279 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14018279 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14018279 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14018279 # number of overall hits +system.cpu.icache.overall_hits::total 14018279 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 981 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 981 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 981 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 981 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 981 # number of overall misses +system.cpu.icache.overall_misses::total 981 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34205000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34205000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34205000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34205000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34205000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34205000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14019260 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14019260 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14019260 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14019260 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14019260 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14019260 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36176.977688 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36176.977688 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36176.977688 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36176.977688 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34867.482161 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34867.482161 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34867.482161 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34867.482161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34867.482161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34867.482161 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,246 +390,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 738 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 738 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 738 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 738 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26658000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26658000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26658000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26658000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26658000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26658000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36121.951220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36121.951220 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26308000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26308000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35647.696477 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35647.696477 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35647.696477 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35647.696477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35647.696477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35647.696477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943542 # number of replacements -system.cpu.dcache.tagsinuse 3691.655008 # Cycle average of tags in use -system.cpu.dcache.total_refs 28378395 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947638 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.946451 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8118725000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3691.655008 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.901283 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.901283 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23798260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23798260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4568472 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4568472 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5862 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5862 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28366732 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28366732 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28366732 # number of overall hits -system.cpu.dcache.overall_hits::total 28366732 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1060889 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1060889 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 166509 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 166509 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1227398 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1227398 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1227398 # number of overall misses -system.cpu.dcache.overall_misses::total 1227398 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21973475500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21973475500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6211010261 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6211010261 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 161000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 161000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28184485761 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28184485761 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28184485761 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28184485761 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24859149 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24859149 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943636 # number of replacements +system.cpu.dcache.tagsinuse 3643.742201 # Cycle average of tags in use +system.cpu.dcache.total_refs 28404607 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947732 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.971138 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8103531000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3643.742201 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.889585 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.889585 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23813813 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23813813 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4579150 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4579150 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5845 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5845 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28392963 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28392963 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28392963 # number of overall hits +system.cpu.dcache.overall_hits::total 28392963 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 995922 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 995922 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 155831 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 155831 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1151753 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1151753 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1151753 # number of overall misses +system.cpu.dcache.overall_misses::total 1151753 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4102006500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4102006500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4011864060 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4011864060 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 120000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 120000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8113870560 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8113870560 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8113870560 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8113870560 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24809735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24809735 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5870 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5870 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29594130 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29594130 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29594130 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29594130 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042676 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.042676 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.035166 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001363 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001363 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.041474 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.041474 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.041474 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.041474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20712.322873 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20712.322873 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37301.348642 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37301.348642 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22962.792640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22962.792640 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 78891432 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5852 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5852 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29544716 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29544716 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29544716 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29544716 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040142 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040142 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032911 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032911 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001196 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001196 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038983 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038983 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038983 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038983 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4118.802979 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 4118.802979 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25744.967689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25744.967689 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7044.800890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7044.800890 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8960217 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9153 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8619.188463 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1374.477220 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942894 # number of writebacks -system.cpu.dcache.writebacks::total 942894 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148366 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 148366 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131394 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 131394 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 279760 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 279760 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 279760 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 279760 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912523 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 912523 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35115 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 35115 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16758552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16758552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1752488893 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1752488893 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18511040893 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18511040893 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18511040893 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18511040893 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036708 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036708 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007416 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007416 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18365.073538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18365.073538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49907.130656 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49907.130656 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 943006 # number of writebacks +system.cpu.dcache.writebacks::total 943006 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82809 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 82809 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 121212 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 121212 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 204021 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 204021 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 204021 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 204021 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 913113 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 913113 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 34619 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 34619 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947732 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947732 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947732 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947732 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1880225500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1880225500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 702020509 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 702020509 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2582246009 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2582246009 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2582246009 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2582246009 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036805 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036805 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007311 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007311 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2059.137807 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2059.137807 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20278.474508 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20278.474508 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2724.658457 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 2724.658457 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2724.658457 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 2724.658457 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10969.237336 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1839897 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15502 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.687718 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10473.281508 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1840746 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15498 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.773132 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10112.492667 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 621.566782 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 235.177887 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.308609 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018969 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007177 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.334755 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 912096 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 912120 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942894 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942894 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 20725 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 20725 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932821 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932845 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932821 # number of overall hits -system.cpu.l2cache.overall_hits::total 932845 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 714 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 282 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 996 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 14535 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14535 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 714 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15531 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 714 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses -system.cpu.l2cache.overall_misses::total 15531 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25532000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10374000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 35906000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499788500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 499788500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25532000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 510162500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 535694500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25532000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 510162500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 535694500 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 9624.671236 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 619.272725 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 229.337548 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.293722 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018899 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.006999 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.319619 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 912835 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 912861 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 943006 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 943006 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 20082 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 20082 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932917 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932943 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932917 # number of overall hits +system.cpu.l2cache.overall_hits::total 932943 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 712 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 277 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 989 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 712 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14815 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15527 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 712 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses +system.cpu.l2cache.overall_misses::total 15527 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25530000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10241500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 35771500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499278500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 499278500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25530000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 509520000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 535050000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25530000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 509520000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 535050000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 738 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 912378 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 913116 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942894 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942894 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 35260 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 35260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 913112 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 913850 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 943006 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 943006 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 34620 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 34620 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 738 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947638 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948376 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947732 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948470 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 738 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947638 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948376 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967480 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412223 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.412223 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967480 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016376 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967480 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016376 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35759.103641 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36787.234043 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36050.200803 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34385.173719 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34385.173719 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34491.951581 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34491.951581 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 947732 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948470 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964770 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000303 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001082 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.419931 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.419931 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964770 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015632 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016371 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964770 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015632 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016371 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35856.741573 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36972.924188 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36169.362993 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34342.997661 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34342.997661 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35856.741573 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34392.170098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34459.328911 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35856.741573 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34392.170098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34459.328911 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,50 +647,50 @@ system.cpu.l2cache.demand_mshr_hits::total 12 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 712 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14535 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14535 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 712 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15519 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 712 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9198500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32438500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 453435000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 453435000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 485873500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462633500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 485873500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001078 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412223 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412223 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.449438 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33818.014706 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32965.955285 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.078431 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.078431 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 710 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 267 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 977 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 710 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15515 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 710 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15515 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23238000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9078500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32316500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 451969500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 451969500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23238000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 461048000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 484286000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23238000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 461048000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 484286000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001069 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016358 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016358 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32729.577465 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34001.872659 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33077.277380 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31088.836154 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31088.836154 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32729.577465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31141.371158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31214.050918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32729.577465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31141.371158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31214.050918 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |